--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_adc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Analog to Digital Convertor (ADC) peripheral: \r
+ * - Initialization and Configuration\r
+ * - Power saving\r
+ * - Analog Watchdog configuration \r
+ * - Temperature Sensor & Vrefint (Voltage Reference internal) management \r
+ * - Regular Channels Configuration\r
+ * - Regular Channels DMA Configuration\r
+ * - Injected channels Configuration \r
+ * - Interrupts and flags management \r
+ * \r
+ * @verbatim\r
+ * \r
+ * =================================================================== \r
+ * How to use this driver\r
+ * =================================================================== \r
+ * - Configure the ADC Prescaler, conversion resolution and data \r
+ * alignment using the ADC_Init() function.\r
+ * - Activate the ADC peripheral using ADC_Cmd() function. \r
+ *\r
+ * Regular channels group configuration\r
+ * ==================================== \r
+ * - To configure the ADC regular channels group features, use \r
+ * ADC_Init() and ADC_RegularChannelConfig() functions.\r
+ * - To activate the continuous mode, use the ADC_continuousModeCmd()\r
+ * function.\r
+ * - To configurate and activate the Discontinuous mode, use the \r
+ * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. \r
+ * - To read the ADC converted values, use the ADC_GetConversionValue()\r
+ * function.\r
+ *\r
+ * DMA for Regular channels group features configuration\r
+ * ====================================================== \r
+ * - To enable the DMA mode for regular channels group, use the \r
+ * ADC_DMACmd() function.\r
+ * - To enable the generation of DMA requests continuously at the end\r
+ * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() \r
+ * function. \r
+ \r
+ * Injected channels group configuration\r
+ * ===================================== \r
+ * - To configure the ADC Injected channels group features, use \r
+ * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()\r
+ * functions.\r
+ * - To activate the continuous mode, use the ADC_continuousModeCmd()\r
+ * function.\r
+ * - To activate the Injected Discontinuous mode, use the \r
+ * ADC_InjectedDiscModeCmd() function. \r
+ * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() \r
+ * function. \r
+ * - To read the ADC converted values, use the ADC_GetInjectedConversionValue() \r
+ * function.\r
+ * \r
+ * @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_adc.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC \r
+ * @brief ADC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ADC DISCNUM mask */\r
+#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)\r
+ \r
+/* ADC AWDCH mask */\r
+#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) \r
+ \r
+/* ADC Analog watchdog enable mode mask */\r
+#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)\r
+ \r
+/* CR1 register Mask */\r
+#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) \r
+ \r
+/* ADC DELAY mask */ \r
+#define CR2_DELS_RESET ((uint32_t)0xFFFFFF0F)\r
+ \r
+/* ADC JEXTEN mask */\r
+#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)\r
+ \r
+/* ADC JEXTSEL mask */\r
+#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)\r
+ \r
+/* CR2 register Mask */\r
+#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)\r
+\r
+/* ADC SQx mask */\r
+#define SQR5_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR4_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR3_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR2_SQ_SET ((uint32_t)0x0000001F) \r
+#define SQR1_SQ_SET ((uint32_t)0x0000001F)\r
+\r
+/* ADC L Mask */\r
+#define SQR1_L_RESET ((uint32_t)0xFE0FFFFF) \r
+\r
+/* ADC JSQx mask */\r
+#define JSQR_JSQ_SET ((uint32_t)0x0000001F) \r
+ \r
+/* ADC JL mask */\r
+#define JSQR_JL_SET ((uint32_t)0x00300000) \r
+#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) \r
+\r
+/* ADC SMPx mask */\r
+#define SMPR1_SMP_SET ((uint32_t)0x00000007) \r
+#define SMPR2_SMP_SET ((uint32_t)0x00000007)\r
+#define SMPR3_SMP_SET ((uint32_t)0x00000007) \r
+\r
+/* ADC JDRx registers offset */\r
+#define JDR_OFFSET ((uint8_t)0x30) \r
+ \r
+/* ADC CCR register Mask */\r
+#define CR_CLEAR_MASK ((uint32_t)0xFFFCFFFF) \r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Initialization and Configuration functions\r
+ =============================================================================== \r
+ This section provides functions allowing to:\r
+ - Initialize and configure the ADC Prescaler\r
+ - ADC Conversion Resolution (12bit..6bit)\r
+ - Scan Conversion Mode (multichannels or one channel) for regular group\r
+ - ADC Continuous Conversion Mode (Continuous or Single conversion) for regular group\r
+ - External trigger Edge and source of regular group, \r
+ - Converted data alignment (left or right)\r
+ - The number of ADC conversions that will be done using the sequencer for regular channel group\r
+ - Enable or disable the ADC peripheral\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes ADC1 peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ADC_DeInit(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ \r
+ /* Enable ADC1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);\r
+ /* Release ADC1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADCx peripheral according to the specified parameters\r
+ * in the ADC_InitStruct.\r
+ * @note This function is used to configure the global features of the ADC ( \r
+ * Resolution and Data Alignment), however, the rest of the configuration\r
+ * parameters are specific to the regular channels group (scan mode \r
+ * activation, continuous mode activation, External trigger source and \r
+ * edge, number of conversion in the regular channels group sequencer). \r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains \r
+ * the configuration information for the specified ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) \r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint8_t tmpreg2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); \r
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); \r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); \r
+ assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); \r
+ assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); \r
+ assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));\r
+ \r
+ /*---------------------------- ADCx CR1 Configuration -----------------*/\r
+ /* Get the ADCx CR1 value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear RES and SCAN bits */ \r
+ tmpreg1 &= CR1_CLEAR_MASK;\r
+ /* Configure ADCx: scan conversion mode and resolution */\r
+ /* Set SCAN bit according to ADC_ScanConvMode value */\r
+ /* Set RES bit according to ADC_Resolution value */ \r
+ tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | ADC_InitStruct->ADC_Resolution);\r
+ /* Write to ADCx CR1 */\r
+ ADCx->CR1 = tmpreg1;\r
+ \r
+ /*---------------------------- ADCx CR2 Configuration -----------------*/\r
+ /* Get the ADCx CR2 value */\r
+ tmpreg1 = ADCx->CR2;\r
+ /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */\r
+ tmpreg1 &= CR2_CLEAR_MASK;\r
+ /* Configure ADCx: external trigger event and edge, data alignment and continuous conversion mode */\r
+ /* Set ALIGN bit according to ADC_DataAlign value */\r
+ /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ \r
+ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */\r
+ /* Set CONT bit according to ADC_ContinuousConvMode value */\r
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | \r
+ ADC_InitStruct->ADC_ExternalTrigConvEdge | ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));\r
+ /* Write to ADCx CR2 */\r
+ ADCx->CR2 = tmpreg1;\r
+ \r
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/\r
+ /* Get the ADCx SQR1 value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Clear L bits */\r
+ tmpreg1 &= SQR1_L_RESET;\r
+ /* Configure ADCx: regular channel sequence length */\r
+ /* Set L bits according to ADC_NbrOfConversion value */ \r
+ tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);\r
+ tmpreg1 |= ((uint32_t)tmpreg2 << 20);\r
+ /* Write to ADCx SQR1 */\r
+ ADCx->SQR1 = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each ADC_InitStruct member with its default value.\r
+ * @note This function is used to initialize the global features of the ADC ( \r
+ * Resolution and Data Alignment), however, the rest of the configuration\r
+ * parameters are specific to the regular channels group (scan mode \r
+ * activation, continuous mode activation, External trigger source and \r
+ * edge, number of conversion in the regular channels group sequencer). \r
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) \r
+{\r
+ /* Reset ADC init structure parameters values */\r
+ /* Initialize the ADC_Resolution member */\r
+ ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;\r
+\r
+ /* Initialize the ADC_ScanConvMode member */\r
+ ADC_InitStruct->ADC_ScanConvMode = DISABLE;\r
+\r
+ /* Initialize the ADC_ContinuousConvMode member */\r
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;\r
+\r
+ /* Initialize the ADC_ExternalTrigConvEdge member */\r
+ ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;\r
+\r
+ /* Initialize the ADC_ExternalTrigConv member */\r
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T2_CC2;\r
+\r
+ /* Initialize the ADC_DataAlign member */\r
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;\r
+\r
+ /* Initialize the ADC_NbrOfConversion member */\r
+ ADC_InitStruct->ADC_NbrOfConversion = 1;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADCs peripherals according to the specified parameters\r
+ * in the ADC_CommonInitStruct.\r
+ * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure \r
+ * that contains the configuration information (Prescaler) for ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) \r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));\r
+\r
+ /*---------------------------- ADC CCR Configuration -----------------*/\r
+ /* Get the ADC CCR value */\r
+ tmpreg = ADC->CCR;\r
+\r
+ /* Clear ADCPRE bit */ \r
+ tmpreg &= CR_CLEAR_MASK;\r
+ \r
+ /* Configure ADCx: ADC prescaler according to ADC_Prescaler */ \r
+ tmpreg |= (uint32_t)(ADC_CommonInitStruct->ADC_Prescaler); \r
+ \r
+ /* Write to ADC CCR */\r
+ ADC->CCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each ADC_CommonInitStruct member with its default value.\r
+ * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure\r
+ * which will be initialized.\r
+ * @retval None\r
+ */\r
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) \r
+{\r
+ /* Reset ADC init structure parameters values */\r
+ /* Initialize the ADC_Prescaler member */\r
+ ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div1;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC peripheral.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the ADCx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ADON bit to wake up the ADC from power down mode */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC peripheral */\r
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group2 Power saving functions\r
+ * @brief Power saving functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Power saving functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to reduce power consumption.\r
+ The two function must be combined to get the maximal benefits:\r
+ When the ADC frequency is higher than the CPU one, it is recommended to \r
+ 1. Insert a freeze delay : \r
+ ==> using ADC_DelaySelectionConfig(ADC1, ADC_DelayLength_Freeze);\r
+ 2. Enable the power down in Idle and Delay phases :\r
+ ==> using ADC_PowerDownCmd(ADC1, ADC_PowerDown_Idle_Delay, ENABLE);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the ADC Power Down during Delay and/or Idle phase.\r
+ * @note ADC power-on and power-off can be managed by hardware to cut the \r
+ * consumption when the ADC is not converting. \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_PowerDown: The ADC power down configuration. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_PowerDown_Delay: ADC is powered down during delay phase \r
+ * @arg ADC_PowerDown_Idle: ADC is powered down during Idle phase \r
+ * @arg ADC_PowerDown_Idle_Delay: ADC is powered down during Delay and Idle phases\r
+ * @note The ADC can be powered down: \r
+ * - During the hardware delay insertion (using the ADC_PowerDown_Delay\r
+ * parameter) \r
+ * => The ADC is powered up again at the end of the delay. \r
+ * - During the ADC is waiting for a trigger event ( using the \r
+ * ADC_PowerDown_Idle parameter) \r
+ * => The ADC is powered up at the next trigger event.\r
+ * - During the hardware delay insertion or the ADC is waiting for a \r
+ * trigger event (using the ADC_PowerDown_Idle_Delay parameter) \r
+ * => The ADC is powered up only at the end of the delay and at the \r
+ * next trigger event. \r
+ * @param NewState: new state of the ADCx power down. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_ADC_POWER_DOWN(ADC_PowerDown));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the ADC power-down during Delay and/or Idle phase */\r
+ ADCx->CR1 |= ADC_PowerDown;\r
+ }\r
+ else\r
+ {\r
+ /* Disable The ADC power-down during Delay and/or Idle phase */\r
+ ADCx->CR1 &= (uint32_t)~ADC_PowerDown;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Defines the length of the delay which is applied after a conversion \r
+ * or a sequence of conversion.\r
+ * @note When the CPU clock is not fast enough to manage the data rate, a \r
+ * Hardware delay can be introduced between ADC conversions to reduce \r
+ * this data rate. \r
+ * @note The Hardware delay is inserted after :\r
+ * - each regular conversion\r
+ * - after each sequence of injected conversions\r
+ * @note No Hardware delay is inserted between conversions of different groups.\r
+ * @note When the hardware delay is not enough, the Freeze Delay Mode can be \r
+ * selected and a new conversion can start only if all the previous data \r
+ * of the same group have been treated:\r
+ * - for a regular conversion: once the ADC conversion data register has \r
+ * been read (using ADC_GetConversionValue() function) or if the EOC \r
+ * Flag has been cleared (using ADC_ClearFlag() function).\r
+ * - for an injected conversion: when the JEOC bit has been cleared \r
+ * (using ADC_ClearFlag() function).\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_DelayLength: The length of delay which is applied after a \r
+ * conversion or a sequence of conversion. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_DelayLength_None: No delay \r
+ * @arg ADC_DelayLength_Freeze: Delay until the converted data has been read.\r
+ * @arg ADC_DelayLength_7Cycles: Delay length equal to 7 APB clock cycles\r
+ * @arg ADC_DelayLength_15Cycles: Delay length equal to 15 APB clock cycles \r
+ * @arg ADC_DelayLength_31Cycles: Delay length equal to 31 APB clock cycles \r
+ * @arg ADC_DelayLength_63Cycles: Delay length equal to 63 APB clock cycles \r
+ * @arg ADC_DelayLength_127Cycles: Delay length equal to 127 APB clock cycles \r
+ * @arg ADC_DelayLength_255Cycles: Delay length equal to 255 APB clock cycles \r
+ * @retval None\r
+ */\r
+void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_DELAY_LENGTH(ADC_DelayLength));\r
+\r
+ /* Get the old register value */ \r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old delay length */\r
+ tmpreg &= CR2_DELS_RESET;\r
+ /* Set the delay length */\r
+ tmpreg |= ADC_DelayLength;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group3 Analog Watchdog configuration functions\r
+ * @brief Analog Watchdog configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Analog Watchdog configuration functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to configure the Analog Watchdog\r
+ (AWD) feature in the ADC.\r
+ \r
+ A typical configuration Analog Watchdog is done following these steps :\r
+ 1. the ADC guarded channel(s) is (are) selected using the \r
+ ADC_AnalogWatchdogSingleChannelConfig() function.\r
+ 2. The Analog watchdog lower and higher threshold are configured using the \r
+ ADC_AnalogWatchdogThresholdsConfig() function.\r
+ 3. The Analog watchdog is enabled and configured to enable the check, on one\r
+ or more channels, using the ADC_AnalogWatchdogCmd() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables or disables the analog watchdog on single/all regular\r
+ * or injected channels\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single \r
+ * regular channel\r
+ * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single \r
+ * injected channel\r
+ * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a \r
+ * single regular or injected channel \r
+ * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular \r
+ * channel\r
+ * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected \r
+ * channel\r
+ * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all \r
+ * regular and injected channels\r
+ * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog\r
+ * @retval None \r
+ */\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear AWDEN, JAWDEN and AWDSGL bits */ \r
+ tmpreg &= CR1_AWDMODE_RESET;\r
+ /* Set the analog watchdog enable mode */\r
+ tmpreg |= ADC_AnalogWatchdog;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the high and low thresholds of the analog watchdog. \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param HighThreshold: the ADC analog watchdog High threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,\r
+ uint16_t LowThreshold)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_THRESHOLD(HighThreshold));\r
+ assert_param(IS_ADC_THRESHOLD(LowThreshold));\r
+\r
+ /* Set the ADCx high threshold */\r
+ ADCx->HTR = HighThreshold;\r
+ /* Set the ADCx low threshold */\r
+ ADCx->LTR = LowThreshold;\r
+}\r
+\r
+/**\r
+ * @brief Configures the analog watchdog guarded single channel\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_Channel_18: ADC Channel18 selected\r
+ * @arg ADC_Channel_19: ADC Channel19 selected\r
+ * @arg ADC_Channel_20: ADC Channel20 selected\r
+ * @arg ADC_Channel_21: ADC Channel21 selected\r
+ * @arg ADC_Channel_22: ADC Channel22 selected\r
+ * @arg ADC_Channel_23: ADC Channel23 selected\r
+ * @arg ADC_Channel_24: ADC Channel24 selected\r
+ * @arg ADC_Channel_25: ADC Channel25 selected\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear the Analog watchdog channel select bits */\r
+ tmpreg &= CR1_AWDCH_RESET;\r
+ /* Set the Analog watchdog channel */\r
+ tmpreg |= ADC_Channel;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group4 Temperature Sensor & Vrefint (Voltage Reference internal) management function\r
+ * @brief Temperature Sensor & Vrefint (Voltage Reference internal) management function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Temperature Sensor & Vrefint (Voltage Reference internal) management function\r
+ =============================================================================== \r
+\r
+ This section provides a function allowing to enable/ disable the internal \r
+ connections between the ADC and the Temperature Sensor and the Vrefint source.\r
+ \r
+ A typical configuration to get the Temperature sensor and Vrefint channels \r
+ voltages or is done following these steps :\r
+ 1. Enable the internal connection of Temperature sensor and Vrefint sources \r
+ with the ADC channels using ADC_TempSensorVrefintCmd() function. \r
+ 2. select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using \r
+ ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions \r
+ 3. Get the voltage values, using ADC_GetConversionValue() or \r
+ ADC_GetInjectedConversionValue().\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables or disables the temperature sensor and Vrefint channel.\r
+ * @param NewState: new state of the temperature sensor and Vref int channels.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the temperature sensor and Vrefint channel*/\r
+ ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the temperature sensor and Vrefint channel*/\r
+ ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group5 Regular Channels Configuration functions\r
+ * @brief Regular Channels Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Regular Channels Configuration functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to manage the ADC regular channels,\r
+ it is composed of 2 sub sections : \r
+ \r
+ 1. Configuration and management functions for regular channels: This subsection \r
+ provides functions allowing to configure the ADC regular channels : \r
+ - Configure the rank in the regular group sequencer for each channel\r
+ - Configure the sampling time for each channel\r
+ - select the conversion Trigger for regular channels\r
+ - select the desired EOC event behavior configuration\r
+ - Activate the continuous Mode (*)\r
+ - Activate the Discontinuous Mode \r
+ Please Note that the following features for regular channels are configurated\r
+ using the ADC_Init() function : \r
+ - scan mode activation \r
+ - continuous mode activation (**) \r
+ - External trigger source \r
+ - External trigger edge \r
+ - number of conversion in the regular channels group sequencer.\r
+ \r
+ @note : (*) and (**) are performing the same configuration\r
+ \r
+ 2. Get the conversion data: This subsection provides an important function in \r
+ the ADC peripheral since it returns the converted data of the current \r
+ regular channel. When the Conversion value is read, the EOC Flag is \r
+ automatically cleared.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures for the selected ADC regular channel its corresponding\r
+ * rank in the sequencer and its sampling time.\r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_Channel_18: ADC Channel18 selected \r
+ * @arg ADC_Channel_19: ADC Channel19 selected\r
+ * @arg ADC_Channel_20: ADC Channel20 selected\r
+ * @arg ADC_Channel_21: ADC Channel21 selected\r
+ * @arg ADC_Channel_22: ADC Channel22 selected\r
+ * @arg ADC_Channel_23: ADC Channel23 selected\r
+ * @arg ADC_Channel_24: ADC Channel24 selected\r
+ * @arg ADC_Channel_25: ADC Channel25 selected\r
+ * @param Rank: The rank in the regular group sequencer. This parameter\r
+ * must be between 1 to 26.\r
+ * @param ADC_SampleTime: The sample time value to be set for the selected \r
+ * channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles \r
+ * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles\r
+ * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles\r
+ * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles \r
+ * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles \r
+ * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles \r
+ * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles \r
+ * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles \r
+ * @retval None\r
+ */\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert_param(IS_ADC_REGULAR_RANK(Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+\r
+ /* if ADC_Channel_20 ... ADC_Channel_25 is selected */\r
+ if (ADC_Channel > ADC_Channel_19)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ }\r
+ \r
+ /* if ADC_Channel_10 ... ADC_Channel_19 is selected */\r
+ else if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+ \r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR3 = tmpreg1;\r
+ }\r
+ /* For Rank 1 to 6 */\r
+ if (Rank < 7)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR5;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR5_SQ_SET << (5 * (Rank - 1));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR5 = tmpreg1;\r
+ }\r
+ /* For Rank 7 to 12 */\r
+ else if (Rank < 13)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR4;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR4_SQ_SET << (5 * (Rank - 7));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR4 = tmpreg1;\r
+ } \r
+ /* For Rank 13 to 18 */\r
+ else if (Rank < 19)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 13));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR3 = tmpreg1;\r
+ }\r
+ \r
+ /* For Rank 19 to 24 */\r
+ else if (Rank < 25)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 19));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 19));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR2 = tmpreg1;\r
+ } \r
+ \r
+ /* For Rank 25 to 27 */\r
+ else\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 25));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 25));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR1 = tmpreg1;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the selected ADC software start conversion of the regular channels.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Enable the selected ADC conversion for regular group */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC Software start regular conversion Status.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval The new state of ADC software start conversion (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Check the status of SWSTART bit */\r
+ if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET)\r
+ {\r
+ /* SWSTART bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SWSTART bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SWSTART bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the EOC on each regular channel conversion\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC EOC flag rising\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC EOC rising on each regular channel conversion */\r
+ ADCx->CR2 |= ADC_CR2_EOCS;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC EOC rising on each regular channel conversion */\r
+ ADCx->CR2 &= (uint32_t)~ADC_CR2_EOCS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the ADC continuous conversion mode \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC continuous conversion mode\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC continuous conversion mode */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC continuous conversion mode */\r
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the discontinuous mode for the selected ADC regular\r
+ * group channel.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param Number: specifies the discontinuous mode regular channel count value. \r
+ * This number must be between 1 and 8.\r
+ * @retval None\r
+ */\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));\r
+\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear the old discontinuous mode channel count */\r
+ tmpreg1 &= CR1_DISCNUM_RESET;\r
+ /* Set the discontinuous mode channel count */\r
+ tmpreg2 = Number - 1;\r
+ tmpreg1 |= tmpreg2 << 13;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the discontinuous mode on regular group\r
+ * channel for the specified ADC\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC discontinuous mode on regular \r
+ * group channel. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the last ADCx conversion result data for regular channel. \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval The Data conversion value.\r
+ */\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Return the selected ADC conversion value */\r
+ return (uint16_t) ADCx->DR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group6 Regular Channels DMA Configuration functions\r
+ * @brief Regular Channels DMA Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Regular Channels DMA Configuration functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to configure the DMA for ADC regular \r
+ channels.\r
+ Since converted regular channel values are stored into a unique data register, \r
+ it is useful to use DMA for conversion of more than one regular channel. This \r
+ avoids the loss of the data already stored in the ADC Data register. \r
+ \r
+ When the DMA mode is enabled (using the ADC_DMACmd() function), after each\r
+ conversion of a regular channel, a DMA request is generated.\r
+ \r
+ Depending on the "DMA disable selection" configuration (using the \r
+ ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA \r
+ transfer, two possibilities are allowed:\r
+ - No new DMA request is issued to the DMA controller (feature DISABLED) \r
+ - Requests can continue to be generated (feature ENABLED).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC DMA request.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC DMA transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_DMA_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC DMA request */\r
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC EOC flag rising\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request after last transfer */\r
+ ADCx->CR2 |= ADC_CR2_DDS;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC DMA request after last transfer */\r
+ ADCx->CR2 &= (uint32_t)~ADC_CR2_DDS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group7 Injected channels Configuration functions\r
+ * @brief Injected channels Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Injected channels Configuration functions\r
+ =============================================================================== \r
+\r
+ This section provide functions allowing to configure the ADC Injected channels,\r
+ it is composed of 2 sub sections : \r
+ \r
+ 1. Configuration functions for Injected channels: This subsection provides \r
+ functions allowing to configure the ADC injected channels : \r
+ - Configure the rank in the injected group sequencer for each channel\r
+ - Configure the sampling time for each channel \r
+ - Activate the Auto injected Mode \r
+ - Activate the Discontinuous Mode \r
+ - scan mode activation \r
+ - External/software trigger source \r
+ - External trigger edge \r
+ - injected channels sequencer.\r
+ \r
+ 2. Get the Specified Injected channel conversion data: This subsection \r
+ provides an important function in the ADC peripheral since it returns the \r
+ converted data of the specific injected channel.\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Configures for the selected ADC injected channel its corresponding\r
+ * rank in the sequencer and its sample time.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_Channel_18: ADC Channel18 selected \r
+ * @arg ADC_Channel_19: ADC Channel19 selected\r
+ * @arg ADC_Channel_20: ADC Channel20 selected\r
+ * @arg ADC_Channel_21: ADC Channel21 selected\r
+ * @arg ADC_Channel_22: ADC Channel22 selected\r
+ * @arg ADC_Channel_23: ADC Channel23 selected\r
+ * @arg ADC_Channel_24: ADC Channel24 selected\r
+ * @arg ADC_Channel_25: ADC Channel25 selected\r
+ * @param Rank: The rank in the injected group sequencer. This parameter\r
+ * must be between 1 to 4.\r
+ * @param ADC_SampleTime: The sample time value to be set for the selected \r
+ * channel. This parameter can be one of the following values:\r
+ * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles \r
+ * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles\r
+ * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles\r
+ * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles \r
+ * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles \r
+ * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles \r
+ * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles \r
+ * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles \r
+ * @retval None\r
+ */\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert_param(IS_ADC_INJECTED_RANK(Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+ \r
+ /* if ADC_Channel_20 ... ADC_Channel_25 is selected */\r
+ if (ADC_Channel > ADC_Channel_19)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ }\r
+ \r
+ /* if ADC_Channel_10 ... ADC_Channel_19 is selected */\r
+ else if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+ \r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);\r
+ /* Clear the old sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the new sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR3 = tmpreg1;\r
+ }\r
+ \r
+ /* Rank configuration */\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Get JL value: Number = JL+1 */\r
+ tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;\r
+ /* Calculate the mask to clear: ((Rank-1)+(4- (JL+1))) */ \r
+ tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
+ /* Clear the old JSQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set: ((Rank-1)+(4- (JL+1))) */ \r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
+ /* Set the JSQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the sequencer length for injected channels\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param Length: The sequencer length. \r
+ * This parameter must be a number between 1 to 4.\r
+ * @retval None\r
+ */\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_LENGTH(Length));\r
+ \r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Clear the old injected sequence length JL bits */\r
+ tmpreg1 &= JSQR_JL_RESET;\r
+ /* Set the injected sequence length JL bits */\r
+ tmpreg2 = Length - 1; \r
+ tmpreg1 |= tmpreg2 << 20;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Set the injected channels conversion value offset\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_InjectedChannel: the ADC injected channel to set its offset. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
+ * @param Offset: the offset value for the selected ADC injected channel\r
+ * This parameter must be a 12bit value.\r
+ * @retval None\r
+ */\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+ assert_param(IS_ADC_OFFSET(Offset)); \r
+ \r
+ tmp = (uint32_t)ADCx;\r
+ tmp += ADC_InjectedChannel;\r
+ \r
+ /* Set the selected injected channel data offset */\r
+ *(__IO uint32_t *) tmp = (uint32_t)Offset;\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADCx external trigger for injected channels conversion.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected \r
+ * conversion. This parameter can be one of the following values: \r
+ * @arg ADC_ExternalTrigInjecConv_T9_CC1: Timer9 capture compare1 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T9_TRGO: Timer9 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected\r
+ * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected \r
+ * @arg ADC_ExternalTrigInjecConv_T10_CC1: Timer10 capture compare1 selected\r
+ * @arg ADC_ExternalTrigInjecConv_T7_TRGO: Timer7 TRGO event selected \r
+ * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected \r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old external event selection for injected group */\r
+ tmpreg &= CR2_JEXTSEL_RESET;\r
+ /* Set the external event selection for injected group */\r
+ tmpreg |= ADC_ExternalTrigInjecConv;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADCx external trigger edge for injected channels conversion.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger\r
+ * edge to start injected conversion. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_ExternalTrigConvEdge_None: external trigger disabled for \r
+ * injected conversion\r
+ * @arg ADC_ExternalTrigConvEdge_Rising: detection on rising edge\r
+ * @arg ADC_ExternalTrigConvEdge_Falling: detection on falling edge\r
+ * @arg ADC_External ADC_ExternalTrigConvEdge_RisingFalling: detection on \r
+ * both rising and falling edge\r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old external trigger edge for injected group */\r
+ tmpreg &= CR2_JEXTEN_RESET;\r
+ /* Set the new external trigger edge for injected group */\r
+ tmpreg |= ADC_ExternalTrigInjecConvEdge;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the selected ADC software start conversion of the injected \r
+ * channels.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Enable the selected ADC conversion for injected group */\r
+ ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC Software start injected conversion Status.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval The new state of ADC software start injected conversion (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Check the status of JSWSTART bit */\r
+ if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)\r
+ {\r
+ /* JSWSTART bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* JSWSTART bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the JSWSTART bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected ADC automatic injected group\r
+ * conversion after regular one.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC auto injected\r
+ * conversion. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the discontinuous mode for injected group\r
+ * channel for the specified ADC\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC discontinuous mode\r
+ * on injected group channel. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the ADC injected channel conversion result\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_InjectedChannel: the converted ADC injected channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
+ * @retval The Data conversion value.\r
+ */\r
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+\r
+ tmp = (uint32_t)ADCx;\r
+ tmp += ADC_InjectedChannel + JDR_OFFSET;\r
+ \r
+ /* Returns the selected injected channel conversion data value */\r
+ return (uint16_t) (*(__IO uint32_t*) tmp); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group8 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ Interrupts and flags management functions\r
+ =============================================================================== \r
+\r
+ This section provides functions allowing to configure the ADC Interrupts and get \r
+ the status and clear flags and Interrupts pending bits.\r
+ \r
+ The ADC provide 4 Interrupts sources and 9 Flags which can be divided into 3 groups:\r
+ \r
+ I. Flags and Interrupts for ADC regular channels\r
+ =================================================\r
+ Flags :\r
+ ---------- \r
+ 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost\r
+\r
+ 2. ADC_FLAG_EOC : Regular channel end of conversion + to indicate (depending \r
+ on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of :\r
+ ==> a regular CHANNEL conversion \r
+ ==> sequence of regular GROUP conversions .\r
+\r
+ 3. ADC_FLAG_STRT: Regular channel start + to indicate when regular CHANNEL \r
+ conversion starts.\r
+ \r
+ 4. ADC_FLAG_RCNR: Regular channel not ready+ to indicate if a new regular \r
+ conversion can be launched\r
+ \r
+ Interrupts :\r
+ ------------\r
+ 1. ADC_IT_OVR \r
+ 2. ADC_IT_EOC \r
+ \r
+ \r
+ II. Flags and Interrupts for ADC Injected channels\r
+ =================================================\r
+ Flags :\r
+ ---------- \r
+ 1. ADC_FLAG_JEOC : Injected channel end of conversion+ to indicate at \r
+ the end of injected GROUP conversion \r
+ \r
+ 2. ADC_FLAG_JSTRT: Injected channel start + to indicate hardware when \r
+ injected GROUP conversion starts.\r
+\r
+ 3. ADC_FLAG_JCNR: Injected channel not ready + to indicate if a new \r
+ injected conversion can be launched.\r
+\r
+ Interrupts :\r
+ ------------\r
+ 1. ADC_IT_JEOC \r
+\r
+ III. General Flags and Interrupts for the ADC\r
+ ================================================= \r
+ Flags :\r
+ ---------- \r
+ 1. ADC_FLAG_AWD: Analog watchdog + to indicate if the converted voltage \r
+ crosses the programmed thresholds values.\r
+ \r
+ 2. ADC_FLAG_ADONS: ADC ON status + to indicate if the ADC is ready to convert.\r
+ \r
+ Interrupts :\r
+ ------------\r
+ 1. ADC_IT_AWD \r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC interrupts.\r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt \r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt \r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt \r
+ * @arg ADC_IT_OVR: overrun interrupt \r
+ * @param NewState: new state of the specified ADC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) \r
+{\r
+ uint32_t itmask = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_ADC_IT(ADC_IT)); \r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (uint8_t)ADC_IT;\r
+ itmask = (uint32_t)0x01 << itmask; \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC interrupts */\r
+ ADCx->CR1 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC interrupts */\r
+ ADCx->CR1 &= (~(uint32_t)itmask);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC flag is set or not.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
+ * @arg ADC_FLAG_OVR: Overrun flag \r
+ * @arg ADC_FLAG_ADONS: ADC ON status \r
+ * @arg ADC_FLAG_RCNR: Regular channel not ready \r
+ * @arg ADC_FLAG_JCNR: Injected channel not ready \r
+ * @retval The new state of ADC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_GET_FLAG(ADC_FLAG));\r
+\r
+ /* Check the status of the specified ADC flag */\r
+ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)\r
+ {\r
+ /* ADC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx's pending flags.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
+ * @arg ADC_FLAG_OVR: overrun flag \r
+ * @retval None\r
+ */\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));\r
+\r
+ /* Clear the selected ADC flags */\r
+ ADCx->SR = ~(uint32_t)ADC_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC interrupt has occurred or not.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt \r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt \r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt \r
+ * @arg ADC_IT_OVR: Overrun interrupt \r
+ * @retval The new state of ADC_IT (SET or RESET).\r
+ */\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t itmask = 0, enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_IT(ADC_IT));\r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (uint32_t)((uint32_t)ADC_IT >> 8);\r
+\r
+ /* Get the ADC_IT enable bit status */\r
+ enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)); \r
+\r
+ /* Check the status of the specified ADC interrupt */\r
+ if (((uint32_t)(ADCx->SR & (uint32_t)itmask) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+ { \r
+ /* ADC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx\92s interrupt pending bits.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt \r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt \r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt \r
+ * @arg ADC_IT_OVR: Overrun interrupt \r
+ * @retval None\r
+ */\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
+{\r
+ uint8_t itmask = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_IT(ADC_IT)); \r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (uint8_t)(ADC_IT >> 8);\r
+\r
+ /* Clear the selected ADC interrupt pending bits */\r
+ ADCx->SR = ~(uint32_t)itmask;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff