--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l1xx_adc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 31-December-2010\r
+ * @brief This file contains all the functions prototypes for the ADC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_ADC_H\r
+#define __STM32L1xx_ADC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief ADC Init structure definition \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.\r
+ This parameter can be a value of @ref ADC_Resolution */\r
+ \r
+ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in\r
+ Scan (multichannel) or Single (one channel) mode.\r
+ This parameter can be set to ENABLE or DISABLE */\r
+ \r
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in\r
+ Continuous or Single mode.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+ \r
+ uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the\r
+ trigger of a regular group. This parameter can be a value\r
+ of @ref ADC_external_trigger_edge_for_regular_channels_conversion */\r
+ \r
+ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog\r
+ to digital conversion of regular channels. This parameter\r
+ can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */\r
+ \r
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.\r
+ This parameter can be a value of @ref ADC_data_align */\r
+ \r
+ uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done\r
+ using the sequencer for regular channel group.\r
+ This parameter must range from 1 to 27. */\r
+}ADC_InitTypeDef;\r
+\r
+typedef struct \r
+{ \r
+ uint32_t ADC_Prescaler; /*!< Selects the ADC prescaler.\r
+ This parameter can be a value \r
+ of @ref ADC_Prescaler */\r
+}ADC_CommonInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Exported_Constants\r
+ * @{\r
+ */ \r
+#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)\r
+#define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)\r
+\r
+/** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase \r
+ * @{\r
+ */ \r
+#define ADC_PowerDown_Delay ((uint32_t)0x00010000)\r
+#define ADC_PowerDown_Idle ((uint32_t)0x00020000)\r
+#define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)\r
+\r
+#define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \\r
+ ((DWON) == ADC_PowerDown_Idle) || \\r
+ ((DWON) == ADC_PowerDown_Idle_Delay))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_Prescaler \r
+ * @{\r
+ */ \r
+#define ADC_Prescaler_Div1 ((uint32_t)0x00000000)\r
+#define ADC_Prescaler_Div2 ((uint32_t)0x00010000)\r
+#define ADC_Prescaler_Div4 ((uint32_t)0x00020000)\r
+\r
+#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \\r
+ ((PRESCALER) == ADC_Prescaler_Div2) || \\r
+ ((PRESCALER) == ADC_Prescaler_Div4))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+\r
+/** @defgroup ADC_resolution \r
+ * @{\r
+ */ \r
+#define ADC_Resolution_12b ((uint32_t)0x00000000)\r
+#define ADC_Resolution_10b ((uint32_t)0x01000000)\r
+#define ADC_Resolution_8b ((uint32_t)0x02000000)\r
+#define ADC_Resolution_6b ((uint32_t)0x03000000)\r
+\r
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \\r
+ ((RESOLUTION) == ADC_Resolution_10b) || \\r
+ ((RESOLUTION) == ADC_Resolution_8b) || \\r
+ ((RESOLUTION) == ADC_Resolution_6b))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion \r
+ * @{\r
+ */ \r
+#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)\r
+#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)\r
+#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)\r
+\r
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion\r
+ * @{\r
+ */ \r
+\r
+/* TIM2 */\r
+#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)\r
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)\r
+#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)\r
+\r
+/* TIM3 */\r
+#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)\r
+#define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)\r
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)\r
+\r
+/* TIM4 */\r
+#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)\r
+#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)\r
+\r
+/* TIM6 */\r
+#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)\r
+\r
+/* TIM9 */\r
+#define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)\r
+\r
+/* EXTI */\r
+#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)\r
+\r
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_data_align \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)\r
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)\r
+\r
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\r
+ ((ALIGN) == ADC_DataAlign_Left))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_channels \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_Channel_0 ((uint8_t)0x00)\r
+#define ADC_Channel_1 ((uint8_t)0x01)\r
+#define ADC_Channel_2 ((uint8_t)0x02)\r
+#define ADC_Channel_3 ((uint8_t)0x03)\r
+#define ADC_Channel_4 ((uint8_t)0x04)\r
+#define ADC_Channel_5 ((uint8_t)0x05)\r
+#define ADC_Channel_6 ((uint8_t)0x06)\r
+#define ADC_Channel_7 ((uint8_t)0x07)\r
+#define ADC_Channel_8 ((uint8_t)0x08)\r
+#define ADC_Channel_9 ((uint8_t)0x09)\r
+#define ADC_Channel_10 ((uint8_t)0x0A)\r
+#define ADC_Channel_11 ((uint8_t)0x0B)\r
+#define ADC_Channel_12 ((uint8_t)0x0C)\r
+#define ADC_Channel_13 ((uint8_t)0x0D)\r
+#define ADC_Channel_14 ((uint8_t)0x0E)\r
+#define ADC_Channel_15 ((uint8_t)0x0F)\r
+#define ADC_Channel_16 ((uint8_t)0x10)\r
+#define ADC_Channel_17 ((uint8_t)0x11)\r
+#define ADC_Channel_18 ((uint8_t)0x12)\r
+#define ADC_Channel_19 ((uint8_t)0x13)\r
+#define ADC_Channel_20 ((uint8_t)0x14)\r
+#define ADC_Channel_21 ((uint8_t)0x15)\r
+#define ADC_Channel_22 ((uint8_t)0x16)\r
+#define ADC_Channel_23 ((uint8_t)0x17)\r
+#define ADC_Channel_24 ((uint8_t)0x18)\r
+#define ADC_Channel_25 ((uint8_t)0x19)\r
+\r
+#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)\r
+#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)\r
+\r
+\r
+\r
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \\r
+ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \\r
+ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \\r
+ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \\r
+ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \\r
+ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \\r
+ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \\r
+ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \\r
+ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \\r
+ ((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \\r
+ ((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \\r
+ ((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \\r
+ ((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) )\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_sampling_times \r
+ * @{\r
+ */ \r
+\r
+#define ADC_SampleTime_4Cycles ((uint8_t)0x00)\r
+#define ADC_SampleTime_9Cycles ((uint8_t)0x01)\r
+#define ADC_SampleTime_16Cycles ((uint8_t)0x02)\r
+#define ADC_SampleTime_24Cycles ((uint8_t)0x03)\r
+#define ADC_SampleTime_48Cycles ((uint8_t)0x04)\r
+#define ADC_SampleTime_96Cycles ((uint8_t)0x05)\r
+#define ADC_SampleTime_192Cycles ((uint8_t)0x06)\r
+#define ADC_SampleTime_384Cycles ((uint8_t)0x07)\r
+\r
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles) || \\r
+ ((TIME) == ADC_SampleTime_9Cycles) || \\r
+ ((TIME) == ADC_SampleTime_16Cycles) || \\r
+ ((TIME) == ADC_SampleTime_24Cycles) || \\r
+ ((TIME) == ADC_SampleTime_48Cycles) || \\r
+ ((TIME) == ADC_SampleTime_96Cycles) || \\r
+ ((TIME) == ADC_SampleTime_192Cycles) || \\r
+ ((TIME) == ADC_SampleTime_384Cycles))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_Delay_length \r
+ * @{\r
+ */ \r
+\r
+#define ADC_DelayLength_None ((uint8_t)0x00)\r
+#define ADC_DelayLength_Freeze ((uint8_t)0x10)\r
+#define ADC_DelayLength_7Cycles ((uint8_t)0x20)\r
+#define ADC_DelayLength_15Cycles ((uint8_t)0x30)\r
+#define ADC_DelayLength_31Cycles ((uint8_t)0x40)\r
+#define ADC_DelayLength_63Cycles ((uint8_t)0x50)\r
+#define ADC_DelayLength_127Cycles ((uint8_t)0x60)\r
+#define ADC_DelayLength_255Cycles ((uint8_t)0x70)\r
+\r
+#define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None) || \\r
+ ((LENGTH) == ADC_DelayLength_Freeze) || \\r
+ ((LENGTH) == ADC_DelayLength_7Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_15Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_31Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_63Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_127Cycles) || \\r
+ ((LENGTH) == ADC_DelayLength_255Cycles))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion \r
+ * @{\r
+ */ \r
+#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)\r
+#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)\r
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)\r
+\r
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \\r
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion \r
+ * @{\r
+ */ \r
+\r
+\r
+/* TIM2 */\r
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)\r
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)\r
+\r
+/* TIM3 */\r
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)\r
+\r
+/* TIM4 */\r
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)\r
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)\r
+\r
+/* TIM7 */\r
+#define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)\r
+\r
+/* TIM9 */\r
+#define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)\r
+\r
+/* TIM10 */\r
+#define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)\r
+\r
+/* EXTI */\r
+#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)\r
+\r
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_channel_selection \r
+ * @{\r
+ */ \r
+#define ADC_InjectedChannel_1 ((uint8_t)0x18)\r
+#define ADC_InjectedChannel_2 ((uint8_t)0x1C)\r
+#define ADC_InjectedChannel_3 ((uint8_t)0x20)\r
+#define ADC_InjectedChannel_4 ((uint8_t)0x24)\r
+\r
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_2) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_3) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_4))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_analog_watchdog_selection \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)\r
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)\r
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) \r
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)\r
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)\r
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)\r
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)\r
+\r
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_interrupts_definition \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_IT_AWD ((uint16_t)0x0106) \r
+#define ADC_IT_EOC ((uint16_t)0x0205) \r
+#define ADC_IT_JEOC ((uint16_t)0x0407) \r
+#define ADC_IT_OVR ((uint16_t)0x201A) \r
+ \r
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \\r
+ ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_flags_definition \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_FLAG_AWD ((uint16_t)0x0001)\r
+#define ADC_FLAG_EOC ((uint16_t)0x0002)\r
+#define ADC_FLAG_JEOC ((uint16_t)0x0004)\r
+#define ADC_FLAG_JSTRT ((uint16_t)0x0008)\r
+#define ADC_FLAG_STRT ((uint16_t)0x0010)\r
+#define ADC_FLAG_OVR ((uint16_t)0x0020)\r
+#define ADC_FLAG_ADONS ((uint16_t)0x0040)\r
+#define ADC_FLAG_RCNR ((uint16_t)0x0100)\r
+#define ADC_FLAG_JCNR ((uint16_t)0x0200) \r
+ \r
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))\r
+ \r
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \\r
+ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \\r
+ ((FLAG) == ADC_FLAG_STRT) || ((FLAG)== ADC_FLAG_OVR) || \\r
+ ((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR) || \\r
+ ((FLAG) == ADC_FLAG_JCNR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_thresholds \r
+ * @{\r
+ */ \r
+ \r
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_offset \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_length \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_injected_rank \r
+ * @{\r
+ */ \r
+ \r
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_regular_length \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 27))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_regular_rank \r
+ * @{\r
+ */ \r
+ \r
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x1B))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_regular_discontinuous_mode_number \r
+ * @{\r
+ */\r
+ \r
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the ADC configuration to the default reset state *****/ \r
+void ADC_DeInit(ADC_TypeDef* ADCx); \r
+\r
+/* Initialization and Configuration functions *********************************/ \r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+\r
+/* Power saving functions *****************************************************/\r
+void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState);\r
+void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength);\r
+\r
+/* Analog Watchdog configuration functions ************************************/\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);\r
+\r
+/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);\r
+\r
+/* Regular Channels Configuration functions ***********************************/\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
+\r
+/* Regular Channels DMA Configuration functions *******************************/\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+\r
+/* Injected channels Configuration functions **********************************/\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);\r
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);\r
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_ADC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
projects / fw / stlink / blobdiff