From c34cf61917860a821a4631edda334443633805e7 Mon Sep 17 00:00:00 2001 From: epetrich Date: Sun, 9 Nov 2003 01:51:10 +0000 Subject: [PATCH] * support/regression/fwk/lib/testfwk.c: printn is recursive and thus needs the reentrant attribute. * src/hc08/gen.c (genPackBits): added missing stack readjustment * sim/ucsim/hc08.src/inst.cc (inst_mov): fixed bugs with mov instruction simulation * src/SDCCast.c (decorateType): fixed bug with storage class not being updated during pointer dereference; f.e. ~(((char *)1)*) was being erroneously reduced to a literal. * src/hc08/ralloc.c (packRegisters, rematStr), * src/hc08/gen.c (aopForRemat): allow literals to be rematerialized in some cases git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@3009 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- ChangeLog | 14 +++++ sim/ucsim/hc08.src/inst.cc | 84 ++++++++++++++++++++++------ src/SDCCast.c | 34 +++++++++++ src/hc08/gen.c | 45 ++++++++++----- src/hc08/ralloc.c | 61 +++++++++++++++++++- support/regression/fwk/lib/testfwk.c | 8 ++- 6 files changed, 213 insertions(+), 33 deletions(-) diff --git a/ChangeLog b/ChangeLog index 90a05598..16011036 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,17 @@ +2003-11-08 Erik Petrich + + * support/regression/fwk/lib/testfwk.c: printn is recursive and thus needs + the reentrant attribute. + * src/hc08/gen.c (genPackBits): added missing stack readjustment + * sim/ucsim/hc08.src/inst.cc (inst_mov): fixed bugs with mov instruction + simulation + * src/SDCCast.c (decorateType): fixed bug with storage class not being + updated during pointer dereference; f.e. ~(((char *)1)*) was being + erroneously reduced to a literal. + * src/hc08/ralloc.c (packRegisters, rematStr), + * src/hc08/gen.c (aopForRemat): allow literals to be rematerialized in + some cases + 2003-11-08 Frieder Ferlemann * src/mcs51/main.c: fixed bug #838385. Thanks to Josef Pavlik for finding and fixing diff --git a/sim/ucsim/hc08.src/inst.cc b/sim/ucsim/hc08.src/inst.cc index 6c491a14..80e1439a 100644 --- a/sim/ucsim/hc08.src/inst.cc +++ b/sim/ucsim/hc08.src/inst.cc @@ -212,12 +212,23 @@ cl_hc08::inst_add(t_mem code, bool prefix) FLAG_NZ (result); FLAG_ASSIGN (BIT_V, 0x80 & ((regs.A & operand & ~result) | (~regs.A & ~operand & result))); - FLAG_ASSIGN (BIT_H, 0x10 & ((regs.A & operand) + FLAG_ASSIGN (BIT_H, 0x08 & ((regs.A & operand) | (operand & ~result) | (~result & regs.A))); FLAG_ASSIGN (BIT_C, 0x80 & ((regs.A & operand) | (operand & ~result) | (~result & regs.A))); + +#if 0 + fprintf (stdout, "add 0x%02x + 0x%02x = 0x%02x ",regs.A, operand, result & 0xff); + fprintf (stdout, "(V=%d, H=%d, C=%d, N=%d, Z=%d), ", + (regs.P & BIT_V)!=0, + (regs.P & BIT_H)!=0, + (regs.P & BIT_C)!=0, + (regs.P & BIT_N)!=0, + (regs.P & BIT_Z)!=0); +#endif + regs.A = result; return(resGO); } @@ -227,19 +238,37 @@ cl_hc08::inst_adc(t_mem code, bool prefix) { int result; uchar operand; + int sresult; + uchar carryin = (regs.P & BIT_C)!=0; operand = OPERAND(code, prefix); - result = (regs.A + operand + ((regs.P & BIT_C)!=0)) & 0xff; - FLAG_NZ (result); - FLAG_ASSIGN (BIT_V, 0x80 & ((regs.A & operand & ~result) - | (~regs.A & ~operand & result))); - FLAG_ASSIGN (BIT_H, 0x10 & ((regs.A & operand) + result = regs.A + operand + carryin; + sresult = (signed char)regs.A + (signed char)operand + ((regs.P & BIT_C)!=0); + FLAG_NZ (result & 0xff); + FLAG_ASSIGN (BIT_V, (sresult<-128) || (sresult>127)); + /* 0x80 & ((regs.A & operand & ~result) + | (~regs.A & ~operand & result))); */ + FLAG_ASSIGN (BIT_H, (result & 0xf) < (regs.A & 0xf)); + /* 0x10 & ((regs.A & operand) | (operand & ~result) - | (~result & regs.A))); - FLAG_ASSIGN (BIT_C, 0x80 & ((regs.A & operand) + | (~result & regs.A))); */ + FLAG_ASSIGN (BIT_C, result & 0x100); + /* 0x80 & ((regs.A & operand) | (operand & ~result) - | (~result & regs.A))); - regs.A = result; + | (~result & regs.A))); */ + +#if 0 + fprintf (stdout, "adc 0x%02x + 0x%02x + %d = 0x%02x ", + regs.A, operand, carryin, result & 0xff); + fprintf (stdout, "(V=%d, H=%d, C=%d, N=%d, Z=%d), ", + (regs.P & BIT_V)!=0, + (regs.P & BIT_H)!=0, + (regs.P & BIT_C)!=0, + (regs.P & BIT_N)!=0, + (regs.P & BIT_Z)!=0); +#endif + + regs.A = result & 0xff; return(resGO); } @@ -257,6 +286,15 @@ cl_hc08::inst_sub(t_mem code, bool prefix) FLAG_ASSIGN (BIT_C, 0x80 & ((~regs.A & operand) | (operand & result) | (result & ~regs.A))); +#if 0 + fprintf (stdout, "sub 0x%02x - 0x%02x = 0x%02x ",regs.A, operand, result & 0xff); + fprintf (stdout, "(V=%d, H=%d, C=%d, N=%d, Z=%d), ", + (regs.P & BIT_V)!=0, + (regs.P & BIT_H)!=0, + (regs.P & BIT_C)!=0, + (regs.P & BIT_N)!=0, + (regs.P & BIT_Z)!=0); +#endif regs.A = result; return(resGO); } @@ -266,15 +304,26 @@ cl_hc08::inst_sbc(t_mem code, bool prefix) { int result; uchar operand; + uchar carryin = (regs.P & BIT_C)!=0; operand = OPERAND(code, prefix); - result = (regs.A - operand - ((regs.P & BIT_C)!=0) ) & 0xff; + result = (regs.A - operand - carryin) & 0xff; FLAG_NZ (result); FLAG_ASSIGN (BIT_V, 0x80 & ((regs.A & ~operand & ~result) | (~regs.A & operand & result))); FLAG_ASSIGN (BIT_C, 0x80 & ((~regs.A & operand) | (operand & result) | (result & ~regs.A))); +#if 0 + fprintf (stdout, "sbc 0x%02x - 0x%02x - %d = 0x%02x ", + regs.A, operand, carryin, result & 0xff); + fprintf (stdout, "(V=%d, H=%d, C=%d, N=%d, Z=%d), ", + (regs.P & BIT_V)!=0, + (regs.P & BIT_H)!=0, + (regs.P & BIT_C)!=0, + (regs.P & BIT_N)!=0, + (regs.P & BIT_Z)!=0); +#endif regs.A = result; return(resGO); } @@ -1028,25 +1077,26 @@ cl_hc08::inst_mov(t_mem code, bool prefix) int ea; uchar operand; bool aix; + int hx = (regs.H << 8) | (regs.X); switch (code) { - case 0x4e: + case 0x4e: //mov opr8a,opr8a operand = get1(fetch()); ea = fetch(); aix = 0; break; - case 0x5e: + case 0x5e: //mov opr8a,x+ operand = get1(fetch()); - ea = regs.X; + ea = hx; aix = 1; break; - case 0x6e: + case 0x6e: //mov #opr8i,opr8a operand = fetch(); ea = fetch(); aix = 0; break; - case 0x7e: - operand = get1(regs.X); + case 0x7e: //mov x+,opr8a + operand = get1(hx); ea = fetch(); aix = 1; break; diff --git a/src/SDCCast.c b/src/SDCCast.c index d0ba0c9b..354a70b2 100644 --- a/src/SDCCast.c +++ b/src/SDCCast.c @@ -2168,6 +2168,7 @@ decorateType (ast * tree) /* adjust the storage class */ switch (DCL_TYPE(tree->left->ftype)) { case POINTER: + SPEC_SCLS(TETYPE(tree)) = S_DATA; break; case FPOINTER: SPEC_SCLS(TETYPE(tree)) = S_XDATA; @@ -2176,6 +2177,7 @@ decorateType (ast * tree) SPEC_SCLS(TETYPE(tree)) = S_CODE; break; case GPOINTER: + SPEC_SCLS (TETYPE (tree)) = 0; break; case PPOINTER: SPEC_SCLS(TETYPE(tree)) = S_XSTACK; @@ -2187,6 +2189,8 @@ decorateType (ast * tree) SPEC_SCLS(TETYPE(tree)) = S_EEPROM; break; case UPOINTER: + SPEC_SCLS (TETYPE (tree)) = 0; + break; case ARRAY: case FUNCTION: break; @@ -2621,6 +2625,36 @@ decorateType (ast * tree) } TTYPE (tree) = copyLinkChain (LTYPE (tree)->next); TETYPE (tree) = getSpec (TTYPE (tree)); + /* adjust the storage class */ + switch (DCL_TYPE(tree->left->ftype)) { + case POINTER: + SPEC_SCLS(TETYPE(tree)) = S_DATA; + break; + case FPOINTER: + SPEC_SCLS(TETYPE(tree)) = S_XDATA; + break; + case CPOINTER: + SPEC_SCLS(TETYPE(tree)) = S_CODE; + break; + case GPOINTER: + SPEC_SCLS (TETYPE (tree)) = 0; + break; + case PPOINTER: + SPEC_SCLS(TETYPE(tree)) = S_XSTACK; + break; + case IPOINTER: + SPEC_SCLS(TETYPE(tree)) = S_IDATA; + break; + case EEPPOINTER: + SPEC_SCLS(TETYPE(tree)) = S_EEPROM; + break; + case UPOINTER: + SPEC_SCLS (TETYPE (tree)) = 0; + break; + case ARRAY: + case FUNCTION: + break; + } return tree; } diff --git a/src/hc08/gen.c b/src/hc08/gen.c index 9f60de19..fde9e310 100644 --- a/src/hc08/gen.c +++ b/src/hc08/gen.c @@ -1352,7 +1352,7 @@ static asmop * aopForRemat (symbol * sym) { iCode *ic = sym->rematiCode; - asmop *aop = newAsmop (AOP_IMMD); + asmop *aop = NULL; int ptr_type=0; int val = 0; @@ -1377,22 +1377,40 @@ aopForRemat (symbol * sym) ic = OP_SYMBOL (IC_LEFT (ic))->rematiCode; } - if (val) - sprintf (buffer, "(%s %c 0x%04x)", - OP_SYMBOL (IC_LEFT (ic))->rname, - val >= 0 ? '+' : '-', - abs (val) & 0xffff); - else - strcpy (buffer, OP_SYMBOL (IC_LEFT (ic))->rname); + if (ic->op == ADDRESS_OF) + { + if (val) + sprintf (buffer, "(%s %c 0x%04x)", + OP_SYMBOL (IC_LEFT (ic))->rname, + val >= 0 ? '+' : '-', + abs (val) & 0xffff); + else + strcpy (buffer, OP_SYMBOL (IC_LEFT (ic))->rname); - aop->aopu.aop_immd.aop_immd1 = Safe_calloc (1, strlen (buffer) + 1); - strcpy (aop->aopu.aop_immd.aop_immd1, buffer); - /* set immd2 field if required */ - if (aop->aopu.aop_immd.from_cast_remat) { + aop = newAsmop (AOP_IMMD); + aop->aopu.aop_immd.aop_immd1 = Safe_calloc (1, strlen (buffer) + 1); + strcpy (aop->aopu.aop_immd.aop_immd1, buffer); + /* set immd2 field if required */ + if (aop->aopu.aop_immd.from_cast_remat) + { sprintf(buffer,"#0x%02x",ptr_type); aop->aopu.aop_immd.aop_immd2 = Safe_calloc (1, strlen (buffer) + 1); strcpy (aop->aopu.aop_immd.aop_immd2, buffer); - } + } + } + else if (ic->op == '=') + { + val += (int) operandLitValue (IC_RIGHT (ic)); + val &= 0xffff; + sprintf (buffer, "0x%04x", val); + aop = newAsmop (AOP_LIT); + aop->aopu.aop_lit = constVal (buffer); + } + else + werror (E_INTERNAL_ERROR, __FILE__, __LINE__, + "unexpected rematerialization"); + + return aop; } @@ -6633,6 +6651,7 @@ genPackBits (sym_link * etype, emitcode ("and", "#0x%02x", mask); emitcode ("ora", "1,s"); emitcode ("sta", ",x"); + pullReg (hc08_reg_a); } hc08_freeReg (hc08_reg_a); diff --git a/src/hc08/ralloc.c b/src/hc08/ralloc.c index 4a911dc1..606fed3e 100644 --- a/src/hc08/ralloc.c +++ b/src/hc08/ralloc.c @@ -1606,6 +1606,7 @@ rematStr (symbol * sym) ic = OP_SYMBOL (IC_LEFT (ic))->rematiCode; continue; } + /* if (ic->op == '+') { @@ -1626,7 +1627,10 @@ rematStr (symbol * sym) continue; } /* we reached the end */ - sprintf (s, "%s", OP_SYMBOL (IC_LEFT (ic))->rname); + if (ic->op == ADDRESS_OF) + sprintf (s, "%s", OP_SYMBOL (IC_LEFT (ic))->rname); + else if (ic->op == '='); + sprintf (s, "0x%04x", (int) operandLitValue (IC_RIGHT (ic)) ); break; } @@ -1838,6 +1842,43 @@ farSpacePackable (iCode * ic) } #endif +#if 0 +static void +packRegsForLiteral (iCode * ic) +{ + int k; + iCode *uic; + + if (ic->op != '=') + return; + if (POINTER_SET (ic)) + return; + if (!IS_LITERAL (getSpec (operandType (IC_RIGHT (ic))))) + return; + if (bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) > 1) + return; + + for (k=0; k< OP_USES (IC_RESULT (ic))->size; k++) + if (bitVectBitValue (OP_USES (IC_RESULT (ic)), k)) + { + uic = hTabItemWithKey (iCodehTab, k); + if (!uic) continue; + + if (uic->op != IFX && uic->op != JUMPTABLE) + { + if (IC_LEFT (uic) && IC_LEFT (uic)->key == IC_RESULT (ic)->key) + ReplaceOpWithCheaperOp(&IC_LEFT(uic), IC_RIGHT(ic)); + if (IC_RIGHT (uic) && IC_RIGHT (uic)->key == IC_RESULT (ic)->key) + ReplaceOpWithCheaperOp(&IC_RIGHT(uic), IC_RIGHT(ic)); + if (IC_RESULT (uic) && IC_RESULT (uic)->key == IC_RESULT (ic)->key) + ReplaceOpWithCheaperOp(&IC_RESULT(uic), IC_RIGHT(ic)); + } + } + +} +#endif + + /*-----------------------------------------------------------------*/ /* packRegsForAssign - register reduction for assignment */ /*-----------------------------------------------------------------*/ @@ -2675,10 +2716,12 @@ packRegisters (eBBlock ** ebpp, int blockno) for (ic = ebp->sch; ic; ic = ic->next) { + //packRegsForLiteral (ic); + /* if this is an itemp & result of an address of a true sym then mark this as rematerialisable */ if (ic->op == ADDRESS_OF && - IS_ITEMP (IC_RESULT (ic)) && + IS_ITEMP (IC_RESULT (ic)) && IS_TRUE_SYMOP (IC_LEFT (ic)) && bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1 && !OP_SYMBOL (IC_LEFT (ic))->onStack ) @@ -2689,7 +2732,20 @@ packRegisters (eBBlock ** ebpp, int blockno) OP_SYMBOL (IC_RESULT (ic))->usl.spillLoc = NULL; } +#if 1 + if (ic->op == '=' && + !POINTER_SET (ic) && + IS_ITEMP (IC_RESULT (ic)) && + IS_VALOP (IC_RIGHT (ic)) && + bitVectnBitsOn (OP_DEFS (IC_RESULT (ic))) == 1) + { + + OP_SYMBOL (IC_RESULT (ic))->remat = 1; + OP_SYMBOL (IC_RESULT (ic))->rematiCode = ic; + OP_SYMBOL (IC_RESULT (ic))->usl.spillLoc = NULL; + } +#endif /* if straight assignment then carry remat flag if this is the only definition */ if (ic->op == '=' && @@ -2903,6 +2959,7 @@ packRegisters (eBBlock ** ebpp, int blockno) || ic->op == GETHBIT || ic->op == LEFT_OP || ic->op == RIGHT_OP || ic->op == CALL || (ic->op == ADDRESS_OF && isOperandOnStack (IC_LEFT (ic))) + || ic->op == RECEIVE ) && IS_ITEMP (IC_RESULT (ic)) && getSize (operandType (IC_RESULT (ic))) <= 1) diff --git a/support/regression/fwk/lib/testfwk.c b/support/regression/fwk/lib/testfwk.c index 766954a6..48d92317 100644 --- a/support/regression/fwk/lib/testfwk.c +++ b/support/regression/fwk/lib/testfwk.c @@ -7,6 +7,12 @@ #include /* main() must see the ISR declarations */ #endif +#if defined(PORT_HOST) || defined(SDCC_z80) || defined(SDCC_gbz80) +#define _REENTRANT +#else +#define _REENTRANT reentrant +#endif + /** Define this if the port's div or mod functions are broken. A slow loop based method will be substituded. */ @@ -45,7 +51,7 @@ int __mod(int num, int denom) } #endif -static void _printn(int n) +static void _printn(int n) _REENTRANT { int rem; -- 2.30.2