From: borutr Date: Sun, 29 Apr 2007 13:15:51 +0000 (+0000) Subject: * Fixed svn:eol-style and svn:keywords properties X-Git-Url: https://git.gag.com/?p=fw%2Fsdcc;a=commitdiff_plain;h=5c167d844868e592617c9a8f1355abb9e29647a9 * Fixed svn:eol-style and svn:keywords properties git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@4776 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- diff --git a/ChangeLog b/ChangeLog index 6dc95f5b..e86ce285 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,7 @@ +2007-04-29 Borut Razem + + * Fixed svn:eol-style and svn:keywords properties + 2007-04-29 Maarten Brock * src/mcs51/gen.c (genRet): fixed bug 1707003 diff --git a/device/include/asm/pic/features.h b/device/include/asm/pic/features.h index 7bee4ec7..a7ffa802 100644 --- a/device/include/asm/pic/features.h +++ b/device/include/asm/pic/features.h @@ -10,7 +10,7 @@ * The GNU PIC Library is maintained by, * Vangelis Rokas * - * $Id: features.h 3714 2005-04-02 13:13:53Z vrokas $ + * $Id$ * */ #ifndef __PIC14_ASM_FEATURES_H diff --git a/device/include/mcs51/ADuC84x.h b/device/include/mcs51/ADuC84x.h index 2eb0d006..2ce4131f 100644 --- a/device/include/mcs51/ADuC84x.h +++ b/device/include/mcs51/ADuC84x.h @@ -1,379 +1,379 @@ -/*------------------------------------------------------------------------- - Register Declarations for Analog Devices ADuC841/ADuC842/ADuC843 - (Based on datasheet Rev 0, 11/2003 ) - - Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (March 2007) - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option); any later version - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - In other words, you are welcome to use, share and improve this program - You are forbidden to forbid anyone else to use, share and improve - what you give them. Help stamp out software-hoarding! --------------------------------------------------------------------------*/ -#ifndef REG_ADUC84X_H -#define REG_ADUC84X_H - -#include - -SFR(CFG841, 0xAF); // ADuC841 Configuration SFR. -SFR(CFG842, 0xAF); // ADuC842/ADuC843 Configuration SFR. - //For the two SFRs above these are the bits. Warning: some are different for - //the ADuC841 and ADuC842/ADuC843. Check the datasheet! - #define EPM2 0x10 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 2. - #define EPM1 0x08 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 1. - #define EPM0 0x04 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 0. - #define EXSP 0x80 // Extended SP Enable. - #define PWPO 0x40 // PWM Pin Out Selection. - #define DBUF 0x20 // DAC Output Buffer. - #define EXTCLK 0x10 // Set by the user to 1 to select an external clock input on P3.4. - #define MSPI 0x02 // Set to 1 by the user to move the SPI functionality of. - #define XRAMEN 0x01 // XRAM Enable Bit. - -SFR(SP, 0x81); // Stack Pointer. -SFR(SPH, 0xB7); // Stack pointer high. - -SFR(DPL, 0x82); // Data Pointer Low. -SFR(DPH, 0x83); // Data Pointer High. -SFR(DPP, 0x84); // Data Pointer Page Byte. -SFR(DPCON, 0xA7); // Data Pointer Control SFR. - -SFR(PCON, 0x87); // Power Control. - #define SMOD 0x80 //Double UART Baud Rate. - #define SERIPD 0x40 //I2C/SPI Power-Down Interrupt Enable. - #define INT0PD 0x20 //INT0 Power-Down Interrupt Enable. - #define ALEOFF 0x10 //Disable ALE Output. - #define GF1 0x08 //General-Purpose Flag Bit. - #define GF0 0x04 //General-Purpose Flag Bit. - #define PD 0x02 //Power-Down Mode Enable. - #define IDL 0x01 //Idle Mode Enable. - -SFR(TCON, 0x88); // Timer/Counter Control. - SBIT(TF1, 0x88, 7); // Timer 1 overflow flag. - SBIT(TR1, 0x88, 6); // Timer 1 run control flag. - SBIT(TF0, 0x88, 5); // Timer 0 overflow flag. - SBIT(TR0, 0x88, 4); // Timer 0 run control flag. - SBIT(IE1, 0x88, 3); // Interrupt 1 flag. - SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit. - SBIT(IE0, 0x88, 1); // Interrupt 0 flag. - SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit. - -SFR(TMOD, 0x89); // Timer/Counter Mode Control. - #define GATE1 0x80 // External enable for timer 1. - #define C_T1 0x40 // Timer or counter select for timer 1. - #define M1_1 0x20 // Operation mode bit 1 for timer 1. - #define M0_1 0x10 // Operation mode bit 0 for timer 1. - #define GATE0 0x08 // External enable for timer 0. - #define C_T0 0x04 // Timer or counter select for timer 0. - #define M1_0 0x02 // Operation mode bit 1 for timer 0. - #define M0_0 0x01 // Operation mode bit 0 for timer 0. - -SFR(TL0, 0x8A); // Timer 0 LSB. -SFR(TL1, 0x8B); // Timer 1 LSB. -SFR(TH0, 0x8C); // Timer 0 MSB. -SFR(TH1, 0x8D); // Timer 1 MSB. - -SFR(P0, 0x80); // Port 0 - SBIT(P0_0, 0x80, 0); // Port 0 bit 0. - SBIT(P0_1, 0x80, 1); // Port 0 bit 1. - SBIT(P0_2, 0x80, 2); // Port 0 bit 2. - SBIT(P0_3, 0x80, 3); // Port 0 bit 3. - SBIT(P0_4, 0x80, 4); // Port 0 bit 4. - SBIT(P0_5, 0x80, 5); // Port 0 bit 5. - SBIT(P0_6, 0x80, 6); // Port 0 bit 6. - SBIT(P0_7, 0x80, 7); // Port 0 bit 7. - -SFR(P1, 0x90); // Port 1 - SBIT(P1_0, 0x90, 0); // Port 1 bit 0. - SBIT(P1_1, 0x90, 1); // Port 1 bit 1. - SBIT(P1_2, 0x90, 2); // Port 1 bit 2. - SBIT(P1_3, 0x90, 3); // Port 1 bit 3. - SBIT(P1_4, 0x90, 4); // Port 1 bit 4. - SBIT(P1_5, 0x90, 5); // Port 1 bit 5. - SBIT(P1_6, 0x90, 6); // Port 1 bit 6. - SBIT(P1_7, 0x90, 7); // Port 1 bit 7. - // Alternate names - SBIT(T2EX, 0x90, 1); //Capture/reload trigger for Counter 2. - SBIT(T2, 0x90, 0); //Input to Timer/Counter 2. - -SFR(P2, 0xA0); // Port 2 - SBIT(P2_0, 0xA0, 0); // Port 2 bit 0. - SBIT(P2_1, 0xA0, 1); // Port 2 bit 1. - SBIT(P2_2, 0xA0, 2); // Port 2 bit 2. - SBIT(P2_3, 0xA0, 3); // Port 2 bit 3. - SBIT(P2_4, 0xA0, 4); // Port 2 bit 4. - SBIT(P2_5, 0xA0, 5); // Port 2 bit 5. - SBIT(P2_6, 0xA0, 6); // Port 2 bit 6. - SBIT(P2_7, 0xA0, 7); // Port 2 bit 7. - -SFR(P3, 0xB0); // Port 3 - SBIT(P3_0, 0xB0, 0); // Port 3 bit 0. - SBIT(P3_1, 0xB0, 1); // Port 3 bit 1. - SBIT(P3_2, 0xB0, 2); // Port 3 bit 2. - SBIT(P3_3, 0xB0, 3); // Port 3 bit 3. - SBIT(P3_4, 0xB0, 4); // Port 3 bit 4. - SBIT(P3_5, 0xB0, 5); // Port 3 bit 5. - SBIT(P3_6, 0xB0, 6); // Port 3 bit 6. - SBIT(P3_7, 0xB0, 7); // Port 3 bit 7. - // Alternate names. - SBIT(RXD, 0xB0, 0); - SBIT(TXD, 0xB0, 1); - SBIT(INT0, 0xB0, 2); - SBIT(INT1, 0xB0, 3); - SBIT(T0, 0xB0, 4); - SBIT(T1, 0xB0, 5); - SBIT(WR, 0xB0, 6); - SBIT(RD, 0xB0, 7); - -SFR(I2CADD, 0x9B); // I2C Address Register 1. -SFR(I2CADD1, 0x91); // I2C Address Register 2. -SFR(I2CADD2, 0x92); // I2C Address Register 3. -SFR(I2CADD3, 0x93); // I2C Address Register 4. -SFR(I2CDAT, 0x9A); // I2C Data Register. - -SFR(SCON, 0x98); // Serial Port Control. - SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0. - SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1. - SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2. - SBIT(REN, 0x98, 4); // Enables serial reception. - SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3. - SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received. - SBIT(TI, 0x98, 1); // Transmit interrupt flag. - SBIT(RI, 0x98, 0); // Receive interrupt flag. - -SFR(SBUF, 0x99); // Serial Data Buffer. - -//For these two, you may want to check page 68 of the datasheet... -SFR(T3FD, 0x9D); // Fractional divider ratio. -SFR(T3CON, 0x9E); // T3CON is the baud rate control SFR, allowing Timer 3 to be - // used to set up the UART baud rate, and setting up the binary - // divider (DIV). -#define T3BAUDEN 0x80 // T3 UART BAUD Enable. -#define DIV2 0x04 // Binary Divider Factor bit 3. -#define DIV1 0x02 // Binary Divider Factor bit 2. -#define DIV0 0x01 // Binary Divider Factor bit 1. - -SFR(TIMECON, 0xA1); // TIC Control Register. - #define TFH 0x40 // Twenty-Four Hour Select Bit. - #define ITS1 0x20 // Interval Timebase Selection Bit 1. - #define ITS0 0x10 // Interval Timebase Selection Bit 1. - #define STI 0x08 // Single Time Interval Bit. - #define TII 0x04 // TIC Interrupt Bit. - #define TIEN 0x02 // Time Interval Enable Bit. - #define TCEN 0x01 // Time Clock Enable Bit. - -SFR(HTHSEC, 0xA2); // Hundredths Seconds Time Register. -SFR(SEC, 0xA3); // Seconds Time Register. -SFR(MIN, 0xA4); // Minutes Time Register. -SFR(HOUR, 0xA5); // Hours Time Register. -SFR(INTVAL, 0xA6); // User Time Interval Select Register. - -SFR(IE, 0xA8); // Interrupt Enable. - SBIT(EA, 0xA8, 7); // Global Interrupt Enable. - SBIT(EADC, 0xA8, 6); // ADC Interrupt Enable. - SBIT(ET2, 0xA8, 5); // Timer 2 Interrupt Enable. - SBIT(ES, 0xA8, 4); // Serial Interrupt Enable. - SBIT(ET1, 0xA8, 3); // Timer 1 Interrupt Enable. - SBIT(EX1, 0xA8, 2); // External 1 Interrupt Enable. - SBIT(ET0, 0xA8, 1); // Timer 0 Interrupt Enable. - SBIT(EX0, 0xA8, 0); // External 0 Interrupt Enable. - -SFR(IEIP2, 0xA9); // Secondary Interrupt Enable Register - #define PTI 0x40 // Priority for time interval interrupt. - #define PPSM 0x20 // Priority for power supply monitor interrupt. - #define PSI2 0x10 // Priority for SPI/I2C interrupt. Same name as bit in IP??? - #define ETI 0x04 // Enable time interval counter interrupts. - #define EPSMI 0x02 // Enable power supply monitor interrupts. - #define ESI 0x01 // Enable SPI or I2C serial port interrupts. - -SFR(PWMCON, 0xAE); //PWM control. - #define SNGL 0x80 // Turns off PMW output at P2.6 or P3.4. - #define MD2 0x40 // PWM Mode Bit 2. - #define MD1 0x20 // PWM Mode Bit 2. - #define MD0 0x10 // PWM Mode Bit 2. - #define CDIV1 0x08 // PWM Clock Divider bit 1. - #define CDIV0 0x04 // PWM Clock Divider bit 1. - #define CSEL1 0x02 // PWM Clock Select bit 1. (Typo in datasheet???) - #define CSEL0 0x01 // PWM Clock Select bit 0. - -SFR(PWM0L, 0xB1); // PWM 0 duty cycle low. -SFR(PWM0H, 0xB2); // PWM 0 duty cycle high. -SFR(PWM1L, 0xB3); // PWM 1 duty cycle low. -SFR(PWM1H, 0xB4); // PWM 1 duty cycle high. - -SFR(IP, 0xB8); // Interrupt Priority Reg. - SBIT(PSI, 0xB8, 7); // Priority for SPI/I2C interrupt. - SBIT(PADC, 0xB8, 6); // ADC interrupt priority bit. - SBIT(PT2, 0xB8, 5); // Timer 2 interrupt priority bit. - SBIT(PS, 0xB8, 4); // Serial Port interrupt priority bit. - SBIT(PT1, 0xB8, 3); // Timer 1 interrupt priority bit. - SBIT(PX1, 0xB8, 2); // External interrupt 1 priority bit. - SBIT(PT0, 0xB8, 1); // Timer 0 interrupt priority bit. - SBIT(PX0, 0xB8, 0); // External interrupt 0 priority bit. - -SFR(ECON, 0xB9); // Flash/EE Memory Control SFR. -SFR(EDATA1, 0xBC); // EE page data byte 1. -SFR(EDATA2, 0xBD); // EE page data byte 2. -SFR(EDATA3, 0xBE); // EE page data byte 3. -SFR(EDATA4, 0xBF); // EE page data byte 4. -SFR(EADRL, 0xC6); // EE address low. -SFR(EADRH, 0xC7); // EE address high. - -SFR(WDCON, 0xC0); //Watchdog Timer Control Register. - SBIT(PRE3, 0xc0, 7); // Timeout period bit 4. - SBIT(PRE2, 0xc0, 6); // Timeout period bit 3. - SBIT(PRE1, 0xc0, 5); // Timeout period bit 2. - SBIT(PRE0, 0xc0, 4); // Timeout period bit 1. - SBIT(WDIR, 0xc0, 3); // Watchdog Interrupt Response Enable Bit. - SBIT(WDS, 0xc0, 2); // Watchdog Status Bit. - SBIT(WDE, 0xc0, 1); // Watchdog Enable Bit. - SBIT(WDWR, 0xc0, 0); // Watchdog Write Enable Bit. - -SFR(CHIPID, 0xC2); // System Self-Identification? WARNING: No description in the datasheet. - -SFR(T2CON, 0xC8); // Timer / Counter 2 Control. - SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag. - SBIT(EXF2, 0xC8, 6); // Timer 2 external flag. - SBIT(RCLK, 0xC8, 5); // Receive clock flag. - SBIT(TCLK, 0xC8, 4); // Transmit clock flag. - SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag. - SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2. - SBIT(CNT2, 0xC8, 1); // Timer or coutner select. - SBIT(CAP2, 0xC8, 0); // Capture/reload flag. - -SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB. -SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB. -SFR(TL2, 0xCC); // Timer 2 LSB. -SFR(TH2, 0xCD); // Timer 2 MSB. - -SFR(PSW, 0xD0); // Program Status Word. - SBIT(CY, 0xD0, 7); // Carry Flag. - SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag. - SBIT(F0, 0xD0, 5); // User-Defined Flag. - SBIT(RS1, 0xD0, 4); // Register Bank Select 1. - SBIT(RS0, 0xD0, 3); // Register Bank Select 0. - SBIT(OV, 0xD0, 2); // Overflow Flag. - SBIT(F1, 0xD0, 1); // User-Defined Flag. - SBIT(P, 0xD0, 0); // Parity Flag. - -SFR(DMAL, 0xD2); // DMA mode address pointer low. -SFR(DMAH, 0xD3); // DMA mode address pointer high. -SFR(DMAP, 0xD4); // DMA mode address pointer page. (?) -SFR(PLLCON, 0xD7); // PLL Control Register. - -SFR(PSMCON, 0xDF); // Power supply monitor. - #define CMPD 0x40 // DVDD Comparator Bit. - #define PSMI 0x20 // Power Supply Monitor Interrupt Bit. - #define TPD1 0x10 // DVDD Trip Point Selection Bit 2. - #define TPD0 0x08 // DVDD Trip Point Selection Bit 1. - #define PSMEN 0x01 // Power Supply Monitor Enable Bit. - -SFR(ACC, 0xE0); // Accumulator - SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0. - SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1. - SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2. - SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3. - SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4. - SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5. - SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6. - SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7. - -SFR(I2CCON, 0xE8); // I2C Control Register - // Master mode - SBIT(MDO, 0xE8, 7); // I2C Software Master Data Output Bit. - SBIT(MDE, 0xE8, 6); // I2C Software Master Data Output Enable Bit. - SBIT(MCO, 0xE8, 5); // I2C Software Master Clock Output Bit. - SBIT(MDI, 0xE8, 4); // I2C Software Master Data Input Bit. - // Slave mode - SBIT(I2CSI, 0xE8, 7); // I2C Stop Interrupt Enable Bit. - SBIT(I2CGC, 0xE8, 6); // I2C General Call Status Bit. - SBIT(I2CID1, 0xE8, 5); // I2C Interrupt Decode Bit 2. - SBIT(I2CID0, 0xE8, 4); // I2C Interrupt Decode Bit 1. - SBIT(I2CM, 0xE8, 3); // I2C Master/Slave Mode Bit. - SBIT(I2CRS, 0xE8, 2); // I2C Reset Bit. - SBIT(I2CTX, 0xE8, 1); // I2C Direction Transfer Bit. - SBIT(I2CI, 0xE8, 0); // I2C Interrupt Bit. - -SFR(B, 0xF0); // B Register - SBIT(B_0, 0xF0, 0); // Register B bit 0. - SBIT(B_1, 0xF0, 1); // Register B bit 1. - SBIT(B_2, 0xF0, 2); // Register B bit 2. - SBIT(B_3, 0xF0, 3); // Register B bit 3. - SBIT(B_4, 0xF0, 4); // Register B bit 4. - SBIT(B_5, 0xF0, 5); // Register B bit 5. - SBIT(B_6, 0xF0, 6); // Register B bit 6. - SBIT(B_7, 0xF0, 7); // Register B bit 7. - -SFR(ADCCON1, 0xEF); //ADC Control SFR 1 - //WARNING: bit 7 is named MD1 in the datasheet, but that name is already used. - #define MD 0x80 // The mode bit selects the active operating mode of the ADC. - #define EXT_REF 0x40 // Set by the user to select an external reference. - #define CK1 0x20 // The ADC clock divide bit 1. - #define CK0 0x10 // The ADC clock divide bit 0. - #define AQ1 0x08 // ADC acquisition select bit 1. - #define AQ0 0x04 // ADC acquisition select bit 0. - #define T2C 0x02 // The Timer 2 conversion bit. - #define EXC 0x01 // The external trigger enable bit. - -SFR(ADCCON2, 0xD8); // ADC Control SFR 2. - SBIT(ADCI, 0xD8, 7); // ADC Interrupt Bit. - SBIT(DMA, 0xD8, 6); // DMA Mode Enable Bit. - SBIT(CCONV, 0xD8, 5); // Continuous Conversion Bit. - SBIT(SCONV, 0xD8, 4); // Single Conversion Bit. - SBIT(CS3, 0xD8, 3); // Channel Selection Bit 4. - SBIT(CS2, 0xD8, 2); // Channel Selection Bit 3. - SBIT(CS1, 0xD8, 1); // Channel Selection Bit 2. - SBIT(CS0, 0xD8, 0); // Channel Selection Bit 1. - -SFR(ADCCON3, 0xF5); //ADC Control SFR 3 - #define BUSY 0x80 // ADC Busy Status Bit. - #define AVGS1 0x20 // Number of Average Selection Bit 2. - #define AVGS0 0x10 // Number of Average Selection Bit 1. - #define TYPICAL 0x02 // Calibration Type Select Bit. - #define SCAL 0x01 // Start Calibration Cycle Bit. - -SFR(ADCDATAL, 0xD9); // ADC Result byte low. -SFR(ADCDATAH, 0xDA); // ADC Result byte high. WARNING: bits 4 to 7 are the ADC channel! -SFR(ADCOFSL, 0xF1); // Offset calibration coefficient byte (low). -SFR(ADCOFSH, 0xF2); // Offset calibration coefficient byte (high). -SFR(ADCGAINL, 0xF3); // Gain calibration coefficient byte (low). -SFR(ADCGAINH, 0xF4); // Gain calibration coefficient byte (high). - -SFR(SPIDAT, 0xF7); // SPI Data Register. - -SFR(SPICON, 0xF8); // SPI Control Register. - SBIT(ISPI, 0xF8, 7); // SPI Interrupt Bit. - SBIT(WCOL, 0xF8, 6); // Write Collision Error Bit. - SBIT(SPE, 0xF8, 5); // SPI Interface Enable Bit. - SBIT(SPIM, 0xF8, 4); // SPI Master/Slave Mode Select Bit. - SBIT(CPOL, 0xF8, 3); // Clock Polarity Select Bit. - SBIT(CPHA, 0xF8, 2); // Clock Phase Select Bit. - SBIT(SPR1, 0xF8, 1); // SPI Bit Rate Select Bit 2. - SBIT(SPR0, 0xF8, 0); // SPI Bit Rate Select Bit 1. - -SFR(DAC0L, 0xF9); // DAC0 Data Low Byte. -SFR(DAC0H, 0xFA); // DAC0 Data High Byte. -SFR(DAC1L, 0xFB); // DAC1 Data Low Byte. -SFR(DAC1H, 0xFC); // DAC1 Data High Byte. -SFR(DACCON, 0xFD); // DAC Control Register. - #define MODE 0x80 // 8/12 bit selection. - #define RNG1 0x40 // DAC1 Range Select Bit. - #define RNG0 0x20 // DAC0 Range Select Bit. - #define CLR1 0x10 // DAC1 Clear Bit. - #define CLR0 0x08 // DAC0 Clear Bit. - #define SYNC 0x04 // DAC0/1 Update Synchronization Bit. - #define PD1 0x02 // DAC1 Power-Down Bit. - #define PD0 0x01 // DAC0 Power-Down Bit. - -#endif //REG_ADUC84X_H +/*------------------------------------------------------------------------- + Register Declarations for Analog Devices ADuC841/ADuC842/ADuC843 + (Based on datasheet Rev 0, 11/2003 ) + + Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (March 2007) + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option); any later version + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + In other words, you are welcome to use, share and improve this program + You are forbidden to forbid anyone else to use, share and improve + what you give them. Help stamp out software-hoarding! +-------------------------------------------------------------------------*/ +#ifndef REG_ADUC84X_H +#define REG_ADUC84X_H + +#include + +SFR(CFG841, 0xAF); // ADuC841 Configuration SFR. +SFR(CFG842, 0xAF); // ADuC842/ADuC843 Configuration SFR. + //For the two SFRs above these are the bits. Warning: some are different for + //the ADuC841 and ADuC842/ADuC843. Check the datasheet! + #define EPM2 0x10 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 2. + #define EPM1 0x08 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 1. + #define EPM0 0x04 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 0. + #define EXSP 0x80 // Extended SP Enable. + #define PWPO 0x40 // PWM Pin Out Selection. + #define DBUF 0x20 // DAC Output Buffer. + #define EXTCLK 0x10 // Set by the user to 1 to select an external clock input on P3.4. + #define MSPI 0x02 // Set to 1 by the user to move the SPI functionality of. + #define XRAMEN 0x01 // XRAM Enable Bit. + +SFR(SP, 0x81); // Stack Pointer. +SFR(SPH, 0xB7); // Stack pointer high. + +SFR(DPL, 0x82); // Data Pointer Low. +SFR(DPH, 0x83); // Data Pointer High. +SFR(DPP, 0x84); // Data Pointer Page Byte. +SFR(DPCON, 0xA7); // Data Pointer Control SFR. + +SFR(PCON, 0x87); // Power Control. + #define SMOD 0x80 //Double UART Baud Rate. + #define SERIPD 0x40 //I2C/SPI Power-Down Interrupt Enable. + #define INT0PD 0x20 //INT0 Power-Down Interrupt Enable. + #define ALEOFF 0x10 //Disable ALE Output. + #define GF1 0x08 //General-Purpose Flag Bit. + #define GF0 0x04 //General-Purpose Flag Bit. + #define PD 0x02 //Power-Down Mode Enable. + #define IDL 0x01 //Idle Mode Enable. + +SFR(TCON, 0x88); // Timer/Counter Control. + SBIT(TF1, 0x88, 7); // Timer 1 overflow flag. + SBIT(TR1, 0x88, 6); // Timer 1 run control flag. + SBIT(TF0, 0x88, 5); // Timer 0 overflow flag. + SBIT(TR0, 0x88, 4); // Timer 0 run control flag. + SBIT(IE1, 0x88, 3); // Interrupt 1 flag. + SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit. + SBIT(IE0, 0x88, 1); // Interrupt 0 flag. + SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit. + +SFR(TMOD, 0x89); // Timer/Counter Mode Control. + #define GATE1 0x80 // External enable for timer 1. + #define C_T1 0x40 // Timer or counter select for timer 1. + #define M1_1 0x20 // Operation mode bit 1 for timer 1. + #define M0_1 0x10 // Operation mode bit 0 for timer 1. + #define GATE0 0x08 // External enable for timer 0. + #define C_T0 0x04 // Timer or counter select for timer 0. + #define M1_0 0x02 // Operation mode bit 1 for timer 0. + #define M0_0 0x01 // Operation mode bit 0 for timer 0. + +SFR(TL0, 0x8A); // Timer 0 LSB. +SFR(TL1, 0x8B); // Timer 1 LSB. +SFR(TH0, 0x8C); // Timer 0 MSB. +SFR(TH1, 0x8D); // Timer 1 MSB. + +SFR(P0, 0x80); // Port 0 + SBIT(P0_0, 0x80, 0); // Port 0 bit 0. + SBIT(P0_1, 0x80, 1); // Port 0 bit 1. + SBIT(P0_2, 0x80, 2); // Port 0 bit 2. + SBIT(P0_3, 0x80, 3); // Port 0 bit 3. + SBIT(P0_4, 0x80, 4); // Port 0 bit 4. + SBIT(P0_5, 0x80, 5); // Port 0 bit 5. + SBIT(P0_6, 0x80, 6); // Port 0 bit 6. + SBIT(P0_7, 0x80, 7); // Port 0 bit 7. + +SFR(P1, 0x90); // Port 1 + SBIT(P1_0, 0x90, 0); // Port 1 bit 0. + SBIT(P1_1, 0x90, 1); // Port 1 bit 1. + SBIT(P1_2, 0x90, 2); // Port 1 bit 2. + SBIT(P1_3, 0x90, 3); // Port 1 bit 3. + SBIT(P1_4, 0x90, 4); // Port 1 bit 4. + SBIT(P1_5, 0x90, 5); // Port 1 bit 5. + SBIT(P1_6, 0x90, 6); // Port 1 bit 6. + SBIT(P1_7, 0x90, 7); // Port 1 bit 7. + // Alternate names + SBIT(T2EX, 0x90, 1); //Capture/reload trigger for Counter 2. + SBIT(T2, 0x90, 0); //Input to Timer/Counter 2. + +SFR(P2, 0xA0); // Port 2 + SBIT(P2_0, 0xA0, 0); // Port 2 bit 0. + SBIT(P2_1, 0xA0, 1); // Port 2 bit 1. + SBIT(P2_2, 0xA0, 2); // Port 2 bit 2. + SBIT(P2_3, 0xA0, 3); // Port 2 bit 3. + SBIT(P2_4, 0xA0, 4); // Port 2 bit 4. + SBIT(P2_5, 0xA0, 5); // Port 2 bit 5. + SBIT(P2_6, 0xA0, 6); // Port 2 bit 6. + SBIT(P2_7, 0xA0, 7); // Port 2 bit 7. + +SFR(P3, 0xB0); // Port 3 + SBIT(P3_0, 0xB0, 0); // Port 3 bit 0. + SBIT(P3_1, 0xB0, 1); // Port 3 bit 1. + SBIT(P3_2, 0xB0, 2); // Port 3 bit 2. + SBIT(P3_3, 0xB0, 3); // Port 3 bit 3. + SBIT(P3_4, 0xB0, 4); // Port 3 bit 4. + SBIT(P3_5, 0xB0, 5); // Port 3 bit 5. + SBIT(P3_6, 0xB0, 6); // Port 3 bit 6. + SBIT(P3_7, 0xB0, 7); // Port 3 bit 7. + // Alternate names. + SBIT(RXD, 0xB0, 0); + SBIT(TXD, 0xB0, 1); + SBIT(INT0, 0xB0, 2); + SBIT(INT1, 0xB0, 3); + SBIT(T0, 0xB0, 4); + SBIT(T1, 0xB0, 5); + SBIT(WR, 0xB0, 6); + SBIT(RD, 0xB0, 7); + +SFR(I2CADD, 0x9B); // I2C Address Register 1. +SFR(I2CADD1, 0x91); // I2C Address Register 2. +SFR(I2CADD2, 0x92); // I2C Address Register 3. +SFR(I2CADD3, 0x93); // I2C Address Register 4. +SFR(I2CDAT, 0x9A); // I2C Data Register. + +SFR(SCON, 0x98); // Serial Port Control. + SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0. + SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1. + SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2. + SBIT(REN, 0x98, 4); // Enables serial reception. + SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3. + SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received. + SBIT(TI, 0x98, 1); // Transmit interrupt flag. + SBIT(RI, 0x98, 0); // Receive interrupt flag. + +SFR(SBUF, 0x99); // Serial Data Buffer. + +//For these two, you may want to check page 68 of the datasheet... +SFR(T3FD, 0x9D); // Fractional divider ratio. +SFR(T3CON, 0x9E); // T3CON is the baud rate control SFR, allowing Timer 3 to be + // used to set up the UART baud rate, and setting up the binary + // divider (DIV). +#define T3BAUDEN 0x80 // T3 UART BAUD Enable. +#define DIV2 0x04 // Binary Divider Factor bit 3. +#define DIV1 0x02 // Binary Divider Factor bit 2. +#define DIV0 0x01 // Binary Divider Factor bit 1. + +SFR(TIMECON, 0xA1); // TIC Control Register. + #define TFH 0x40 // Twenty-Four Hour Select Bit. + #define ITS1 0x20 // Interval Timebase Selection Bit 1. + #define ITS0 0x10 // Interval Timebase Selection Bit 1. + #define STI 0x08 // Single Time Interval Bit. + #define TII 0x04 // TIC Interrupt Bit. + #define TIEN 0x02 // Time Interval Enable Bit. + #define TCEN 0x01 // Time Clock Enable Bit. + +SFR(HTHSEC, 0xA2); // Hundredths Seconds Time Register. +SFR(SEC, 0xA3); // Seconds Time Register. +SFR(MIN, 0xA4); // Minutes Time Register. +SFR(HOUR, 0xA5); // Hours Time Register. +SFR(INTVAL, 0xA6); // User Time Interval Select Register. + +SFR(IE, 0xA8); // Interrupt Enable. + SBIT(EA, 0xA8, 7); // Global Interrupt Enable. + SBIT(EADC, 0xA8, 6); // ADC Interrupt Enable. + SBIT(ET2, 0xA8, 5); // Timer 2 Interrupt Enable. + SBIT(ES, 0xA8, 4); // Serial Interrupt Enable. + SBIT(ET1, 0xA8, 3); // Timer 1 Interrupt Enable. + SBIT(EX1, 0xA8, 2); // External 1 Interrupt Enable. + SBIT(ET0, 0xA8, 1); // Timer 0 Interrupt Enable. + SBIT(EX0, 0xA8, 0); // External 0 Interrupt Enable. + +SFR(IEIP2, 0xA9); // Secondary Interrupt Enable Register + #define PTI 0x40 // Priority for time interval interrupt. + #define PPSM 0x20 // Priority for power supply monitor interrupt. + #define PSI2 0x10 // Priority for SPI/I2C interrupt. Same name as bit in IP??? + #define ETI 0x04 // Enable time interval counter interrupts. + #define EPSMI 0x02 // Enable power supply monitor interrupts. + #define ESI 0x01 // Enable SPI or I2C serial port interrupts. + +SFR(PWMCON, 0xAE); //PWM control. + #define SNGL 0x80 // Turns off PMW output at P2.6 or P3.4. + #define MD2 0x40 // PWM Mode Bit 2. + #define MD1 0x20 // PWM Mode Bit 2. + #define MD0 0x10 // PWM Mode Bit 2. + #define CDIV1 0x08 // PWM Clock Divider bit 1. + #define CDIV0 0x04 // PWM Clock Divider bit 1. + #define CSEL1 0x02 // PWM Clock Select bit 1. (Typo in datasheet???) + #define CSEL0 0x01 // PWM Clock Select bit 0. + +SFR(PWM0L, 0xB1); // PWM 0 duty cycle low. +SFR(PWM0H, 0xB2); // PWM 0 duty cycle high. +SFR(PWM1L, 0xB3); // PWM 1 duty cycle low. +SFR(PWM1H, 0xB4); // PWM 1 duty cycle high. + +SFR(IP, 0xB8); // Interrupt Priority Reg. + SBIT(PSI, 0xB8, 7); // Priority for SPI/I2C interrupt. + SBIT(PADC, 0xB8, 6); // ADC interrupt priority bit. + SBIT(PT2, 0xB8, 5); // Timer 2 interrupt priority bit. + SBIT(PS, 0xB8, 4); // Serial Port interrupt priority bit. + SBIT(PT1, 0xB8, 3); // Timer 1 interrupt priority bit. + SBIT(PX1, 0xB8, 2); // External interrupt 1 priority bit. + SBIT(PT0, 0xB8, 1); // Timer 0 interrupt priority bit. + SBIT(PX0, 0xB8, 0); // External interrupt 0 priority bit. + +SFR(ECON, 0xB9); // Flash/EE Memory Control SFR. +SFR(EDATA1, 0xBC); // EE page data byte 1. +SFR(EDATA2, 0xBD); // EE page data byte 2. +SFR(EDATA3, 0xBE); // EE page data byte 3. +SFR(EDATA4, 0xBF); // EE page data byte 4. +SFR(EADRL, 0xC6); // EE address low. +SFR(EADRH, 0xC7); // EE address high. + +SFR(WDCON, 0xC0); //Watchdog Timer Control Register. + SBIT(PRE3, 0xc0, 7); // Timeout period bit 4. + SBIT(PRE2, 0xc0, 6); // Timeout period bit 3. + SBIT(PRE1, 0xc0, 5); // Timeout period bit 2. + SBIT(PRE0, 0xc0, 4); // Timeout period bit 1. + SBIT(WDIR, 0xc0, 3); // Watchdog Interrupt Response Enable Bit. + SBIT(WDS, 0xc0, 2); // Watchdog Status Bit. + SBIT(WDE, 0xc0, 1); // Watchdog Enable Bit. + SBIT(WDWR, 0xc0, 0); // Watchdog Write Enable Bit. + +SFR(CHIPID, 0xC2); // System Self-Identification? WARNING: No description in the datasheet. + +SFR(T2CON, 0xC8); // Timer / Counter 2 Control. + SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag. + SBIT(EXF2, 0xC8, 6); // Timer 2 external flag. + SBIT(RCLK, 0xC8, 5); // Receive clock flag. + SBIT(TCLK, 0xC8, 4); // Transmit clock flag. + SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag. + SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2. + SBIT(CNT2, 0xC8, 1); // Timer or coutner select. + SBIT(CAP2, 0xC8, 0); // Capture/reload flag. + +SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB. +SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB. +SFR(TL2, 0xCC); // Timer 2 LSB. +SFR(TH2, 0xCD); // Timer 2 MSB. + +SFR(PSW, 0xD0); // Program Status Word. + SBIT(CY, 0xD0, 7); // Carry Flag. + SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag. + SBIT(F0, 0xD0, 5); // User-Defined Flag. + SBIT(RS1, 0xD0, 4); // Register Bank Select 1. + SBIT(RS0, 0xD0, 3); // Register Bank Select 0. + SBIT(OV, 0xD0, 2); // Overflow Flag. + SBIT(F1, 0xD0, 1); // User-Defined Flag. + SBIT(P, 0xD0, 0); // Parity Flag. + +SFR(DMAL, 0xD2); // DMA mode address pointer low. +SFR(DMAH, 0xD3); // DMA mode address pointer high. +SFR(DMAP, 0xD4); // DMA mode address pointer page. (?) +SFR(PLLCON, 0xD7); // PLL Control Register. + +SFR(PSMCON, 0xDF); // Power supply monitor. + #define CMPD 0x40 // DVDD Comparator Bit. + #define PSMI 0x20 // Power Supply Monitor Interrupt Bit. + #define TPD1 0x10 // DVDD Trip Point Selection Bit 2. + #define TPD0 0x08 // DVDD Trip Point Selection Bit 1. + #define PSMEN 0x01 // Power Supply Monitor Enable Bit. + +SFR(ACC, 0xE0); // Accumulator + SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0. + SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1. + SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2. + SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3. + SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4. + SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5. + SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6. + SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7. + +SFR(I2CCON, 0xE8); // I2C Control Register + // Master mode + SBIT(MDO, 0xE8, 7); // I2C Software Master Data Output Bit. + SBIT(MDE, 0xE8, 6); // I2C Software Master Data Output Enable Bit. + SBIT(MCO, 0xE8, 5); // I2C Software Master Clock Output Bit. + SBIT(MDI, 0xE8, 4); // I2C Software Master Data Input Bit. + // Slave mode + SBIT(I2CSI, 0xE8, 7); // I2C Stop Interrupt Enable Bit. + SBIT(I2CGC, 0xE8, 6); // I2C General Call Status Bit. + SBIT(I2CID1, 0xE8, 5); // I2C Interrupt Decode Bit 2. + SBIT(I2CID0, 0xE8, 4); // I2C Interrupt Decode Bit 1. + SBIT(I2CM, 0xE8, 3); // I2C Master/Slave Mode Bit. + SBIT(I2CRS, 0xE8, 2); // I2C Reset Bit. + SBIT(I2CTX, 0xE8, 1); // I2C Direction Transfer Bit. + SBIT(I2CI, 0xE8, 0); // I2C Interrupt Bit. + +SFR(B, 0xF0); // B Register + SBIT(B_0, 0xF0, 0); // Register B bit 0. + SBIT(B_1, 0xF0, 1); // Register B bit 1. + SBIT(B_2, 0xF0, 2); // Register B bit 2. + SBIT(B_3, 0xF0, 3); // Register B bit 3. + SBIT(B_4, 0xF0, 4); // Register B bit 4. + SBIT(B_5, 0xF0, 5); // Register B bit 5. + SBIT(B_6, 0xF0, 6); // Register B bit 6. + SBIT(B_7, 0xF0, 7); // Register B bit 7. + +SFR(ADCCON1, 0xEF); //ADC Control SFR 1 + //WARNING: bit 7 is named MD1 in the datasheet, but that name is already used. + #define MD 0x80 // The mode bit selects the active operating mode of the ADC. + #define EXT_REF 0x40 // Set by the user to select an external reference. + #define CK1 0x20 // The ADC clock divide bit 1. + #define CK0 0x10 // The ADC clock divide bit 0. + #define AQ1 0x08 // ADC acquisition select bit 1. + #define AQ0 0x04 // ADC acquisition select bit 0. + #define T2C 0x02 // The Timer 2 conversion bit. + #define EXC 0x01 // The external trigger enable bit. + +SFR(ADCCON2, 0xD8); // ADC Control SFR 2. + SBIT(ADCI, 0xD8, 7); // ADC Interrupt Bit. + SBIT(DMA, 0xD8, 6); // DMA Mode Enable Bit. + SBIT(CCONV, 0xD8, 5); // Continuous Conversion Bit. + SBIT(SCONV, 0xD8, 4); // Single Conversion Bit. + SBIT(CS3, 0xD8, 3); // Channel Selection Bit 4. + SBIT(CS2, 0xD8, 2); // Channel Selection Bit 3. + SBIT(CS1, 0xD8, 1); // Channel Selection Bit 2. + SBIT(CS0, 0xD8, 0); // Channel Selection Bit 1. + +SFR(ADCCON3, 0xF5); //ADC Control SFR 3 + #define BUSY 0x80 // ADC Busy Status Bit. + #define AVGS1 0x20 // Number of Average Selection Bit 2. + #define AVGS0 0x10 // Number of Average Selection Bit 1. + #define TYPICAL 0x02 // Calibration Type Select Bit. + #define SCAL 0x01 // Start Calibration Cycle Bit. + +SFR(ADCDATAL, 0xD9); // ADC Result byte low. +SFR(ADCDATAH, 0xDA); // ADC Result byte high. WARNING: bits 4 to 7 are the ADC channel! +SFR(ADCOFSL, 0xF1); // Offset calibration coefficient byte (low). +SFR(ADCOFSH, 0xF2); // Offset calibration coefficient byte (high). +SFR(ADCGAINL, 0xF3); // Gain calibration coefficient byte (low). +SFR(ADCGAINH, 0xF4); // Gain calibration coefficient byte (high). + +SFR(SPIDAT, 0xF7); // SPI Data Register. + +SFR(SPICON, 0xF8); // SPI Control Register. + SBIT(ISPI, 0xF8, 7); // SPI Interrupt Bit. + SBIT(WCOL, 0xF8, 6); // Write Collision Error Bit. + SBIT(SPE, 0xF8, 5); // SPI Interface Enable Bit. + SBIT(SPIM, 0xF8, 4); // SPI Master/Slave Mode Select Bit. + SBIT(CPOL, 0xF8, 3); // Clock Polarity Select Bit. + SBIT(CPHA, 0xF8, 2); // Clock Phase Select Bit. + SBIT(SPR1, 0xF8, 1); // SPI Bit Rate Select Bit 2. + SBIT(SPR0, 0xF8, 0); // SPI Bit Rate Select Bit 1. + +SFR(DAC0L, 0xF9); // DAC0 Data Low Byte. +SFR(DAC0H, 0xFA); // DAC0 Data High Byte. +SFR(DAC1L, 0xFB); // DAC1 Data Low Byte. +SFR(DAC1H, 0xFC); // DAC1 Data High Byte. +SFR(DACCON, 0xFD); // DAC Control Register. + #define MODE 0x80 // 8/12 bit selection. + #define RNG1 0x40 // DAC1 Range Select Bit. + #define RNG0 0x20 // DAC0 Range Select Bit. + #define CLR1 0x10 // DAC1 Clear Bit. + #define CLR0 0x08 // DAC0 Clear Bit. + #define SYNC 0x04 // DAC0/1 Update Synchronization Bit. + #define PD1 0x02 // DAC1 Power-Down Bit. + #define PD0 0x01 // DAC0 Power-Down Bit. + +#endif //REG_ADUC84X_H diff --git a/device/include/mcs51/C8051F360.h b/device/include/mcs51/C8051F360.h index 68142507..d920e526 100644 --- a/device/include/mcs51/C8051F360.h +++ b/device/include/mcs51/C8051F360.h @@ -23,7 +23,7 @@ #include -/* All Pages */ +/* All Pages */ SFR(P0, 0x80); // Port 0 SBIT(P0_0, 0x80, 0); // Port 0 bit 0 @@ -244,7 +244,7 @@ SFR16(PCA0CP5, 0xFD); // PCA Capture 5 Word SFR(PCA0CPH5, 0xFE); // PCA Capture 5 High Byte SFR(VDM0CN, 0xFF); // VDD Monitor Control -/* Page 0x00 */ +/* Page 0x00 */ SFR(PSCTL, 0x8F); // Program Store R/W Control SFR16(MAC0A, 0xA4); // MAC0 A Register Word @@ -273,7 +273,7 @@ SFR(P1MASK, 0xE2); // Port 1 Mask SFR(P0MAT, 0xF3); // Port 0 Match SFR(P0MASK, 0xF4); // Port 0 Mask -/* Page 0x0F */ +/* Page 0x0F */ SFR(CCH0CN, 0x84); // Cache Control SFR(CLKSEL, 0x8F); // Clock Select @@ -339,7 +339,7 @@ SFR(EMI0TC, 0xF7); // EMIF Timing Control #define INT_UART0 4 // Serial Port 0 #define INT_TIMER2 5 // Timer2 Overflow #define INT_SPI0 6 // Serial Peripheral Interface 0 -#define INT_SMBUS0 7 // SMBus0 Interface +#define INT_SMBUS0 7 // SMBus0 Interface // 8 Reserved #define INT_ADC0_WINDOW 9 // ADC0 Window Comparison #define INT_ADC0_EOC 10 // ADC0 End Of Conversion diff --git a/device/include/mcs51/P89LPC901.h b/device/include/mcs51/P89LPC901.h index 7a41ce19..dc3caeda 100644 --- a/device/include/mcs51/P89LPC901.h +++ b/device/include/mcs51/P89LPC901.h @@ -1,184 +1,184 @@ -/*-------------------------------------------------------------------------- -P89LPC901.H -(English) -This header allows to use the microcontroler Philips P89LPC901 -with the compiler SDCC. - -Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - -(Spanish-Español) -Archivo encabezador para el ucontrolador Philips P89LPC901. -Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com -Uso libre ---------------------------------------------------------------------------*/ - -#ifndef __REG901_H__ -#define __REG901_H__ - -/* BYTE Registers */ -__sfr __at (0x80) P0 ; -__sfr __at (0x84) P0M1 ; -__sfr __at (0x85) P0M2 ; - -__sfr __at (0x90) P1 ; -__sfr __at (0x91) P1M1 ; -__sfr __at (0x92) P1M2 ; - -__sfr __at (0xB0) P3 ; -__sfr __at (0xB1) P3M1 ; -__sfr __at (0xB2) P3M2 ; -//------------------ -__sfr __at (0xD0) PSW ; -__sfr __at (0xE0) ACC ; -__sfr __at (0xF0) B ; -__sfr __at (0x81) SP ; -__sfr __at (0x82) DPL ; -__sfr __at (0x83) DPH ; -//------------------ -__sfr __at (0xA2) AUXR1 ; -__sfr __at (0xAC) CMP1 ; -__sfr __at (0x95) DIVM ; - -__sfr __at (0xE7) FMADRH ; -__sfr __at (0xE6) FMADRL ; -__sfr __at (0xE4) FMCON ; -__sfr __at (0xE5) FMDATA ; - -__sfr __at (0xA8) IEN0 ; -__sfr __at (0xE8) IEN1 ; - -__sfr __at (0xB8) IP0 ; -__sfr __at (0xB7) IP0H ; -__sfr __at (0xF8) IP1 ; -__sfr __at (0xF7) IP1H ; - -__sfr __at (0x94) KBCON ; -__sfr __at (0x86) KBMASK ; -__sfr __at (0x93) KBPATN ; - -__sfr __at (0x87) PCON ; -__sfr __at (0xB5) PCONA ; -__sfr __at (0xB6) PCONB ; - -__sfr __at (0xF6) PT0AD ; -__sfr __at (0xDF) RSTSRC ; - -__sfr __at (0xD1) RTCCON ; -__sfr __at (0xD2) RTCH ; -__sfr __at (0xD3) RTCL ; - -__sfr __at (0x8F) TAMOD ; -__sfr __at (0x88) TCON ; -__sfr __at (0x8A) TL0 ; -__sfr __at (0x8B) TL1 ; -__sfr __at (0x8C) TH0 ; -__sfr __at (0x8D) TH1 ; -__sfr __at (0x89) TMOD ; -__sfr __at (0x96) TRIM ; - -__sfr __at (0xA7) WDCON ; -__sfr __at (0xC1) WDL ; -__sfr __at (0xC2) WFEED1 ; -__sfr __at (0xC3) WFEED2 ; - - -/* BIT Registers */ -/* PSW */ -__sbit __at (0xD7) PSW_7; -__sbit __at (0xD6) PSW_6; -__sbit __at (0xD5) PSW_5; -__sbit __at (0xD4) PSW_4; -__sbit __at (0xD3) PSW_3; -__sbit __at (0xD2) PSW_2; -__sbit __at (0xD1) PSW_1; -__sbit __at (0xD0) PSW_0; - -#define CY PSW_7 -#define AC PSW_6 -#define F0 PSW_5 -#define RS1 PSW_4 -#define RS0 PSW_3 -#define OV PSW_2 -#define F1 PSW_1 -#define P PSW_0 - -/* TCON */ -__sbit __at (0x8F) TCON_7; -__sbit __at (0x8E) TCON_6; -__sbit __at (0x8D) TCON_5; -__sbit __at (0x8C) TCON_4; - -#define TF1 TCON_7 -#define TR1 TCON_6 -#define TF0 TCON_5 -#define TR0 TCON_4 - -/* IEN0 */ -__sbit __at (0xAF) IEN0_7; -__sbit __at (0xAE) IEN0_6; -__sbit __at (0xAD) IEN0_5; -__sbit __at (0xAB) IEN0_3; -__sbit __at (0xA9) IEN0_1; - -#define EA IEN0_7 -#define EWDRT IEN0_6 -#define EBO IEN0_5 -#define ET1 IEN0_3 -#define ET0 IEN0_1 - -/* IEN1 */ -__sbit __at (0xEA) IEN1_2; -__sbit __at (0xE9) IEN1_1; - -#define EC IEN1_2 -#define EKBI IEN1_1 - -/* IP0 */ -__sbit __at (0xBE) IP0_6; -__sbit __at (0xBD) IP0_5; -__sbit __at (0xBB) IP0_3; -__sbit __at (0xB9) IP0_1; - -#define PWDRT IP0_6 -#define PB0 IP0_5 -#define PT1 IP0_3 -#define PT0 IP0_1 - -/* P0 */ -__sbit __at (0x85) P0_5; -__sbit __at (0x84) P0_4; - -#define KB5 P0_5 -#define CMPREF P0_5 -#define KB4 P0_4 -#define CIN1A P0_4 - -/* P1 */ -__sbit __at (0x95) P1_5; -__sbit __at (0x92) P1_2; - -#define RST P1_5 -#define T0 P1_2 - -/* P3 */ -__sbit __at (0xB1) P3_1; -__sbit __at (0xB0) P3_0; - -#define XTAL1 P3_1 -#define XTAL2 P3_0 - -#endif +/*-------------------------------------------------------------------------- +P89LPC901.H +(English) +This header allows to use the microcontroler Philips P89LPC901 +with the compiler SDCC. + +Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +(Spanish-Español) +Archivo encabezador para el ucontrolador Philips P89LPC901. +Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com +Uso libre +--------------------------------------------------------------------------*/ + +#ifndef __REG901_H__ +#define __REG901_H__ + +/* BYTE Registers */ +__sfr __at (0x80) P0 ; +__sfr __at (0x84) P0M1 ; +__sfr __at (0x85) P0M2 ; + +__sfr __at (0x90) P1 ; +__sfr __at (0x91) P1M1 ; +__sfr __at (0x92) P1M2 ; + +__sfr __at (0xB0) P3 ; +__sfr __at (0xB1) P3M1 ; +__sfr __at (0xB2) P3M2 ; +//------------------ +__sfr __at (0xD0) PSW ; +__sfr __at (0xE0) ACC ; +__sfr __at (0xF0) B ; +__sfr __at (0x81) SP ; +__sfr __at (0x82) DPL ; +__sfr __at (0x83) DPH ; +//------------------ +__sfr __at (0xA2) AUXR1 ; +__sfr __at (0xAC) CMP1 ; +__sfr __at (0x95) DIVM ; + +__sfr __at (0xE7) FMADRH ; +__sfr __at (0xE6) FMADRL ; +__sfr __at (0xE4) FMCON ; +__sfr __at (0xE5) FMDATA ; + +__sfr __at (0xA8) IEN0 ; +__sfr __at (0xE8) IEN1 ; + +__sfr __at (0xB8) IP0 ; +__sfr __at (0xB7) IP0H ; +__sfr __at (0xF8) IP1 ; +__sfr __at (0xF7) IP1H ; + +__sfr __at (0x94) KBCON ; +__sfr __at (0x86) KBMASK ; +__sfr __at (0x93) KBPATN ; + +__sfr __at (0x87) PCON ; +__sfr __at (0xB5) PCONA ; +__sfr __at (0xB6) PCONB ; + +__sfr __at (0xF6) PT0AD ; +__sfr __at (0xDF) RSTSRC ; + +__sfr __at (0xD1) RTCCON ; +__sfr __at (0xD2) RTCH ; +__sfr __at (0xD3) RTCL ; + +__sfr __at (0x8F) TAMOD ; +__sfr __at (0x88) TCON ; +__sfr __at (0x8A) TL0 ; +__sfr __at (0x8B) TL1 ; +__sfr __at (0x8C) TH0 ; +__sfr __at (0x8D) TH1 ; +__sfr __at (0x89) TMOD ; +__sfr __at (0x96) TRIM ; + +__sfr __at (0xA7) WDCON ; +__sfr __at (0xC1) WDL ; +__sfr __at (0xC2) WFEED1 ; +__sfr __at (0xC3) WFEED2 ; + + +/* BIT Registers */ +/* PSW */ +__sbit __at (0xD7) PSW_7; +__sbit __at (0xD6) PSW_6; +__sbit __at (0xD5) PSW_5; +__sbit __at (0xD4) PSW_4; +__sbit __at (0xD3) PSW_3; +__sbit __at (0xD2) PSW_2; +__sbit __at (0xD1) PSW_1; +__sbit __at (0xD0) PSW_0; + +#define CY PSW_7 +#define AC PSW_6 +#define F0 PSW_5 +#define RS1 PSW_4 +#define RS0 PSW_3 +#define OV PSW_2 +#define F1 PSW_1 +#define P PSW_0 + +/* TCON */ +__sbit __at (0x8F) TCON_7; +__sbit __at (0x8E) TCON_6; +__sbit __at (0x8D) TCON_5; +__sbit __at (0x8C) TCON_4; + +#define TF1 TCON_7 +#define TR1 TCON_6 +#define TF0 TCON_5 +#define TR0 TCON_4 + +/* IEN0 */ +__sbit __at (0xAF) IEN0_7; +__sbit __at (0xAE) IEN0_6; +__sbit __at (0xAD) IEN0_5; +__sbit __at (0xAB) IEN0_3; +__sbit __at (0xA9) IEN0_1; + +#define EA IEN0_7 +#define EWDRT IEN0_6 +#define EBO IEN0_5 +#define ET1 IEN0_3 +#define ET0 IEN0_1 + +/* IEN1 */ +__sbit __at (0xEA) IEN1_2; +__sbit __at (0xE9) IEN1_1; + +#define EC IEN1_2 +#define EKBI IEN1_1 + +/* IP0 */ +__sbit __at (0xBE) IP0_6; +__sbit __at (0xBD) IP0_5; +__sbit __at (0xBB) IP0_3; +__sbit __at (0xB9) IP0_1; + +#define PWDRT IP0_6 +#define PB0 IP0_5 +#define PT1 IP0_3 +#define PT0 IP0_1 + +/* P0 */ +__sbit __at (0x85) P0_5; +__sbit __at (0x84) P0_4; + +#define KB5 P0_5 +#define CMPREF P0_5 +#define KB4 P0_4 +#define CIN1A P0_4 + +/* P1 */ +__sbit __at (0x95) P1_5; +__sbit __at (0x92) P1_2; + +#define RST P1_5 +#define T0 P1_2 + +/* P3 */ +__sbit __at (0xB1) P3_1; +__sbit __at (0xB0) P3_0; + +#define XTAL1 P3_1 +#define XTAL2 P3_0 + +#endif diff --git a/device/include/mcs51/P89LPC922.h b/device/include/mcs51/P89LPC922.h index a709ff35..ce87fdde 100644 --- a/device/include/mcs51/P89LPC922.h +++ b/device/include/mcs51/P89LPC922.h @@ -1,280 +1,280 @@ -/*------------------------------------------------------------------//-------- -P89LPC922.H -(English) -This header allows to use the microcontroler Philips P89LPC922 -with the compiler SDCC. - -Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - -(Spanish-Español) -Archivo encabezador para el ucontrolador Philips P89LPC922. -Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com -Uso libre -//------------------------------------------------------------------//--//------*/ -#ifndef __REG922_H__ -#define __REG922_H__ - -//* BYTE Registers *// -__sfr __at (0x80) P0 ; -__sfr __at (0x90) P1 ; -__sfr __at (0xB0) P3 ; -__sfr __at (0xD0) PSW ; -__sfr __at (0xE0) ACC ; -__sfr __at (0xF0) B ; -__sfr __at (0x81) SP ; -__sfr __at (0x82) DPL ; -__sfr __at (0x83) DPH ; -__sfr __at (0x87) PCON ; -__sfr __at (0x88) TCON ; -__sfr __at (0x89) TMOD ; -__sfr __at (0x8A) TL0 ; -__sfr __at (0x8B) TL1 ; -__sfr __at (0x8B) TH0 ; -__sfr __at (0x8D) TH1 ; -__sfr __at (0xA8) IEN0 ; -__sfr __at (0xB8) IP0 ; -__sfr __at (0x98) SCON ; -__sfr __at (0x99) SBUF ; - - -__sfr __at (0xA2) AUXR1 ; -__sfr __at (0xA9) SADDR ; -__sfr __at (0xB9) SADEN ; -__sfr __at (0xBE) BRGR0 ; -__sfr __at (0xBF) BRGR1 ; -__sfr __at (0xBD) BRGCON ; -__sfr __at (0xAC) CMP1 ; -__sfr __at (0xAD) CMP2 ; -__sfr __at (0x95) DIVM ; -__sfr __at (0xE7) FMADRH ; -__sfr __at (0xE6) FMADRL ; -__sfr __at (0xE4) FMCON ; -__sfr __at (0xE5) FMDATA ; -__sfr __at (0xDB) I2ADR ; -__sfr __at (0xD8) I2CON ; -__sfr __at (0xDA) I2DAT ; -__sfr __at (0xDD) I2SCLH ; -__sfr __at (0xDC) I2SCLL ; -__sfr __at (0xD9) I2STAT ; -__sfr __at (0xF8) IP1 ; -__sfr __at (0xF7) IP1H ; -__sfr __at (0x94) KBCON ; -__sfr __at (0x86) KBMASK ; -__sfr __at (0x93) KBPATN ; -__sfr __at (0x84) P0M1 ; -__sfr __at (0x85) P0M2 ; -__sfr __at (0x91) P1M1 ; -__sfr __at (0x92) P1M2 ; -__sfr __at (0xB1) P3M1 ; -__sfr __at (0xB2) P3M2 ; -__sfr __at (0xB5) PCONA ; -__sfr __at (0xF6) PT0AD ; -__sfr __at (0xDF) RSTSRC ; -__sfr __at (0xD1) RTCCON ; -__sfr __at (0xD2) RTCH ; -__sfr __at (0xD3) RTCL ; -__sfr __at (0xBA) SSTAT ; -__sfr __at (0x8F) TAMOD ; -__sfr __at (0x96) TRIM ; -__sfr __at (0xA7) WDCON ; -__sfr __at (0xC1) WDL ; -__sfr __at (0xC2) WFEED1 ; -__sfr __at (0xC3) WFEED2 ; -__sfr __at (0xB7) IP0H ; -__sfr __at (0xE8) IEN1 ; - -/* BIT Registers */ -/* PSW */ -__sbit __at (0xD0) PSW_0 ; -__sbit __at (0xD1) PSW_1 ; -__sbit __at (0xD2) PSW_2 ; -__sbit __at (0xD3) PSW_3 ; -__sbit __at (0xD4) PSW_4 ; -__sbit __at (0xD5) PSW_5 ; -__sbit __at (0xD6) PSW_6 ; -__sbit __at (0xD7) PSW_7 ; - -#define CY PSW_7 -#define AC PSW_6 -#define F0 PSW_5 -#define RS1 PSW_4 -#define RS0 PSW_3 -#define OV PSW_2 -#define F1 PSW_1 -#define P PSW_0 - -/* TCON */ -__sbit __at (0x8F) TCON_7 ; -__sbit __at (0x8E) TCON_6 ; -__sbit __at (0x8D) TCON_5 ; -__sbit __at (0x8C) TCON_4 ; -__sbit __at (0x8B) TCON_3 ; -__sbit __at (0x8A) TCON_2 ; -__sbit __at (0x89) TCON_1 ; -__sbit __at (0x88) TCON_0 ; - -#define TF1 TCON_7 -#define TR1 TCON_6 -#define TF0 TCON_5 -#define TR0 TCON_4 -#define IE1 TCON_3 -#define IT1 TCON_2 -#define IE0 TCON_1 -#define IT0 TCON_0 - -/* IEN0 */ -__sbit __at (0xAF) IEN0_7 ; -__sbit __at (0xAE) IEN0_6 ; -__sbit __at (0xAD) IEN0_5 ; -__sbit __at (0xAC) IEN0_4 ; -__sbit __at (0xAB) IEN0_3 ; -__sbit __at (0xAA) IEN0_2 ; -__sbit __at (0xA9) IEN0_1 ; -__sbit __at (0xA8) IEN0_0 ; - -#define EA IEN0_7 -#define EWDRT IEN0_6 -#define EBO IEN0_5 -#define ES IEN0_4 // alternatively "ESR" -#define ESR IEN0_4 -#define ET1 IEN0_3 -#define EX1 IEN0_2 -#define ET0 IEN0_1 -#define EX0 IEN0_0 - -/* IEN1 */ -__sbit __at (0xEA) IEN1_2 ; -__sbit __at (0xE9) IEN1_1 ; -__sbit __at (0xE8) IEN1_0 ; - -#define EC IEN1_2 -#define EKBI IEN1_1 -#define EI2C IEN1_0 - -/* IP1 */ -__sbit __at (0xFE) IP1_6 ; -__sbit __at (0xFA) IP1_2 ; -__sbit __at (0xF9) IP1_1 ; -__sbit __at (0xF8) IP1_0 ; - -#define PST IP1_6 -#define PC IP1_2 -#define PKBI IP1_1 -#define PI2C IP1_0 - -/* IP0 */ -__sbit __at (0xBE) IP0_6 ; -__sbit __at (0xBD) IP0_5 ; -__sbit __at (0xBC) IP0_4 ; // alternatively "PSR" -__sbit __at (0xBB) IP0_3 ; -__sbit __at (0xBA) IP0_2 ; -__sbit __at (0xB9) IP0_1 ; -__sbit __at (0xB8) IP0_0 ; - -#define PWDRT IP0_6 -#define PBO IP0_5 -#define PS IP0_4 // alternatively "PSR" -#define PSR IP0_4 -#define PT1 IP0_3 -#define PX1 IP0_2 -#define PT0 IP0_1 -#define PX0 IP0_0 - -/* SCON */ -__sbit __at (0x98) SCON_0 ; -__sbit __at (0x99) SCON_1 ; -__sbit __at (0x9A) SCON_2 ; -__sbit __at (0x9B) SCON_3 ; -__sbit __at (0x9C) SCON_4 ; -__sbit __at (0x9D) SCON_5 ; -__sbit __at (0x9E) SCON_6 ; -__sbit __at (0x9F) SCON_7 ; - -#define SM0 SCON_7 // alternatively "FE" -#define FE SCON_7 -#define SM1 SCON_6 -#define SM2 SCON_5 -#define REN SCON_4 -#define TB8 SCON_3 -#define RB8 SCON_2 -#define TI SCON_1 -#define RI SCON_0 - -/* I2CON */ -__sbit __at (0xDE) I2CON_6 ; -__sbit __at (0xDD) I2CON_5 ; -__sbit __at (0xDC) I2CON_4 ; -__sbit __at (0xDB) I2CON_3 ; -__sbit __at (0xDA) I2CON_2 ; -__sbit __at (0xD8) I2CON_0 ; - -#define I2EN I2CON_6 -#define STA I2CON_5 -#define STO I2CON_4 -#define SI I2CON_3 -#define AA I2CON_2 -#define CRSEL I2CON_0 - -/* P0 */ -__sbit __at (0x80) P0_0 ; -__sbit __at (0x81) P0_1 ; -__sbit __at (0x82) P0_2 ; -__sbit __at (0x83) P0_3 ; -__sbit __at (0x84) P0_4 ; -__sbit __at (0x85) P0_5 ; -__sbit __at (0x86) P0_6 ; -__sbit __at (0x87) P0_7 ; - -#define KB7 P0_7 // alternatively "T1" -#define T1 P0_7 -#define KB6 P0_6 // alternatively "CMP1" -#define CMP1 P0_6 -#define KB5 P0_5 -#define KB4 P0_4 -#define KB3 P0_3 -#define KB2 P0_2 -#define KB1 P0_1 -#define KB0 P0_0 // alternatively "CMP2" -#define CMP2 P0_0 - -/* P1 */ -__sbit __at (0x90) P1_0 ; -__sbit __at (0x91) P1_1 ; -__sbit __at (0x92) P1_2 ; -__sbit __at (0x93) P1_3 ; -__sbit __at (0x94) P1_4 ; -__sbit __at (0x95) P1_5 ; -__sbit __at (0x96) P1_6 ; -__sbit __at (0x97) P1_7 ; - -#define RST P1_5 -#define INT1 P1_4 -#define INT0 P1_3 // alternatively "SDA" -#define SDA P1_3 -#define T0 P1_2 // alternatively "SCL" -#define SCL P1_2 -#define RxD P1_1 -#define TxD P1_0 - -/* P3 */ -__sbit __at (0xB0) P3_0 ; -__sbit __at (0xB1) P3_1 ; - -#define XTAL1 P3_1 -#define XTAL2 P3_0 - -#endif +/*------------------------------------------------------------------//-------- +P89LPC922.H +(English) +This header allows to use the microcontroler Philips P89LPC922 +with the compiler SDCC. + +Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +(Spanish-Español) +Archivo encabezador para el ucontrolador Philips P89LPC922. +Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com +Uso libre +//------------------------------------------------------------------//--//------*/ +#ifndef __REG922_H__ +#define __REG922_H__ + +//* BYTE Registers *// +__sfr __at (0x80) P0 ; +__sfr __at (0x90) P1 ; +__sfr __at (0xB0) P3 ; +__sfr __at (0xD0) PSW ; +__sfr __at (0xE0) ACC ; +__sfr __at (0xF0) B ; +__sfr __at (0x81) SP ; +__sfr __at (0x82) DPL ; +__sfr __at (0x83) DPH ; +__sfr __at (0x87) PCON ; +__sfr __at (0x88) TCON ; +__sfr __at (0x89) TMOD ; +__sfr __at (0x8A) TL0 ; +__sfr __at (0x8B) TL1 ; +__sfr __at (0x8B) TH0 ; +__sfr __at (0x8D) TH1 ; +__sfr __at (0xA8) IEN0 ; +__sfr __at (0xB8) IP0 ; +__sfr __at (0x98) SCON ; +__sfr __at (0x99) SBUF ; + + +__sfr __at (0xA2) AUXR1 ; +__sfr __at (0xA9) SADDR ; +__sfr __at (0xB9) SADEN ; +__sfr __at (0xBE) BRGR0 ; +__sfr __at (0xBF) BRGR1 ; +__sfr __at (0xBD) BRGCON ; +__sfr __at (0xAC) CMP1 ; +__sfr __at (0xAD) CMP2 ; +__sfr __at (0x95) DIVM ; +__sfr __at (0xE7) FMADRH ; +__sfr __at (0xE6) FMADRL ; +__sfr __at (0xE4) FMCON ; +__sfr __at (0xE5) FMDATA ; +__sfr __at (0xDB) I2ADR ; +__sfr __at (0xD8) I2CON ; +__sfr __at (0xDA) I2DAT ; +__sfr __at (0xDD) I2SCLH ; +__sfr __at (0xDC) I2SCLL ; +__sfr __at (0xD9) I2STAT ; +__sfr __at (0xF8) IP1 ; +__sfr __at (0xF7) IP1H ; +__sfr __at (0x94) KBCON ; +__sfr __at (0x86) KBMASK ; +__sfr __at (0x93) KBPATN ; +__sfr __at (0x84) P0M1 ; +__sfr __at (0x85) P0M2 ; +__sfr __at (0x91) P1M1 ; +__sfr __at (0x92) P1M2 ; +__sfr __at (0xB1) P3M1 ; +__sfr __at (0xB2) P3M2 ; +__sfr __at (0xB5) PCONA ; +__sfr __at (0xF6) PT0AD ; +__sfr __at (0xDF) RSTSRC ; +__sfr __at (0xD1) RTCCON ; +__sfr __at (0xD2) RTCH ; +__sfr __at (0xD3) RTCL ; +__sfr __at (0xBA) SSTAT ; +__sfr __at (0x8F) TAMOD ; +__sfr __at (0x96) TRIM ; +__sfr __at (0xA7) WDCON ; +__sfr __at (0xC1) WDL ; +__sfr __at (0xC2) WFEED1 ; +__sfr __at (0xC3) WFEED2 ; +__sfr __at (0xB7) IP0H ; +__sfr __at (0xE8) IEN1 ; + +/* BIT Registers */ +/* PSW */ +__sbit __at (0xD0) PSW_0 ; +__sbit __at (0xD1) PSW_1 ; +__sbit __at (0xD2) PSW_2 ; +__sbit __at (0xD3) PSW_3 ; +__sbit __at (0xD4) PSW_4 ; +__sbit __at (0xD5) PSW_5 ; +__sbit __at (0xD6) PSW_6 ; +__sbit __at (0xD7) PSW_7 ; + +#define CY PSW_7 +#define AC PSW_6 +#define F0 PSW_5 +#define RS1 PSW_4 +#define RS0 PSW_3 +#define OV PSW_2 +#define F1 PSW_1 +#define P PSW_0 + +/* TCON */ +__sbit __at (0x8F) TCON_7 ; +__sbit __at (0x8E) TCON_6 ; +__sbit __at (0x8D) TCON_5 ; +__sbit __at (0x8C) TCON_4 ; +__sbit __at (0x8B) TCON_3 ; +__sbit __at (0x8A) TCON_2 ; +__sbit __at (0x89) TCON_1 ; +__sbit __at (0x88) TCON_0 ; + +#define TF1 TCON_7 +#define TR1 TCON_6 +#define TF0 TCON_5 +#define TR0 TCON_4 +#define IE1 TCON_3 +#define IT1 TCON_2 +#define IE0 TCON_1 +#define IT0 TCON_0 + +/* IEN0 */ +__sbit __at (0xAF) IEN0_7 ; +__sbit __at (0xAE) IEN0_6 ; +__sbit __at (0xAD) IEN0_5 ; +__sbit __at (0xAC) IEN0_4 ; +__sbit __at (0xAB) IEN0_3 ; +__sbit __at (0xAA) IEN0_2 ; +__sbit __at (0xA9) IEN0_1 ; +__sbit __at (0xA8) IEN0_0 ; + +#define EA IEN0_7 +#define EWDRT IEN0_6 +#define EBO IEN0_5 +#define ES IEN0_4 // alternatively "ESR" +#define ESR IEN0_4 +#define ET1 IEN0_3 +#define EX1 IEN0_2 +#define ET0 IEN0_1 +#define EX0 IEN0_0 + +/* IEN1 */ +__sbit __at (0xEA) IEN1_2 ; +__sbit __at (0xE9) IEN1_1 ; +__sbit __at (0xE8) IEN1_0 ; + +#define EC IEN1_2 +#define EKBI IEN1_1 +#define EI2C IEN1_0 + +/* IP1 */ +__sbit __at (0xFE) IP1_6 ; +__sbit __at (0xFA) IP1_2 ; +__sbit __at (0xF9) IP1_1 ; +__sbit __at (0xF8) IP1_0 ; + +#define PST IP1_6 +#define PC IP1_2 +#define PKBI IP1_1 +#define PI2C IP1_0 + +/* IP0 */ +__sbit __at (0xBE) IP0_6 ; +__sbit __at (0xBD) IP0_5 ; +__sbit __at (0xBC) IP0_4 ; // alternatively "PSR" +__sbit __at (0xBB) IP0_3 ; +__sbit __at (0xBA) IP0_2 ; +__sbit __at (0xB9) IP0_1 ; +__sbit __at (0xB8) IP0_0 ; + +#define PWDRT IP0_6 +#define PBO IP0_5 +#define PS IP0_4 // alternatively "PSR" +#define PSR IP0_4 +#define PT1 IP0_3 +#define PX1 IP0_2 +#define PT0 IP0_1 +#define PX0 IP0_0 + +/* SCON */ +__sbit __at (0x98) SCON_0 ; +__sbit __at (0x99) SCON_1 ; +__sbit __at (0x9A) SCON_2 ; +__sbit __at (0x9B) SCON_3 ; +__sbit __at (0x9C) SCON_4 ; +__sbit __at (0x9D) SCON_5 ; +__sbit __at (0x9E) SCON_6 ; +__sbit __at (0x9F) SCON_7 ; + +#define SM0 SCON_7 // alternatively "FE" +#define FE SCON_7 +#define SM1 SCON_6 +#define SM2 SCON_5 +#define REN SCON_4 +#define TB8 SCON_3 +#define RB8 SCON_2 +#define TI SCON_1 +#define RI SCON_0 + +/* I2CON */ +__sbit __at (0xDE) I2CON_6 ; +__sbit __at (0xDD) I2CON_5 ; +__sbit __at (0xDC) I2CON_4 ; +__sbit __at (0xDB) I2CON_3 ; +__sbit __at (0xDA) I2CON_2 ; +__sbit __at (0xD8) I2CON_0 ; + +#define I2EN I2CON_6 +#define STA I2CON_5 +#define STO I2CON_4 +#define SI I2CON_3 +#define AA I2CON_2 +#define CRSEL I2CON_0 + +/* P0 */ +__sbit __at (0x80) P0_0 ; +__sbit __at (0x81) P0_1 ; +__sbit __at (0x82) P0_2 ; +__sbit __at (0x83) P0_3 ; +__sbit __at (0x84) P0_4 ; +__sbit __at (0x85) P0_5 ; +__sbit __at (0x86) P0_6 ; +__sbit __at (0x87) P0_7 ; + +#define KB7 P0_7 // alternatively "T1" +#define T1 P0_7 +#define KB6 P0_6 // alternatively "CMP1" +#define CMP1 P0_6 +#define KB5 P0_5 +#define KB4 P0_4 +#define KB3 P0_3 +#define KB2 P0_2 +#define KB1 P0_1 +#define KB0 P0_0 // alternatively "CMP2" +#define CMP2 P0_0 + +/* P1 */ +__sbit __at (0x90) P1_0 ; +__sbit __at (0x91) P1_1 ; +__sbit __at (0x92) P1_2 ; +__sbit __at (0x93) P1_3 ; +__sbit __at (0x94) P1_4 ; +__sbit __at (0x95) P1_5 ; +__sbit __at (0x96) P1_6 ; +__sbit __at (0x97) P1_7 ; + +#define RST P1_5 +#define INT1 P1_4 +#define INT0 P1_3 // alternatively "SDA" +#define SDA P1_3 +#define T0 P1_2 // alternatively "SCL" +#define SCL P1_2 +#define RxD P1_1 +#define TxD P1_0 + +/* P3 */ +__sbit __at (0xB0) P3_0 ; +__sbit __at (0xB1) P3_1 ; + +#define XTAL1 P3_1 +#define XTAL2 P3_0 + +#endif diff --git a/device/include/mcs51/P89LPC925.h b/device/include/mcs51/P89LPC925.h index 5541b107..74165e4e 100644 --- a/device/include/mcs51/P89LPC925.h +++ b/device/include/mcs51/P89LPC925.h @@ -1,481 +1,481 @@ -/*------------------------------------------------------------------------- - Register Declarations for NXP P89LPC924 and P89LPC925 - (Based on datasheet Rev. 03 — 15 December 2004) - - Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (February 2007) - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option); any later version - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - In other words, you are welcome to use, share and improve this program - You are forbidden to forbid anyone else to use, share and improve - what you give them. Help stamp out software-hoarding! --------------------------------------------------------------------------*/ - -#ifndef REG_P89LPC925_H -#define REG_P89LPC925_H - -#include - -SFR(ACC, 0xE0); // Accumulator - SBIT(ACC_7, 0xE0, 7); - SBIT(ACC_6, 0xE0, 6); - SBIT(ACC_5, 0xE0, 5); - SBIT(ACC_4, 0xE0, 4); - SBIT(ACC_3, 0xE0, 3); - SBIT(ACC_2, 0xE0, 2); - SBIT(ACC_1, 0xE0, 1); - SBIT(ACC_0, 0xE0, 0); - -SFR(ADCON1, 0x97); // A/D control register 1 - #define ENBI1 0x80 - #define ENADCI1 0x40 - #define TMM1 0x20 - #define EDGE1 0x10 - #define ADCI1 0x08 - #define ENADC1 0x04 - #define ADCS11 0x02 - #define ADCS10 0x01 - -SFR(ADINS, 0xA3); // A/D input select - #define ADI13 0x80 - #define ADI12 0x40 - #define ADI11 0x20 - #define ADI10 0x10 - -SFR(ADMODA, 0xC0); // A/D mode register A - #define BNDI1 0x80 - #define BURST1 0x40 - #define SCC1 0x20 - #define SCAN1 0x10 - -SFR(ADMODB, 0xA1); // A/D mode register B - #define CLK2 0x80 - #define CLK1 0x40 - #define CLK0 0x20 - #define ENDAC1 0x08 - #define BSA1 0x02 - -SFR(AD1BH, 0xC4); // A/D_1 boundary high register - -SFR(AD1BL, 0xBC); // A/D_1 boundary low register - -SFR(AD1DAT0, 0xD5); // A/D_1 data register 0 - -SFR(AD1DAT1, 0xD6); // A/D_1 data register 1 - -SFR(AD1DAT2, 0xD7); // A/D_1 data register 2 - -SFR(AD1DAT3, 0xF5); // A/D_1 data register 3 - -SFR(AUXR1, 0xA2); // Auxiliary function register - #define CLKLP 0x80 - #define EBRR 0x40 - #define ENT1 0x20 - #define ENT0 0x10 - #define SRST 0x08 - #define DPS 0x01 - -SFR(B, 0xF0); // B register - SBIT(B_7, 0xF0, 7); - SBIT(B_6, 0xF0, 6); - SBIT(B_5, 0xF0, 5); - SBIT(B_4, 0xF0, 4); - SBIT(B_3, 0xF0, 3); - SBIT(B_2, 0xF0, 2); - SBIT(B_1, 0xF0, 1); - SBIT(B_0, 0xF0, 0); - -SFR(BRGR0, 0xBE); // Baud rate generator rate LOW - -SFR(BRGR1, 0xBF); // Baud rate generator rate HIGH - -SFR(BRGCON, 0xBD); // Baud rate generator control - #define SBRGS 0x02 - #define BRGEN 0x01 - -SFR(CMP1, 0xAC); // Comparator1 control register - #define CE1 0x20 - #define CP1 0x10 - #define CN1 0x08 - #define OE1 0x04 - #define CO1 0x02 - #define CMF1 0x01 - -SFR(CMP2, 0xAD); // Comparator2 control register - #define CE2 0x20 - #define CP2 0x10 - #define CN2 0x08 - #define OE2 0x04 - #define CO2 0x02 - #define CMF2 0x01 - -SFR(DIVM, 0x95); // CPU clock divide-by-M control - -SFR(DPH, 0x83); // Data pointer HIGH - -SFR(DPL, 0x82); // Data pointer LOW - -SFR(FMADRH, 0xE7); // Program Flash address HIGH - -SFR(FMADRL, 0xE6); // Program Flash address LOW - -SFR(FMCON, 0xE4); // Program Flash control (Read) - #define BUSY 0x80 - #define HVA 0x08 - #define HVE 0x04 - #define SV 0x02 - #define OI 0x01 - -SFR(FMCON, 0xE4); // Program Flash control (Write) - #define FMCMD_7 0x80 - #define FMCMD_6 0x40 - #define FMCMD_5 0x20 - #define FMCMD_4 0x10 - #define FMCMD_3 0x08 - #define FMCMD_2 0x04 - #define FMCMD_1 0x02 - #define FMCMD_0 0x01 - -SFR(FMDATA, 0xE5); // Program Flash data - -SFR(I2ADR, 0xDB); // I2C slave address register - #define I2ADR_6 0x80 - #define I2ADR_5 0x40 - #define I2ADR_4 0x20 - #define I2ADR_3 0x10 - #define I2ADR_2 0x08 - #define I2ADR_1 0x04 - #define I2ADR_0 0x02 - #define GC 0x01 - -SFR(I2CON, 0xD8); // I2C control register - SBIT(I2EN, 0xD8, 6); - SBIT(STA, 0xD8, 5); - SBIT(STO, 0xD8, 4); - SBIT(SI, 0xD8, 3); - SBIT(AA, 0xD8, 2); - SBIT(CRSEL, 0xD8, 0); - -SFR(I2DAT, 0xDA); // I2C data register - -SFR(I2SCLH, 0xDD); // Serial clock generator/SCL duty cycle register HIGH - -SFR(I2SCLL, 0xDC); // Serial clock generator/SCL duty cycle register LOW - -SFR(I2STAT, 0xD9); // I2C status register - #define STA_4 0x80 - #define STA_3 0x40 - #define STA_2 0x20 - #define STA_1 0x10 - #define STA_0 0x08 - -SFR(IEN0, 0xA8); // Interrupt enable 0 - SBIT(EA, 0xA8, 7); - SBIT(EWDRT, 0xA8, 6); - SBIT(EBO, 0xA8, 5); - SBIT(ES, 0xA8, 4); - SBIT(ESR, 0xA8, 4); - SBIT(ET1, 0xA8, 3); - SBIT(EX1, 0xA8, 2); - SBIT(ET0, 0xA8, 1); - SBIT(EX0, 0xA8, 0); - -SFR(IEN1, 0xE8); // Interrupt enable 1 - SBIT(EAD, 0xE8, 7); - SBIT(EST, 0xE8, 6); - SBIT(EC, 0xE8, 2); - SBIT(EKBI, 0xE8, 1); - SBIT(EI2C, 0xE8, 0); - -SFR(IP0, 0xB8); // Interrupt priority 0 - SBIT(PWDRT, 0xB8, 6); - SBIT(PBO, 0xB8, 5); - SBIT(PS, 0xB8, 4); - SBIT(PSR, 0xB8, 4); - SBIT(PT1, 0xB8, 3); - SBIT(PX1, 0xB8, 2); - SBIT(PT0, 0xB8, 1); - SBIT(PX0, 0xB8, 0); - -SFR(IP0H, 0xB7); // Interrupt priority 0 HIGH - #define PWDRTH 0x40 - #define PBOH 0x20 - #define PSH 0x10 - #define PSRH 0x10 - #define PT1H 0x08 - #define PX1H 0x04 - #define PT0H 0x02 - #define PX0H 0x01 - -SFR(IP1, 0xF8); // Interrupt priority 1 - SBIT(PAD, 0xF8, 7); - SBIT(PST, 0xF8, 6); - SBIT(PC, 0xF8, 2); - SBIT(PKBI, 0xF8, 1); - SBIT(PI2C, 0xF8, 0); - -SFR(IP1H, 0xF7); // Interrupt priority 1 HIGH - #define PADH 0x80 - #define PSTH 0x40 - #define PCH 0x04 - #define PKBIH 0x02 - #define PI2CH 0x01 - -SFR(KBCON, 0x94); // Keypad control register - #define PATN_SEL 0x02 //Pattern Matching Polarity selection - #define KBIF 0x01 // Keypad Interrupt Flag - -SFR(KBMASK, 0x86); // Keypad interrupt register mask - -SFR(KBPATN, 0x93); // Keypad pattern register - -SFR(P0, 0x80); // Port 0 - SBIT(P0_7, 0x80, 7); - SBIT(P0_6, 0x80, 6); - SBIT(P0_5, 0x80, 5); - SBIT(P0_4, 0x80, 4); - SBIT(P0_3, 0x80, 3); - SBIT(P0_2, 0x80, 2); - SBIT(P0_1, 0x80, 1); - SBIT(P0_0, 0x80, 0); - //P0 alternate pin functions - SBIT(T1, 0x80, 7); - SBIT(CMP1b, 0x80, 6); //Should be CMP1 but there is SFR with that name - SBIT(CMPREF, 0x80, 5); - SBIT(CIN1A, 0x80, 4); - SBIT(CIN1B, 0x80, 3); - SBIT(CIN2A, 0x80, 2); - SBIT(CIN2B, 0x80, 1); - SBIT(CMP2b, 0x80, 0); //Should be CMP2 but there is SFR with that name - //More P0 alternate pin functions - SBIT(KB7, 0x80, 7); - SBIT(KB6, 0x80, 6); - SBIT(KB5, 0x80, 5); - SBIT(KB4, 0x80, 4); - SBIT(KB3, 0x80, 3); - SBIT(KB2, 0x80, 2); - SBIT(KB1, 0x80, 1); - SBIT(KB0, 0x80, 0); - -SFR(P1, 0x90); // Port 1 - SBIT(P1_7, 0x90, 7); - SBIT(P1_6, 0x90, 6); - SBIT(P1_5, 0x90, 5); - SBIT(P1_4, 0x90, 4); - SBIT(P1_3, 0x90, 3); - SBIT(P1_2, 0x90, 2); - SBIT(P1_1, 0x90, 1); - SBIT(P1_0, 0x90, 0); - //P1 alternate pin functions - SBIT(RST, 0x90, 5); - SBIT(INT1, 0x90, 4); - SBIT(INT0, 0x90, 3); - SBIT(SDA, 0x90, 3); - SBIT(T0, 0x90, 2); - SBIT(SCL, 0x90, 2); - SBIT(RXD, 0x90, 1); - SBIT(TXD, 0x90, 0); - -SFR(P3, 0xB0); // Port 3 - SBIT(P3_1, 0xB0, 1); - SBIT(P3_0, 0xB0, 0); - SBIT(XTAL1, 0xB0, 1); - SBIT(XTAL2, 0xB0, 0); - -SFR(P0M1, 0x84); // Port0 output mode1 - #define P0M1_7 0x80 - #define P0M1_6 0x40 - #define P0M1_5 0x20 - #define P0M1_4 0x10 - #define P0M1_3 0x08 - #define P0M1_2 0x04 - #define P0M1_1 0x02 - #define P0M1_0 0x01 - -SFR(P0M2, 0x85); // Port0 output mode2 - #define P0M2_7 0x80 - #define P0M2_6 0x40 - #define P0M2_5 0x20 - #define P0M2_4 0x10 - #define P0M2_3 0x08 - #define P0M2_2 0x04 - #define P0M2_1 0x02 - #define P0M2_0 0x01 - -SFR(P1M1, 0x91); // Port1 output mode1 - #define P1M1_7 0x80 - #define P1M1_6 0x40 - #define P1M1_4 0x10 - #define P1M1_3 0x08 - #define P1M1_2 0x04 - #define P1M1_1 0x02 - #define P1M1_0 0x01 - -SFR(P1M2, 0x92); // Port1 output mode2 - #define P1M2_7 0x80 - #define P1M2_6 0x40 - #define P1M2_4 0x10 - #define P1M2_3 0x08 - #define P1M2_2 0x04 - #define P1M2_1 0x02 - #define P1M2_0 0x01 - -SFR(P3M1, 0xB1); // Port3 output mode1 - #define P3M1_1 0x02 - #define P3M1_0 0x01 - -SFR(P3M2, 0xB2); // Port3 output mode2 - #define P3M2_1 0x02 - #define P3M2_0 0x01 - -SFR(PCON, 0x87); // Power control register - #define SMOD1 0x80 - #define SMOD0 0x40 - #define BOPD 0x20 - #define BOI 0x10 - #define GF1 0x08 - #define GF0 0x04 - #define PMOD1 0x02 - #define PMOD0 0x01 - -SFR(PCONA, 0xB5); // Power control register A - #define RTCPD 0x80 - #define VCPD 0x20 - #define ADPD 0x10 - #define I2PD 0x08 - #define SPD 0x02 - -SFR(PSW, 0xD0); // Program status word - SBIT(CY, 0xD0, 7); - SBIT(AC, 0xD0, 6); - SBIT(F0, 0xD0, 5); - SBIT(RS1, 0xD0, 4); - SBIT(RS0, 0xD0, 3); - SBIT(OV, 0xD0, 2); - SBIT(F1, 0xD0, 1); - SBIT(P, 0xD0, 0); - -SFR(PT0AD, 0xF6); // Port0 digital input disable - #define PT0AD_5 0x20 - #define PT0AD_4 0x10 - #define PT0AD_3 0x08 - #define PT0AD_2 0x04 - #define PT0AD_1 0x02 - -SFR(RSTSRC, 0xDF); // Reset source register - #define BOF 0x20 - #define POF 0x10 - #define R_BK 0x08 - #define R_WD 0x04 - #define R_SF 0x02 - #define R_EX 0x01 - -SFR(RTCCON, 0xD1); // Real-time clock control - #define RTCF 0x80 - #define RTCS1 0x40 - #define RTCS0 0x20 - #define ERTC 0x02 - #define RTCEN 0x01 - -SFR(RTCH, 0xD2); // Real-time clock register HIGH - -SFR(RTCL, 0xD3); // Real-time clock register LOW - -SFR(SADDR, 0xA9); // Serial port address register - -SFR(SADEN, 0xB9); // Serial port address enable - -SFR(SBUF, 0x99); // Serial Port data buffer register - -SFR(SCON, 0x98); // Serial port control - SBIT(FE, 0x98, 7); - SBIT(SM0, 0x98, 7); - SBIT(SM1, 0x98, 6); - SBIT(SM2, 0x98, 5); - SBIT(REN, 0x98, 4); - SBIT(TB8, 0x98, 3); - SBIT(RB8, 0x98, 2); - SBIT(TI, 0x98, 1); - SBIT(RI, 0x98, 0); - -SFR(SSTAT, 0xBA); // Serial port extended status register - #define DBMOD 0x80 - #define INTLO 0x40 - #define CIDIS 0x20 - #define DBISEL 0x10 - #define FE 0x08 - #define BR 0x04 - #define OE 0x02 - #define STINT 0x01 - -SFR(SP, 0x81); // Stack pointer - -SFR(TAMOD, 0x8F); // Timer0 and 1 auxiliary mode - #define T1M2 0x10 - #define T0M2 0x01 - -SFR(TCON, 0x88); // Timer0 and 1 control - SBIT(TF1, 0x88, 7); - SBIT(TR1, 0x88, 6); - SBIT(TF0, 0x88, 5); - SBIT(TR0, 0x88, 4); - SBIT(IE1, 0x88, 3); - SBIT(IT1, 0x88, 2); - SBIT(IE0, 0x88, 1); - SBIT(IT0, 0x88, 0); - -SFR(TH0, 0x8C); // Timer0 HIGH - -SFR(TH1, 0x8D); // Timer 1 HIGH - -SFR(TL0, 0x8A); // Timer 0 LOW - -SFR(TL1, 0x8B); // Timer 1 LOW - -SFR(TMOD, 0x89); // Timer0 and 1 mode - #define T1GATE 0x80 - #define T1C_T 0x40 - #define T1M1 0x20 - #define T1M0 0x10 - #define T0GATE 0x08 - #define T0C_T 0x04 - #define T0M1 0x02 - #define T0M0 0x01 - -SFR(TRIM, 0x96); // Internal oscillator trim register - #define RCCLK 0x80 - #define ENCLK 0x40 - #define TRIM_5 0x20 - #define TRIM_4 0x10 - #define TRIM_3 0x08 - #define TRIM_2 0x04 - #define TRIM_1 0x02 - #define TRIM_0 0x01 - -SFR(WDCON, 0xA7); // Watchdog control register - #define PRE2 0x80 //Watchdog Prescaler Tap Select bit 2 - #define PRE1 0x40 //Watchdog Prescaler Tap Select bit 1 - #define PRE0 0x20 //Watchdog Prescaler Tap Select bit 0 - #define WDRUN 0x04 //Watchdog Run Control - #define WDTOF 0x02 //Watchdog Timer Time-Out Flag - #define WDCLK 0x01 //Watchdog input clock select - -SFR(WDL, 0xC1); // Watchdog load - -SFR(WFEED1, 0xC2); // Watchdog feed 1 - -SFR(WFEED2, 0xC3); // Watchdog feed 2 - -#endif /*REG_P89LPC925_H*/ +/*------------------------------------------------------------------------- + Register Declarations for NXP P89LPC924 and P89LPC925 + (Based on datasheet Rev. 03 — 15 December 2004) + + Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (February 2007) + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option); any later version + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + In other words, you are welcome to use, share and improve this program + You are forbidden to forbid anyone else to use, share and improve + what you give them. Help stamp out software-hoarding! +-------------------------------------------------------------------------*/ + +#ifndef REG_P89LPC925_H +#define REG_P89LPC925_H + +#include + +SFR(ACC, 0xE0); // Accumulator + SBIT(ACC_7, 0xE0, 7); + SBIT(ACC_6, 0xE0, 6); + SBIT(ACC_5, 0xE0, 5); + SBIT(ACC_4, 0xE0, 4); + SBIT(ACC_3, 0xE0, 3); + SBIT(ACC_2, 0xE0, 2); + SBIT(ACC_1, 0xE0, 1); + SBIT(ACC_0, 0xE0, 0); + +SFR(ADCON1, 0x97); // A/D control register 1 + #define ENBI1 0x80 + #define ENADCI1 0x40 + #define TMM1 0x20 + #define EDGE1 0x10 + #define ADCI1 0x08 + #define ENADC1 0x04 + #define ADCS11 0x02 + #define ADCS10 0x01 + +SFR(ADINS, 0xA3); // A/D input select + #define ADI13 0x80 + #define ADI12 0x40 + #define ADI11 0x20 + #define ADI10 0x10 + +SFR(ADMODA, 0xC0); // A/D mode register A + #define BNDI1 0x80 + #define BURST1 0x40 + #define SCC1 0x20 + #define SCAN1 0x10 + +SFR(ADMODB, 0xA1); // A/D mode register B + #define CLK2 0x80 + #define CLK1 0x40 + #define CLK0 0x20 + #define ENDAC1 0x08 + #define BSA1 0x02 + +SFR(AD1BH, 0xC4); // A/D_1 boundary high register + +SFR(AD1BL, 0xBC); // A/D_1 boundary low register + +SFR(AD1DAT0, 0xD5); // A/D_1 data register 0 + +SFR(AD1DAT1, 0xD6); // A/D_1 data register 1 + +SFR(AD1DAT2, 0xD7); // A/D_1 data register 2 + +SFR(AD1DAT3, 0xF5); // A/D_1 data register 3 + +SFR(AUXR1, 0xA2); // Auxiliary function register + #define CLKLP 0x80 + #define EBRR 0x40 + #define ENT1 0x20 + #define ENT0 0x10 + #define SRST 0x08 + #define DPS 0x01 + +SFR(B, 0xF0); // B register + SBIT(B_7, 0xF0, 7); + SBIT(B_6, 0xF0, 6); + SBIT(B_5, 0xF0, 5); + SBIT(B_4, 0xF0, 4); + SBIT(B_3, 0xF0, 3); + SBIT(B_2, 0xF0, 2); + SBIT(B_1, 0xF0, 1); + SBIT(B_0, 0xF0, 0); + +SFR(BRGR0, 0xBE); // Baud rate generator rate LOW + +SFR(BRGR1, 0xBF); // Baud rate generator rate HIGH + +SFR(BRGCON, 0xBD); // Baud rate generator control + #define SBRGS 0x02 + #define BRGEN 0x01 + +SFR(CMP1, 0xAC); // Comparator1 control register + #define CE1 0x20 + #define CP1 0x10 + #define CN1 0x08 + #define OE1 0x04 + #define CO1 0x02 + #define CMF1 0x01 + +SFR(CMP2, 0xAD); // Comparator2 control register + #define CE2 0x20 + #define CP2 0x10 + #define CN2 0x08 + #define OE2 0x04 + #define CO2 0x02 + #define CMF2 0x01 + +SFR(DIVM, 0x95); // CPU clock divide-by-M control + +SFR(DPH, 0x83); // Data pointer HIGH + +SFR(DPL, 0x82); // Data pointer LOW + +SFR(FMADRH, 0xE7); // Program Flash address HIGH + +SFR(FMADRL, 0xE6); // Program Flash address LOW + +SFR(FMCON, 0xE4); // Program Flash control (Read) + #define BUSY 0x80 + #define HVA 0x08 + #define HVE 0x04 + #define SV 0x02 + #define OI 0x01 + +SFR(FMCON, 0xE4); // Program Flash control (Write) + #define FMCMD_7 0x80 + #define FMCMD_6 0x40 + #define FMCMD_5 0x20 + #define FMCMD_4 0x10 + #define FMCMD_3 0x08 + #define FMCMD_2 0x04 + #define FMCMD_1 0x02 + #define FMCMD_0 0x01 + +SFR(FMDATA, 0xE5); // Program Flash data + +SFR(I2ADR, 0xDB); // I2C slave address register + #define I2ADR_6 0x80 + #define I2ADR_5 0x40 + #define I2ADR_4 0x20 + #define I2ADR_3 0x10 + #define I2ADR_2 0x08 + #define I2ADR_1 0x04 + #define I2ADR_0 0x02 + #define GC 0x01 + +SFR(I2CON, 0xD8); // I2C control register + SBIT(I2EN, 0xD8, 6); + SBIT(STA, 0xD8, 5); + SBIT(STO, 0xD8, 4); + SBIT(SI, 0xD8, 3); + SBIT(AA, 0xD8, 2); + SBIT(CRSEL, 0xD8, 0); + +SFR(I2DAT, 0xDA); // I2C data register + +SFR(I2SCLH, 0xDD); // Serial clock generator/SCL duty cycle register HIGH + +SFR(I2SCLL, 0xDC); // Serial clock generator/SCL duty cycle register LOW + +SFR(I2STAT, 0xD9); // I2C status register + #define STA_4 0x80 + #define STA_3 0x40 + #define STA_2 0x20 + #define STA_1 0x10 + #define STA_0 0x08 + +SFR(IEN0, 0xA8); // Interrupt enable 0 + SBIT(EA, 0xA8, 7); + SBIT(EWDRT, 0xA8, 6); + SBIT(EBO, 0xA8, 5); + SBIT(ES, 0xA8, 4); + SBIT(ESR, 0xA8, 4); + SBIT(ET1, 0xA8, 3); + SBIT(EX1, 0xA8, 2); + SBIT(ET0, 0xA8, 1); + SBIT(EX0, 0xA8, 0); + +SFR(IEN1, 0xE8); // Interrupt enable 1 + SBIT(EAD, 0xE8, 7); + SBIT(EST, 0xE8, 6); + SBIT(EC, 0xE8, 2); + SBIT(EKBI, 0xE8, 1); + SBIT(EI2C, 0xE8, 0); + +SFR(IP0, 0xB8); // Interrupt priority 0 + SBIT(PWDRT, 0xB8, 6); + SBIT(PBO, 0xB8, 5); + SBIT(PS, 0xB8, 4); + SBIT(PSR, 0xB8, 4); + SBIT(PT1, 0xB8, 3); + SBIT(PX1, 0xB8, 2); + SBIT(PT0, 0xB8, 1); + SBIT(PX0, 0xB8, 0); + +SFR(IP0H, 0xB7); // Interrupt priority 0 HIGH + #define PWDRTH 0x40 + #define PBOH 0x20 + #define PSH 0x10 + #define PSRH 0x10 + #define PT1H 0x08 + #define PX1H 0x04 + #define PT0H 0x02 + #define PX0H 0x01 + +SFR(IP1, 0xF8); // Interrupt priority 1 + SBIT(PAD, 0xF8, 7); + SBIT(PST, 0xF8, 6); + SBIT(PC, 0xF8, 2); + SBIT(PKBI, 0xF8, 1); + SBIT(PI2C, 0xF8, 0); + +SFR(IP1H, 0xF7); // Interrupt priority 1 HIGH + #define PADH 0x80 + #define PSTH 0x40 + #define PCH 0x04 + #define PKBIH 0x02 + #define PI2CH 0x01 + +SFR(KBCON, 0x94); // Keypad control register + #define PATN_SEL 0x02 //Pattern Matching Polarity selection + #define KBIF 0x01 // Keypad Interrupt Flag + +SFR(KBMASK, 0x86); // Keypad interrupt register mask + +SFR(KBPATN, 0x93); // Keypad pattern register + +SFR(P0, 0x80); // Port 0 + SBIT(P0_7, 0x80, 7); + SBIT(P0_6, 0x80, 6); + SBIT(P0_5, 0x80, 5); + SBIT(P0_4, 0x80, 4); + SBIT(P0_3, 0x80, 3); + SBIT(P0_2, 0x80, 2); + SBIT(P0_1, 0x80, 1); + SBIT(P0_0, 0x80, 0); + //P0 alternate pin functions + SBIT(T1, 0x80, 7); + SBIT(CMP1b, 0x80, 6); //Should be CMP1 but there is SFR with that name + SBIT(CMPREF, 0x80, 5); + SBIT(CIN1A, 0x80, 4); + SBIT(CIN1B, 0x80, 3); + SBIT(CIN2A, 0x80, 2); + SBIT(CIN2B, 0x80, 1); + SBIT(CMP2b, 0x80, 0); //Should be CMP2 but there is SFR with that name + //More P0 alternate pin functions + SBIT(KB7, 0x80, 7); + SBIT(KB6, 0x80, 6); + SBIT(KB5, 0x80, 5); + SBIT(KB4, 0x80, 4); + SBIT(KB3, 0x80, 3); + SBIT(KB2, 0x80, 2); + SBIT(KB1, 0x80, 1); + SBIT(KB0, 0x80, 0); + +SFR(P1, 0x90); // Port 1 + SBIT(P1_7, 0x90, 7); + SBIT(P1_6, 0x90, 6); + SBIT(P1_5, 0x90, 5); + SBIT(P1_4, 0x90, 4); + SBIT(P1_3, 0x90, 3); + SBIT(P1_2, 0x90, 2); + SBIT(P1_1, 0x90, 1); + SBIT(P1_0, 0x90, 0); + //P1 alternate pin functions + SBIT(RST, 0x90, 5); + SBIT(INT1, 0x90, 4); + SBIT(INT0, 0x90, 3); + SBIT(SDA, 0x90, 3); + SBIT(T0, 0x90, 2); + SBIT(SCL, 0x90, 2); + SBIT(RXD, 0x90, 1); + SBIT(TXD, 0x90, 0); + +SFR(P3, 0xB0); // Port 3 + SBIT(P3_1, 0xB0, 1); + SBIT(P3_0, 0xB0, 0); + SBIT(XTAL1, 0xB0, 1); + SBIT(XTAL2, 0xB0, 0); + +SFR(P0M1, 0x84); // Port0 output mode1 + #define P0M1_7 0x80 + #define P0M1_6 0x40 + #define P0M1_5 0x20 + #define P0M1_4 0x10 + #define P0M1_3 0x08 + #define P0M1_2 0x04 + #define P0M1_1 0x02 + #define P0M1_0 0x01 + +SFR(P0M2, 0x85); // Port0 output mode2 + #define P0M2_7 0x80 + #define P0M2_6 0x40 + #define P0M2_5 0x20 + #define P0M2_4 0x10 + #define P0M2_3 0x08 + #define P0M2_2 0x04 + #define P0M2_1 0x02 + #define P0M2_0 0x01 + +SFR(P1M1, 0x91); // Port1 output mode1 + #define P1M1_7 0x80 + #define P1M1_6 0x40 + #define P1M1_4 0x10 + #define P1M1_3 0x08 + #define P1M1_2 0x04 + #define P1M1_1 0x02 + #define P1M1_0 0x01 + +SFR(P1M2, 0x92); // Port1 output mode2 + #define P1M2_7 0x80 + #define P1M2_6 0x40 + #define P1M2_4 0x10 + #define P1M2_3 0x08 + #define P1M2_2 0x04 + #define P1M2_1 0x02 + #define P1M2_0 0x01 + +SFR(P3M1, 0xB1); // Port3 output mode1 + #define P3M1_1 0x02 + #define P3M1_0 0x01 + +SFR(P3M2, 0xB2); // Port3 output mode2 + #define P3M2_1 0x02 + #define P3M2_0 0x01 + +SFR(PCON, 0x87); // Power control register + #define SMOD1 0x80 + #define SMOD0 0x40 + #define BOPD 0x20 + #define BOI 0x10 + #define GF1 0x08 + #define GF0 0x04 + #define PMOD1 0x02 + #define PMOD0 0x01 + +SFR(PCONA, 0xB5); // Power control register A + #define RTCPD 0x80 + #define VCPD 0x20 + #define ADPD 0x10 + #define I2PD 0x08 + #define SPD 0x02 + +SFR(PSW, 0xD0); // Program status word + SBIT(CY, 0xD0, 7); + SBIT(AC, 0xD0, 6); + SBIT(F0, 0xD0, 5); + SBIT(RS1, 0xD0, 4); + SBIT(RS0, 0xD0, 3); + SBIT(OV, 0xD0, 2); + SBIT(F1, 0xD0, 1); + SBIT(P, 0xD0, 0); + +SFR(PT0AD, 0xF6); // Port0 digital input disable + #define PT0AD_5 0x20 + #define PT0AD_4 0x10 + #define PT0AD_3 0x08 + #define PT0AD_2 0x04 + #define PT0AD_1 0x02 + +SFR(RSTSRC, 0xDF); // Reset source register + #define BOF 0x20 + #define POF 0x10 + #define R_BK 0x08 + #define R_WD 0x04 + #define R_SF 0x02 + #define R_EX 0x01 + +SFR(RTCCON, 0xD1); // Real-time clock control + #define RTCF 0x80 + #define RTCS1 0x40 + #define RTCS0 0x20 + #define ERTC 0x02 + #define RTCEN 0x01 + +SFR(RTCH, 0xD2); // Real-time clock register HIGH + +SFR(RTCL, 0xD3); // Real-time clock register LOW + +SFR(SADDR, 0xA9); // Serial port address register + +SFR(SADEN, 0xB9); // Serial port address enable + +SFR(SBUF, 0x99); // Serial Port data buffer register + +SFR(SCON, 0x98); // Serial port control + SBIT(FE, 0x98, 7); + SBIT(SM0, 0x98, 7); + SBIT(SM1, 0x98, 6); + SBIT(SM2, 0x98, 5); + SBIT(REN, 0x98, 4); + SBIT(TB8, 0x98, 3); + SBIT(RB8, 0x98, 2); + SBIT(TI, 0x98, 1); + SBIT(RI, 0x98, 0); + +SFR(SSTAT, 0xBA); // Serial port extended status register + #define DBMOD 0x80 + #define INTLO 0x40 + #define CIDIS 0x20 + #define DBISEL 0x10 + #define FE 0x08 + #define BR 0x04 + #define OE 0x02 + #define STINT 0x01 + +SFR(SP, 0x81); // Stack pointer + +SFR(TAMOD, 0x8F); // Timer0 and 1 auxiliary mode + #define T1M2 0x10 + #define T0M2 0x01 + +SFR(TCON, 0x88); // Timer0 and 1 control + SBIT(TF1, 0x88, 7); + SBIT(TR1, 0x88, 6); + SBIT(TF0, 0x88, 5); + SBIT(TR0, 0x88, 4); + SBIT(IE1, 0x88, 3); + SBIT(IT1, 0x88, 2); + SBIT(IE0, 0x88, 1); + SBIT(IT0, 0x88, 0); + +SFR(TH0, 0x8C); // Timer0 HIGH + +SFR(TH1, 0x8D); // Timer 1 HIGH + +SFR(TL0, 0x8A); // Timer 0 LOW + +SFR(TL1, 0x8B); // Timer 1 LOW + +SFR(TMOD, 0x89); // Timer0 and 1 mode + #define T1GATE 0x80 + #define T1C_T 0x40 + #define T1M1 0x20 + #define T1M0 0x10 + #define T0GATE 0x08 + #define T0C_T 0x04 + #define T0M1 0x02 + #define T0M0 0x01 + +SFR(TRIM, 0x96); // Internal oscillator trim register + #define RCCLK 0x80 + #define ENCLK 0x40 + #define TRIM_5 0x20 + #define TRIM_4 0x10 + #define TRIM_3 0x08 + #define TRIM_2 0x04 + #define TRIM_1 0x02 + #define TRIM_0 0x01 + +SFR(WDCON, 0xA7); // Watchdog control register + #define PRE2 0x80 //Watchdog Prescaler Tap Select bit 2 + #define PRE1 0x40 //Watchdog Prescaler Tap Select bit 1 + #define PRE0 0x20 //Watchdog Prescaler Tap Select bit 0 + #define WDRUN 0x04 //Watchdog Run Control + #define WDTOF 0x02 //Watchdog Timer Time-Out Flag + #define WDCLK 0x01 //Watchdog input clock select + +SFR(WDL, 0xC1); // Watchdog load + +SFR(WFEED1, 0xC2); // Watchdog feed 1 + +SFR(WFEED2, 0xC3); // Watchdog feed 2 + +#endif /*REG_P89LPC925_H*/ diff --git a/device/include/mcs51/P89LPC932.h b/device/include/mcs51/P89LPC932.h index 1753f00e..36da6f13 100644 --- a/device/include/mcs51/P89LPC932.h +++ b/device/include/mcs51/P89LPC932.h @@ -1,351 +1,351 @@ -/*-------------------------------------------------------------------------- -P89LPC932.H -(English) -This header allows to use the microcontroler Philips P89LPC932 -with the compiler SDCC. - -Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - -(Spanish-Español) -Archivo encabezador para el ucontrolador Philips P89LPC932. -Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com -Uso libre ---------------------------------------------------------------------------*/ -#ifndef __REG932_H__ -#define __REG932_H__ - -/* BYTE Registers */ -__sfr __at (0x80) P0 ; -__sfr __at (0x90) P1 ; -__sfr __at (0xA0) P2 ; -__sfr __at (0xB0) P3 ; -__sfr __at (0xD0) PSW ; -__sfr __at (0xE0) ACC ; -__sfr __at (0xF0) B ; -__sfr __at (0x81) SP ; -__sfr __at (0x82) DPL ; -__sfr __at (0x83) DPH ; -__sfr __at (0x87) PCON ; -__sfr __at (0x88) TCON ; -__sfr __at (0x89) TMOD ; -__sfr __at (0x8A) TL0 ; -__sfr __at (0x8B) TL1 ; -__sfr __at (0x8C) TH0 ; -__sfr __at (0x8D) TH1 ; -__sfr __at (0xA8) IEN0 ; -__sfr __at (0xB8) IP0 ; -__sfr __at (0x98) SCON ; -__sfr __at (0x99) SBUF ; - - -__sfr __at (0xA2) AUXR1 ; -__sfr __at (0xA9) SADDR ; -__sfr __at (0xB9) SADEN ; -__sfr __at (0xCC) TL2 ; -__sfr __at (0xCD) TH2 ; -__sfr __at (0xBE) BRGR0 ; -__sfr __at (0xBF) BRGR1 ; -__sfr __at (0xBD) BRGCON ; -__sfr __at (0xEA) CCCRA ; -__sfr __at (0xEB) CCCRB ; -__sfr __at (0xEC) CCCRC ; -__sfr __at (0xED) CCCRD ; -__sfr __at (0xAC) CMP1 ; -__sfr __at (0xAD) CMP2 ; -__sfr __at (0xF1) DEECON ; -__sfr __at (0xF2) DEEDAT ; -__sfr __at (0xF3) DEEADR ; -__sfr __at (0x95) DIVM ; -__sfr __at (0xDB) I2ADR ; -__sfr __at (0xD8) I2CON ; -__sfr __at (0xDA) I2DAT ; -__sfr __at (0xDD) I2SCLH ; -__sfr __at (0xDC) I2SCLL ; -__sfr __at (0xD9) I2STAT ; -__sfr __at (0xAB) ICRAH ; -__sfr __at (0xAA) ICRAL ; -__sfr __at (0xAF) ICRBH ; -__sfr __at (0xAE) ICRBL ; -__sfr __at (0xE8) IEN1 ; -__sfr __at (0xF8) IP1 ; -__sfr __at (0xF7) IP1H ; -__sfr __at (0x94) KBCON ; -__sfr __at (0x86) KBMASK ; -__sfr __at (0x93) KBPATN ; -__sfr __at (0xEF) OCRAH ; -__sfr __at (0xEE) OCRAL ; -__sfr __at (0xFB) OCRBH ; -__sfr __at (0xFA) OCRBL ; -__sfr __at (0xFD) OCRCH ; -__sfr __at (0xFC) OCRCL ; -__sfr __at (0xFF) OCRDH ; -__sfr __at (0xFE) OCRDL ; -__sfr __at (0x84) P0M1 ; -__sfr __at (0x85) P0M2 ; -__sfr __at (0x91) P1M1 ; -__sfr __at (0x92) P1M2 ; -__sfr __at (0xA4) P2M1 ; -__sfr __at (0xA5) P2M2 ; -__sfr __at (0xB1) P3M1 ; -__sfr __at (0xB2) P3M2 ; -__sfr __at (0xB5) PCONA ; -__sfr __at (0xF6) PT0AD ; -__sfr __at (0xDF) RSTSRC ; -__sfr __at (0xD1) RTCCON ; -__sfr __at (0xD2) RTCH ; -__sfr __at (0xD3) RTCL ; -__sfr __at (0xBA) SSTAT ; -__sfr __at (0xE2) SPCTL ; -__sfr __at (0xE1) SPSTAT ; -__sfr __at (0xE3) SPDAT ; -__sfr __at (0x8F) TAMOD ; -__sfr __at (0xC8) TCR20 ; -__sfr __at (0xF9) TCR21 ; -__sfr __at (0xC9) TICR2 ; -__sfr __at (0xE9) TIFR2 ; -__sfr __at (0xDE) TISE2 ; -__sfr __at (0xCF) TOR2H ; -__sfr __at (0xCE) TOR2L ; -__sfr __at (0xCB) TPCR2H ; -__sfr __at (0xCA) TPCR2L ; -__sfr __at (0x96) TRIM ; -__sfr __at (0xA7) WDCON ; -__sfr __at (0xC1) WDL ; -__sfr __at (0xC2) WFEED1 ; -__sfr __at (0xC3) WFEED2 ; -__sfr __at (0xB7) IP0H ; - -/* BIT Registers */ -/* PSW */ -__sbit __at (0xD7) PSW_7; -__sbit __at (0xD6) PSW_6; -__sbit __at (0xD5) PSW_5; -__sbit __at (0xD4) PSW_4; -__sbit __at (0xD3) PSW_3; -__sbit __at (0xD2) PSW_2; -__sbit __at (0xD1) PSW_1; -__sbit __at (0xD0) PSW_0; - -#define CY PSW_7 -#define AC PSW_6 -#define F0 PSW_5 -#define RS1 PSW_4 -#define RS0 PSW_3 -#define OV PSW_2 -#define F1 PSW_1 -#define P PSW_0 - -/* TCON */ -__sbit __at (0x8F) TCON_7; -__sbit __at (0x8E) TCON_6; -__sbit __at (0x8D) TCON_5; -__sbit __at (0x8C) TCON_4; -__sbit __at (0x8B) TCON_3; -__sbit __at (0x8A) TCON_2; -__sbit __at (0x89) TCON_1; -__sbit __at (0x88) TCON_0; - -#define TF1 TCON_7 -#define TR1 TCON_6 -#define TF0 TCON_5 -#define TR0 TCON_4 -#define IE1 TCON_3 -#define IT1 TCON_2 -#define IE0 TCON_1 -#define IT0 TCON_0 - -/* IEN0 */ -__sbit __at (0xAF) IEN0_7; -__sbit __at (0xAE) IEN0_6; -__sbit __at (0xAD) IEN0_5; -__sbit __at (0xAC) IEN0_4; // alternatively "ESR" -__sbit __at (0xAC) IEN0_4; -__sbit __at (0xAB) IEN0_3; -__sbit __at (0xAA) IEN0_2; -__sbit __at (0xA9) IEN0_1; -__sbit __at (0xA8) IEN0_0; - -#define EA IEN0_7 -#define EWDRT IEN0_6 -#define EBO IEN0_5 -#define ES IEN0_4 // alternatively "ESR" -#define ESR IEN0_4 -#define ET1 IEN0_3 -#define EX1 IEN0_2 -#define ET0 IEN0_1 -#define EX0 IEN0_0 - -/* IEN1 */ -__sbit __at (0xEF) IEN1_7; -__sbit __at (0xEE) IEN1_6; -__sbit __at (0xEC) IEN1_4; -__sbit __at (0xEB) IEN1_3; -__sbit __at (0xEA) IEN1_2; -__sbit __at (0xE9) IEN1_1; -__sbit __at (0xE8) IEN1_0; - -#define EIEE IEN1_7 -#define EST IEN1_6 -#define ECCU IEN1_4 -#define ESPI IEN1_3 -#define EC IEN1_2 -#define EKBI IEN1_1 -#define EI2C IEN1_0 - -/* IP0 */ -__sbit __at (0xBE) IP0_6; -__sbit __at (0xBD) IP0_5; -__sbit __at (0xBC) IP0_4; // alternatively "PSR" -__sbit __at (0xBC) IP0_4; -__sbit __at (0xBB) IP0_3; -__sbit __at (0xBA) IP0_2; -__sbit __at (0xB9) IP0_1; -__sbit __at (0xB8) IP0_0; - -#define PWDRT IP0_6 -#define PB0 IP0_5 -#define PS IP0_4 // alternatively "PSR" -#define PSR IP0_4 -#define PT1 IP0_3 -#define PX1 IP0_2 -#define PT0 IP0_1 -#define PX0 IP0_0 - -/* SCON */ -__sbit __at (0x9F) SCON_7; // alternatively "FE" -__sbit __at (0x9E) SCON_6; -__sbit __at (0x9D) SCON_5; -__sbit __at (0x9C) SCON_4; -__sbit __at (0x9B) SCON_3; -__sbit __at (0x9A) SCON_2; -__sbit __at (0x99) SCON_1; -__sbit __at (0x98) SCON_0; - -#define SM0 SCON_7 // alternatively "FE" -#define FE SCON_7 -#define SM1 SCON_6 -#define SM2 SCON_5 -#define REN SCON_4 -#define TB8 SCON_3 -#define RB8 SCON_2 -#define TI SCON_1 -#define RI SCON_0 - -/* I2CON */ -__sbit __at (0xDE) I2CON_6; -__sbit __at (0xDD) I2CON_5; -__sbit __at (0xDC) I2CON_4; -__sbit __at (0xDB) I2CON_3; -__sbit __at (0xDA) I2CON_2; -__sbit __at (0xD8) I2CON_0; - -#define I2EN I2CON_6; -#define STA I2CON_5; -#define STO I2CON_4; -#define SI I2CON_3; -#define AA I2CON_2; -#define CRSEL I2CON_0; - -/* P0 */ -__sbit __at (0x87) P0_7; -__sbit __at (0x86) P0_6; // alternatively "CMP1" -__sbit __at (0x85) P0_5; -__sbit __at (0x84) P0_4; -__sbit __at (0x83) P0_3; -__sbit __at (0x82) P0_2; -__sbit __at (0x81) P0_1; -__sbit __at (0x80) P0_0; // alternatively "CMP2" - -#define KB7 P0_7 // alternatively "T1" -#define T1 P0_7 -#define KB6 P0_6 // alternatively "CMP1" -#define CMP1 P0_6 -#define KB5 P0_5 -#define KB4 P0_4 -#define KB3 P0_3 -#define KB2 P0_2 -#define KB1 P0_1 -#define KB0 P0_0 // alternatively "CMP2" -#define CMP2 P0_0 - -/* P1 */ -__sbit __at (0x97) P1_7; -__sbit __at (0x96) P1_6; -__sbit __at (0x95) P1_5; -__sbit __at (0x94) P1_4; -__sbit __at (0x93) P1_3; -__sbit __at (0x92) P1_2; -__sbit __at (0x91) P1_1; -__sbit __at (0x90) P1_0; - -#define OCC P1_7 -#define OCB P1_6 -#define RST P1_5 -#define INT1 P1_4 -#define INT0 P1_3 // alternatively "SDA" -#define SDA P1_3 -#define T0 P1_2 // alternatively "SCL" -#define SCL P1_2 -#define RxD P1_1 -#define TxD P1_0 - -/* P2 */ -__sbit __at (0xA7) P2_7; -__sbit __at (0xA6) P2_6; -__sbit __at (0xA5) P2_5; -__sbit __at (0xA4) P2_4; -__sbit __at (0xA3) P2_3; -__sbit __at (0xA2) P2_2; -__sbit __at (0xA1) P2_1; -__sbit __at (0xA0) P2_0; - -#define ICA P2_7 -#define OCA P2_6 -#define SPICLK P2_5 -#define SS P2_4 -#define MISO P2_3 -#define MOSI P2_2 -#define OCD P2_1 -#define ICB P2_0 - -/* P3 */ -__sbit __at (0xB1) P3_1; -__sbit __at (0xB0) P3_0; - -#define XTAL1 P3_1 -#define XTAL2 P3_0 - -/* TCR20 */ -__sbit __at (0xCF) TCR20_7; -__sbit __at (0xCE) TCR20_6; -__sbit __at (0xCD) TCR20_5; -__sbit __at (0xCC) TCR20_4; -__sbit __at (0xCB) TCR20_3; -__sbit __at (0xCA) TCR20_2; -__sbit __at (0xC9) TCR20_1; -__sbit __at (0xC8) TCR20_0; - -#define PLLEN TCR20_7 -#define HLTRN TCR20_6 -#define HLTEN TCR20_5 -#define ALTCD TCR20_4 -#define ALTAB TCR20_3 -#define TDIR2 TCR20_2 -#define TMOD21 TCR20_1 -#define TMOD20 TCR20_0 - -#endif +/*-------------------------------------------------------------------------- +P89LPC932.H +(English) +This header allows to use the microcontroler Philips P89LPC932 +with the compiler SDCC. + +Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +(Spanish-Español) +Archivo encabezador para el ucontrolador Philips P89LPC932. +Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com +Uso libre +--------------------------------------------------------------------------*/ +#ifndef __REG932_H__ +#define __REG932_H__ + +/* BYTE Registers */ +__sfr __at (0x80) P0 ; +__sfr __at (0x90) P1 ; +__sfr __at (0xA0) P2 ; +__sfr __at (0xB0) P3 ; +__sfr __at (0xD0) PSW ; +__sfr __at (0xE0) ACC ; +__sfr __at (0xF0) B ; +__sfr __at (0x81) SP ; +__sfr __at (0x82) DPL ; +__sfr __at (0x83) DPH ; +__sfr __at (0x87) PCON ; +__sfr __at (0x88) TCON ; +__sfr __at (0x89) TMOD ; +__sfr __at (0x8A) TL0 ; +__sfr __at (0x8B) TL1 ; +__sfr __at (0x8C) TH0 ; +__sfr __at (0x8D) TH1 ; +__sfr __at (0xA8) IEN0 ; +__sfr __at (0xB8) IP0 ; +__sfr __at (0x98) SCON ; +__sfr __at (0x99) SBUF ; + + +__sfr __at (0xA2) AUXR1 ; +__sfr __at (0xA9) SADDR ; +__sfr __at (0xB9) SADEN ; +__sfr __at (0xCC) TL2 ; +__sfr __at (0xCD) TH2 ; +__sfr __at (0xBE) BRGR0 ; +__sfr __at (0xBF) BRGR1 ; +__sfr __at (0xBD) BRGCON ; +__sfr __at (0xEA) CCCRA ; +__sfr __at (0xEB) CCCRB ; +__sfr __at (0xEC) CCCRC ; +__sfr __at (0xED) CCCRD ; +__sfr __at (0xAC) CMP1 ; +__sfr __at (0xAD) CMP2 ; +__sfr __at (0xF1) DEECON ; +__sfr __at (0xF2) DEEDAT ; +__sfr __at (0xF3) DEEADR ; +__sfr __at (0x95) DIVM ; +__sfr __at (0xDB) I2ADR ; +__sfr __at (0xD8) I2CON ; +__sfr __at (0xDA) I2DAT ; +__sfr __at (0xDD) I2SCLH ; +__sfr __at (0xDC) I2SCLL ; +__sfr __at (0xD9) I2STAT ; +__sfr __at (0xAB) ICRAH ; +__sfr __at (0xAA) ICRAL ; +__sfr __at (0xAF) ICRBH ; +__sfr __at (0xAE) ICRBL ; +__sfr __at (0xE8) IEN1 ; +__sfr __at (0xF8) IP1 ; +__sfr __at (0xF7) IP1H ; +__sfr __at (0x94) KBCON ; +__sfr __at (0x86) KBMASK ; +__sfr __at (0x93) KBPATN ; +__sfr __at (0xEF) OCRAH ; +__sfr __at (0xEE) OCRAL ; +__sfr __at (0xFB) OCRBH ; +__sfr __at (0xFA) OCRBL ; +__sfr __at (0xFD) OCRCH ; +__sfr __at (0xFC) OCRCL ; +__sfr __at (0xFF) OCRDH ; +__sfr __at (0xFE) OCRDL ; +__sfr __at (0x84) P0M1 ; +__sfr __at (0x85) P0M2 ; +__sfr __at (0x91) P1M1 ; +__sfr __at (0x92) P1M2 ; +__sfr __at (0xA4) P2M1 ; +__sfr __at (0xA5) P2M2 ; +__sfr __at (0xB1) P3M1 ; +__sfr __at (0xB2) P3M2 ; +__sfr __at (0xB5) PCONA ; +__sfr __at (0xF6) PT0AD ; +__sfr __at (0xDF) RSTSRC ; +__sfr __at (0xD1) RTCCON ; +__sfr __at (0xD2) RTCH ; +__sfr __at (0xD3) RTCL ; +__sfr __at (0xBA) SSTAT ; +__sfr __at (0xE2) SPCTL ; +__sfr __at (0xE1) SPSTAT ; +__sfr __at (0xE3) SPDAT ; +__sfr __at (0x8F) TAMOD ; +__sfr __at (0xC8) TCR20 ; +__sfr __at (0xF9) TCR21 ; +__sfr __at (0xC9) TICR2 ; +__sfr __at (0xE9) TIFR2 ; +__sfr __at (0xDE) TISE2 ; +__sfr __at (0xCF) TOR2H ; +__sfr __at (0xCE) TOR2L ; +__sfr __at (0xCB) TPCR2H ; +__sfr __at (0xCA) TPCR2L ; +__sfr __at (0x96) TRIM ; +__sfr __at (0xA7) WDCON ; +__sfr __at (0xC1) WDL ; +__sfr __at (0xC2) WFEED1 ; +__sfr __at (0xC3) WFEED2 ; +__sfr __at (0xB7) IP0H ; + +/* BIT Registers */ +/* PSW */ +__sbit __at (0xD7) PSW_7; +__sbit __at (0xD6) PSW_6; +__sbit __at (0xD5) PSW_5; +__sbit __at (0xD4) PSW_4; +__sbit __at (0xD3) PSW_3; +__sbit __at (0xD2) PSW_2; +__sbit __at (0xD1) PSW_1; +__sbit __at (0xD0) PSW_0; + +#define CY PSW_7 +#define AC PSW_6 +#define F0 PSW_5 +#define RS1 PSW_4 +#define RS0 PSW_3 +#define OV PSW_2 +#define F1 PSW_1 +#define P PSW_0 + +/* TCON */ +__sbit __at (0x8F) TCON_7; +__sbit __at (0x8E) TCON_6; +__sbit __at (0x8D) TCON_5; +__sbit __at (0x8C) TCON_4; +__sbit __at (0x8B) TCON_3; +__sbit __at (0x8A) TCON_2; +__sbit __at (0x89) TCON_1; +__sbit __at (0x88) TCON_0; + +#define TF1 TCON_7 +#define TR1 TCON_6 +#define TF0 TCON_5 +#define TR0 TCON_4 +#define IE1 TCON_3 +#define IT1 TCON_2 +#define IE0 TCON_1 +#define IT0 TCON_0 + +/* IEN0 */ +__sbit __at (0xAF) IEN0_7; +__sbit __at (0xAE) IEN0_6; +__sbit __at (0xAD) IEN0_5; +__sbit __at (0xAC) IEN0_4; // alternatively "ESR" +__sbit __at (0xAC) IEN0_4; +__sbit __at (0xAB) IEN0_3; +__sbit __at (0xAA) IEN0_2; +__sbit __at (0xA9) IEN0_1; +__sbit __at (0xA8) IEN0_0; + +#define EA IEN0_7 +#define EWDRT IEN0_6 +#define EBO IEN0_5 +#define ES IEN0_4 // alternatively "ESR" +#define ESR IEN0_4 +#define ET1 IEN0_3 +#define EX1 IEN0_2 +#define ET0 IEN0_1 +#define EX0 IEN0_0 + +/* IEN1 */ +__sbit __at (0xEF) IEN1_7; +__sbit __at (0xEE) IEN1_6; +__sbit __at (0xEC) IEN1_4; +__sbit __at (0xEB) IEN1_3; +__sbit __at (0xEA) IEN1_2; +__sbit __at (0xE9) IEN1_1; +__sbit __at (0xE8) IEN1_0; + +#define EIEE IEN1_7 +#define EST IEN1_6 +#define ECCU IEN1_4 +#define ESPI IEN1_3 +#define EC IEN1_2 +#define EKBI IEN1_1 +#define EI2C IEN1_0 + +/* IP0 */ +__sbit __at (0xBE) IP0_6; +__sbit __at (0xBD) IP0_5; +__sbit __at (0xBC) IP0_4; // alternatively "PSR" +__sbit __at (0xBC) IP0_4; +__sbit __at (0xBB) IP0_3; +__sbit __at (0xBA) IP0_2; +__sbit __at (0xB9) IP0_1; +__sbit __at (0xB8) IP0_0; + +#define PWDRT IP0_6 +#define PB0 IP0_5 +#define PS IP0_4 // alternatively "PSR" +#define PSR IP0_4 +#define PT1 IP0_3 +#define PX1 IP0_2 +#define PT0 IP0_1 +#define PX0 IP0_0 + +/* SCON */ +__sbit __at (0x9F) SCON_7; // alternatively "FE" +__sbit __at (0x9E) SCON_6; +__sbit __at (0x9D) SCON_5; +__sbit __at (0x9C) SCON_4; +__sbit __at (0x9B) SCON_3; +__sbit __at (0x9A) SCON_2; +__sbit __at (0x99) SCON_1; +__sbit __at (0x98) SCON_0; + +#define SM0 SCON_7 // alternatively "FE" +#define FE SCON_7 +#define SM1 SCON_6 +#define SM2 SCON_5 +#define REN SCON_4 +#define TB8 SCON_3 +#define RB8 SCON_2 +#define TI SCON_1 +#define RI SCON_0 + +/* I2CON */ +__sbit __at (0xDE) I2CON_6; +__sbit __at (0xDD) I2CON_5; +__sbit __at (0xDC) I2CON_4; +__sbit __at (0xDB) I2CON_3; +__sbit __at (0xDA) I2CON_2; +__sbit __at (0xD8) I2CON_0; + +#define I2EN I2CON_6; +#define STA I2CON_5; +#define STO I2CON_4; +#define SI I2CON_3; +#define AA I2CON_2; +#define CRSEL I2CON_0; + +/* P0 */ +__sbit __at (0x87) P0_7; +__sbit __at (0x86) P0_6; // alternatively "CMP1" +__sbit __at (0x85) P0_5; +__sbit __at (0x84) P0_4; +__sbit __at (0x83) P0_3; +__sbit __at (0x82) P0_2; +__sbit __at (0x81) P0_1; +__sbit __at (0x80) P0_0; // alternatively "CMP2" + +#define KB7 P0_7 // alternatively "T1" +#define T1 P0_7 +#define KB6 P0_6 // alternatively "CMP1" +#define CMP1 P0_6 +#define KB5 P0_5 +#define KB4 P0_4 +#define KB3 P0_3 +#define KB2 P0_2 +#define KB1 P0_1 +#define KB0 P0_0 // alternatively "CMP2" +#define CMP2 P0_0 + +/* P1 */ +__sbit __at (0x97) P1_7; +__sbit __at (0x96) P1_6; +__sbit __at (0x95) P1_5; +__sbit __at (0x94) P1_4; +__sbit __at (0x93) P1_3; +__sbit __at (0x92) P1_2; +__sbit __at (0x91) P1_1; +__sbit __at (0x90) P1_0; + +#define OCC P1_7 +#define OCB P1_6 +#define RST P1_5 +#define INT1 P1_4 +#define INT0 P1_3 // alternatively "SDA" +#define SDA P1_3 +#define T0 P1_2 // alternatively "SCL" +#define SCL P1_2 +#define RxD P1_1 +#define TxD P1_0 + +/* P2 */ +__sbit __at (0xA7) P2_7; +__sbit __at (0xA6) P2_6; +__sbit __at (0xA5) P2_5; +__sbit __at (0xA4) P2_4; +__sbit __at (0xA3) P2_3; +__sbit __at (0xA2) P2_2; +__sbit __at (0xA1) P2_1; +__sbit __at (0xA0) P2_0; + +#define ICA P2_7 +#define OCA P2_6 +#define SPICLK P2_5 +#define SS P2_4 +#define MISO P2_3 +#define MOSI P2_2 +#define OCD P2_1 +#define ICB P2_0 + +/* P3 */ +__sbit __at (0xB1) P3_1; +__sbit __at (0xB0) P3_0; + +#define XTAL1 P3_1 +#define XTAL2 P3_0 + +/* TCR20 */ +__sbit __at (0xCF) TCR20_7; +__sbit __at (0xCE) TCR20_6; +__sbit __at (0xCD) TCR20_5; +__sbit __at (0xCC) TCR20_4; +__sbit __at (0xCB) TCR20_3; +__sbit __at (0xCA) TCR20_2; +__sbit __at (0xC9) TCR20_1; +__sbit __at (0xC8) TCR20_0; + +#define PLLEN TCR20_7 +#define HLTRN TCR20_6 +#define HLTEN TCR20_5 +#define ALTCD TCR20_4 +#define ALTAB TCR20_3 +#define TDIR2 TCR20_2 +#define TMOD21 TCR20_1 +#define TMOD20 TCR20_0 + +#endif diff --git a/device/include/mcs51/P89c51RD2.h b/device/include/mcs51/P89c51RD2.h index c6346236..a5b5268c 100644 --- a/device/include/mcs51/P89c51RD2.h +++ b/device/include/mcs51/P89c51RD2.h @@ -1,256 +1,256 @@ -/*-------------------------------------------------------------------------- -P89c51RD2.H -(English) -This header allows to use the microcontroler Philips P89c51RD2 -with the compiler SDCC. - -Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - -(Spanish-Español) -Archivo encabezador para el ucontrolador Philips P89c51RD2. -Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com -Uso libre ---------------------------------------------------------------------------*/ - -#ifndef __P89c51RD2_H__ -#define __P89c51RD2_H__ - -/* BYTE Registers */ -__sfr __at (0x80) P0 ; -__sfr __at (0x90) P1 ; -__sfr __at (0xA0) P2 ; -__sfr __at (0xB0) P3 ; -__sfr __at (0xD0) PSW ; -__sfr __at (0xE0) ACC ; -__sfr __at (0xF0) B ; -__sfr __at (0x81) SP ; -__sfr __at (0x82) DPL ; -__sfr __at (0x83) DPH ; -__sfr __at (0x87) PCON ; -__sfr __at (0x88) TCON ; -__sfr __at (0x89) TMOD ; -__sfr __at (0x8A) TL0 ; -__sfr __at (0x8B) TL1 ; -__sfr __at (0x8C) TH0 ; -__sfr __at (0x8D) TH1 ; -__sfr __at (0xA8) IE ; -__sfr __at (0xB8) IP ; -__sfr __at (0x98) SCON ; -__sfr __at (0x99) SBUF ; - -/* 80C51Fx/Rx Extensions */ -__sfr __at (0x8E) AUXR ; -__sfr __at (0xA2) AUXR1 ; -__sfr __at (0xA9) SADDR ; -__sfr __at (0xB7) IPH ; -__sfr __at (0xB9) SADEN ; -__sfr __at (0xC8) T2CON ; -__sfr __at (0xC9) T2MOD ; -__sfr __at (0xCA) RCAP2L ; -__sfr __at (0xCB) RCAP2H ; -__sfr __at (0xCC) TL2 ; -__sfr __at (0xCD) TH2 ; -__sfr __at (0xD8) CCON ; -__sfr __at (0xD9) CMOD ; -__sfr __at (0xDA) CCAPM0 ; -__sfr __at (0xDB) CCAPM1 ; -__sfr __at (0xDC) CCAPM2 ; -__sfr __at (0xDD) CCAPM3 ; -__sfr __at (0xDE) CCAPM4 ; -__sfr __at (0xE9) CL ; -__sfr __at (0xEA) CCAP0L ; -__sfr __at (0xEB) CCAP1L ; -__sfr __at (0xEC) CCAP2L ; -__sfr __at (0xED) CCAP3L ; -__sfr __at (0xEE) CCAP4L ; -__sfr __at (0xF9) CH ; -__sfr __at (0xFA) CCAP0H ; -__sfr __at (0xFB) CCAP1H ; -__sfr __at (0xFC) CCAP2H ; -__sfr __at (0xFD) CCAP3H ; -__sfr __at (0xFE) CCAP4H ; - - -/* BIT Registers */ -/* PSW */ - -__sbit __at (0xD7) PSW_7; -__sbit __at (0xD6) PSW_6; -__sbit __at (0xD5) PSW_5; -__sbit __at (0xD4) PSW_4; -__sbit __at (0xD3) PSW_3; -__sbit __at (0xD2) PSW_2; -__sbit __at (0xD0) PSW_0; - -#define CY PSW_7 -#define AC PSW_6 -#define F0 PSW_5 -#define RS1 PSW_4 -#define RS0 PSW_3 -#define OV PSW_2 -#define P PSW_0 - -/* TCON */ -__sbit __at (0x8F) TCON_7; -__sbit __at (0x8E) TCON_6; -__sbit __at (0x8D) TCON_5; -__sbit __at (0x8C) TCON_4; -__sbit __at (0x8B) TCON_3; -__sbit __at (0x8A) TCON_2; -__sbit __at (0x89) TCON_1; -__sbit __at (0x88) TCON_0; - -#define TF1 TCON_7 -#define TR1 TCON_6 -#define TF0 TCON_5 -#define TR0 TCON_4 -#define IE1 TCON_3 -#define IT1 TCON_2 -#define IE0 TCON_1 -#define IT0 TCON_0 - -/* IE */ -__sbit __at (0xAF) IE_7; -__sbit __at (0xAE) IE_6; -__sbit __at (0xAD) IE_5; -__sbit __at (0xAC) IE_4; -__sbit __at (0xAB) IE_3; -__sbit __at (0xAA) IE_2; -__sbit __at (0xA9) IE_1; -__sbit __at (0xA8) IE_0; - -#define EA IE_7 -#define EC IE_6 -#define ET2 IE_5 -#define ES IE_4 -#define ET1 IE_3 -#define EX1 IE_2 -#define ET0 IE_1 -#define EX0 IE_0 - -/* IP */ -__sbit __at (0xBE) IP_6; -__sbit __at (0xBD) IP_5; -__sbit __at (0xBC) IP_4; -__sbit __at (0xBB) IP_3; -__sbit __at (0xBA) IP_2; -__sbit __at (0xB9) IP_1; -__sbit __at (0xB8) IP_0; - -#define PPC IP_6 -#define PT2 IP_5 -#define PS IP_4 -#define PT1 IP_3 -#define PX1 IP_2 -#define PT0 IP_1 -#define PX0 IP_0 - -/* P3 */ -__sbit __at (0xB7) P3_7; -__sbit __at (0xB6) P3_6; -__sbit __at (0xB5) P3_5; -__sbit __at (0xB4) P3_4; -__sbit __at (0xB3) P3_3; -__sbit __at (0xB2) P3_2; -__sbit __at (0xB1) P3_1; -__sbit __at (0xB0) P3_0; - -#define RD P3_7 -#define WR P3_6 -#define T1 P3_5 -#define T0 P3_4 -#define INT1 P3_3 -#define INT0 P3_2 -#define TXD P3_1 -#define RXD P3_0 - -/* SCON */ -__sbit __at (0x9F) SCON_7; // alternatively "FE" -__sbit __at (0x9E) SCON_6; -__sbit __at (0x9D) SCON_5; -__sbit __at (0x9C) SCON_4; -__sbit __at (0x9B) SCON_3; -__sbit __at (0x9A) SCON_2; -__sbit __at (0x99) SCON_1; -__sbit __at (0x98) SCON_0; - -#define SM0 SCON_7 // alternatively "FE" -#define FE SCON_7 -#define SM1 SCON_6 -#define SM2 SCON_5 -#define REN SCON_4 -#define TB8 SCON_3 -#define RB8 SCON_2 -#define TI SCON_1 -#define RI SCON_0 - -/* P1 */ -__sbit __at (0x97) P1_7; -__sbit __at (0x96) P1_6; -__sbit __at (0x95) P1_5; -__sbit __at (0x94) P1_4; -__sbit __at (0x93) P1_3; -__sbit __at (0x92) P1_2; -__sbit __at (0x91) P1_1; -__sbit __at (0x90) P1_0; - -#define CEX4 P1_7 -#define CEX3 P1_6 -#define CEX2 P1_5 -#define CEX1 P1_4 -#define CEX0 P1_3 -#define ECI P1_2 -#define T2EX P1_1 -#define T2 P1_0 - -/* T2CON */ -__sbit __at (0xCF) T2CON_7; -__sbit __at (0xCE) T2CON_6; -__sbit __at (0xCD) T2CON_5; -__sbit __at (0xCC) T2CON_4; -__sbit __at (0xCB) T2CON_3; -__sbit __at (0xCA) T2CON_2; -__sbit __at (0xC9) T2CON_1; -__sbit __at (0xC8) T2CON_0; - -#define TF2 T2CON_7 -#define EXF2 T2CON_6 -#define RCLK T2CON_5 -#define TCLK T2CON_4 -#define EXEN2 T2CON_3 -#define TR2 T2CON_2 -#define C_T2 T2CON_1 -#define CP_RL2 T2CON_0 - -/* CCON */ -__sbit __at (0xDF) CCON_7; -__sbit __at (0xDE) CCON_6; -__sbit __at (0xDC) CCON_4; -__sbit __at (0xDB) CCON_3; -__sbit __at (0xDA) CCON_2; -__sbit __at (0xD9) CCON_1; -__sbit __at (0xD8) CCON_0; - -#define CF CCON_7 -#define CR CCON_6 -#define CCF4 CCON_4 -#define CCF3 CCON_3 -#define CCF2 CCON_2 -#define CCF1 CCON_1 -#define CCF0 CCON_0 - -#endif +/*-------------------------------------------------------------------------- +P89c51RD2.H +(English) +This header allows to use the microcontroler Philips P89c51RD2 +with the compiler SDCC. + +Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +(Spanish-Español) +Archivo encabezador para el ucontrolador Philips P89c51RD2. +Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com +Uso libre +--------------------------------------------------------------------------*/ + +#ifndef __P89c51RD2_H__ +#define __P89c51RD2_H__ + +/* BYTE Registers */ +__sfr __at (0x80) P0 ; +__sfr __at (0x90) P1 ; +__sfr __at (0xA0) P2 ; +__sfr __at (0xB0) P3 ; +__sfr __at (0xD0) PSW ; +__sfr __at (0xE0) ACC ; +__sfr __at (0xF0) B ; +__sfr __at (0x81) SP ; +__sfr __at (0x82) DPL ; +__sfr __at (0x83) DPH ; +__sfr __at (0x87) PCON ; +__sfr __at (0x88) TCON ; +__sfr __at (0x89) TMOD ; +__sfr __at (0x8A) TL0 ; +__sfr __at (0x8B) TL1 ; +__sfr __at (0x8C) TH0 ; +__sfr __at (0x8D) TH1 ; +__sfr __at (0xA8) IE ; +__sfr __at (0xB8) IP ; +__sfr __at (0x98) SCON ; +__sfr __at (0x99) SBUF ; + +/* 80C51Fx/Rx Extensions */ +__sfr __at (0x8E) AUXR ; +__sfr __at (0xA2) AUXR1 ; +__sfr __at (0xA9) SADDR ; +__sfr __at (0xB7) IPH ; +__sfr __at (0xB9) SADEN ; +__sfr __at (0xC8) T2CON ; +__sfr __at (0xC9) T2MOD ; +__sfr __at (0xCA) RCAP2L ; +__sfr __at (0xCB) RCAP2H ; +__sfr __at (0xCC) TL2 ; +__sfr __at (0xCD) TH2 ; +__sfr __at (0xD8) CCON ; +__sfr __at (0xD9) CMOD ; +__sfr __at (0xDA) CCAPM0 ; +__sfr __at (0xDB) CCAPM1 ; +__sfr __at (0xDC) CCAPM2 ; +__sfr __at (0xDD) CCAPM3 ; +__sfr __at (0xDE) CCAPM4 ; +__sfr __at (0xE9) CL ; +__sfr __at (0xEA) CCAP0L ; +__sfr __at (0xEB) CCAP1L ; +__sfr __at (0xEC) CCAP2L ; +__sfr __at (0xED) CCAP3L ; +__sfr __at (0xEE) CCAP4L ; +__sfr __at (0xF9) CH ; +__sfr __at (0xFA) CCAP0H ; +__sfr __at (0xFB) CCAP1H ; +__sfr __at (0xFC) CCAP2H ; +__sfr __at (0xFD) CCAP3H ; +__sfr __at (0xFE) CCAP4H ; + + +/* BIT Registers */ +/* PSW */ + +__sbit __at (0xD7) PSW_7; +__sbit __at (0xD6) PSW_6; +__sbit __at (0xD5) PSW_5; +__sbit __at (0xD4) PSW_4; +__sbit __at (0xD3) PSW_3; +__sbit __at (0xD2) PSW_2; +__sbit __at (0xD0) PSW_0; + +#define CY PSW_7 +#define AC PSW_6 +#define F0 PSW_5 +#define RS1 PSW_4 +#define RS0 PSW_3 +#define OV PSW_2 +#define P PSW_0 + +/* TCON */ +__sbit __at (0x8F) TCON_7; +__sbit __at (0x8E) TCON_6; +__sbit __at (0x8D) TCON_5; +__sbit __at (0x8C) TCON_4; +__sbit __at (0x8B) TCON_3; +__sbit __at (0x8A) TCON_2; +__sbit __at (0x89) TCON_1; +__sbit __at (0x88) TCON_0; + +#define TF1 TCON_7 +#define TR1 TCON_6 +#define TF0 TCON_5 +#define TR0 TCON_4 +#define IE1 TCON_3 +#define IT1 TCON_2 +#define IE0 TCON_1 +#define IT0 TCON_0 + +/* IE */ +__sbit __at (0xAF) IE_7; +__sbit __at (0xAE) IE_6; +__sbit __at (0xAD) IE_5; +__sbit __at (0xAC) IE_4; +__sbit __at (0xAB) IE_3; +__sbit __at (0xAA) IE_2; +__sbit __at (0xA9) IE_1; +__sbit __at (0xA8) IE_0; + +#define EA IE_7 +#define EC IE_6 +#define ET2 IE_5 +#define ES IE_4 +#define ET1 IE_3 +#define EX1 IE_2 +#define ET0 IE_1 +#define EX0 IE_0 + +/* IP */ +__sbit __at (0xBE) IP_6; +__sbit __at (0xBD) IP_5; +__sbit __at (0xBC) IP_4; +__sbit __at (0xBB) IP_3; +__sbit __at (0xBA) IP_2; +__sbit __at (0xB9) IP_1; +__sbit __at (0xB8) IP_0; + +#define PPC IP_6 +#define PT2 IP_5 +#define PS IP_4 +#define PT1 IP_3 +#define PX1 IP_2 +#define PT0 IP_1 +#define PX0 IP_0 + +/* P3 */ +__sbit __at (0xB7) P3_7; +__sbit __at (0xB6) P3_6; +__sbit __at (0xB5) P3_5; +__sbit __at (0xB4) P3_4; +__sbit __at (0xB3) P3_3; +__sbit __at (0xB2) P3_2; +__sbit __at (0xB1) P3_1; +__sbit __at (0xB0) P3_0; + +#define RD P3_7 +#define WR P3_6 +#define T1 P3_5 +#define T0 P3_4 +#define INT1 P3_3 +#define INT0 P3_2 +#define TXD P3_1 +#define RXD P3_0 + +/* SCON */ +__sbit __at (0x9F) SCON_7; // alternatively "FE" +__sbit __at (0x9E) SCON_6; +__sbit __at (0x9D) SCON_5; +__sbit __at (0x9C) SCON_4; +__sbit __at (0x9B) SCON_3; +__sbit __at (0x9A) SCON_2; +__sbit __at (0x99) SCON_1; +__sbit __at (0x98) SCON_0; + +#define SM0 SCON_7 // alternatively "FE" +#define FE SCON_7 +#define SM1 SCON_6 +#define SM2 SCON_5 +#define REN SCON_4 +#define TB8 SCON_3 +#define RB8 SCON_2 +#define TI SCON_1 +#define RI SCON_0 + +/* P1 */ +__sbit __at (0x97) P1_7; +__sbit __at (0x96) P1_6; +__sbit __at (0x95) P1_5; +__sbit __at (0x94) P1_4; +__sbit __at (0x93) P1_3; +__sbit __at (0x92) P1_2; +__sbit __at (0x91) P1_1; +__sbit __at (0x90) P1_0; + +#define CEX4 P1_7 +#define CEX3 P1_6 +#define CEX2 P1_5 +#define CEX1 P1_4 +#define CEX0 P1_3 +#define ECI P1_2 +#define T2EX P1_1 +#define T2 P1_0 + +/* T2CON */ +__sbit __at (0xCF) T2CON_7; +__sbit __at (0xCE) T2CON_6; +__sbit __at (0xCD) T2CON_5; +__sbit __at (0xCC) T2CON_4; +__sbit __at (0xCB) T2CON_3; +__sbit __at (0xCA) T2CON_2; +__sbit __at (0xC9) T2CON_1; +__sbit __at (0xC8) T2CON_0; + +#define TF2 T2CON_7 +#define EXF2 T2CON_6 +#define RCLK T2CON_5 +#define TCLK T2CON_4 +#define EXEN2 T2CON_3 +#define TR2 T2CON_2 +#define C_T2 T2CON_1 +#define CP_RL2 T2CON_0 + +/* CCON */ +__sbit __at (0xDF) CCON_7; +__sbit __at (0xDE) CCON_6; +__sbit __at (0xDC) CCON_4; +__sbit __at (0xDB) CCON_3; +__sbit __at (0xDA) CCON_2; +__sbit __at (0xD9) CCON_1; +__sbit __at (0xD8) CCON_0; + +#define CF CCON_7 +#define CR CCON_6 +#define CCF4 CCON_4 +#define CCF3 CCON_3 +#define CCF2 CCON_2 +#define CCF1 CCON_1 +#define CCF0 CCON_0 + +#endif diff --git a/device/include/mcs51/SST89x5xRDx.h b/device/include/mcs51/SST89x5xRDx.h index 450237fe..43f7f016 100644 --- a/device/include/mcs51/SST89x5xRDx.h +++ b/device/include/mcs51/SST89x5xRDx.h @@ -1,343 +1,343 @@ -/*------------------------------------------------------------------------- - Register Declarations for SST SST89E516RD2, ST89E516RD, SST89V516RD2, and - SST89V516RD Processors (Based on datasheed S71273-03-000 1/07) - - Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (February 2007) - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option); any later version - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - In other words, you are welcome to use, share and improve this program - You are forbidden to forbid anyone else to use, share and improve - what you give them. Help stamp out software-hoarding! --------------------------------------------------------------------------*/ - -#ifndef REG_SST89x5xRDx_H -#define REG_SST89x5xRDx_H - -#include - -// From TABLE 3-5: CPU related SFRs - -SFR(ACC, 0xE0); // Accumulator - SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0 - SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1 - SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2 - SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3 - SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4 - SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5 - SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6 - SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7 -SFR(B, 0xF0); // B Register - SBIT(B_0, 0xF0, 0); // Register B bit 0 - SBIT(B_1, 0xF0, 1); // Register B bit 1 - SBIT(B_2, 0xF0, 2); // Register B bit 2 - SBIT(B_3, 0xF0, 3); // Register B bit 3 - SBIT(B_4, 0xF0, 4); // Register B bit 4 - SBIT(B_5, 0xF0, 5); // Register B bit 5 - SBIT(B_6, 0xF0, 6); // Register B bit 6 - SBIT(B_7, 0xF0, 7); // Register B bit 7 -SFR(PSW, 0xD0); // Program Status Word - SBIT(P, 0xD0, 0); // Parity Flag - SBIT(F1, 0xD0, 1); // User-Defined Flag - SBIT(OV, 0xD0, 2); // Overflow Flag - SBIT(RS0, 0xD0, 3); // Register Bank Select 0 - SBIT(RS1, 0xD0, 4); // Register Bank Select 1 - SBIT(F0, 0xD0, 5); // User-Defined Flag - SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag - SBIT(CY, 0xD0, 7); // Carry Flag -SFR(SP, 0x81); // Stack Pointer -SFR(DPL, 0x82); // Data Pointer Low -SFR(DPH, 0x83); // Data Pointer High -SFR(IE, 0xA8); // Interrupt Enable - SBIT(EA, 0xA8, 7); // Global Interrupt Enable - SBIT(EC, 0xA8, 6); // PCA Interrupt Enable - SBIT(ET2, 0xA8, 5); // Timer 2 Interrupt Enable - SBIT(ES, 0xA8, 4); // Serial Interrupt Enable - SBIT(ET1, 0xA8, 3); // Timer 1 Interrupt Enable - SBIT(EX1, 0xA8, 2); // External 1 Interrupt Enable - SBIT(ET0, 0xA8, 1); // Timer 0 Interrupt Enable - SBIT(EX0, 0xA8, 0); // External 0 Interrupt Enable -SFR(IEA, 0xE8); // Interrupt Enable A - SBIT(EBO, 0xE8, 3); // Brown-out Interrupt Enable. (Vector is 0x00b4) -SFR(IP, 0xB8); // Interrupt Priority Reg - SBIT(PPC, 0xB8, 6); // PCA interrupt priority bit - SBIT(PT2, 0xB8, 5); // Timer 2 interrupt priority bit - SBIT(PS, 0xB8, 4); // Serial Port interrupt priority bit - SBIT(PT1, 0xB8, 3); // Timer 1 interrupt priority bit - SBIT(PX1, 0xB8, 2); // External interrupt 1 priority bit - SBIT(PT0, 0xB8, 1); // Timer 0 interrupt priority bit - SBIT(PX0, 0xB8, 0); // External interrupt 0 priority bit -SFR(IPH, 0xB7); // Interrupt Priority Reg High - #define PPCH 0x40 // PCA Interrupt Priority High Bit - #define PT2H 0x20 // Timer 2 Interrupt Interrupt Priority High Bit - #define PSH 0x10 // Serial Port Interrupt Priority High Bit - #define PT1H 0x08 // Timer 1 Interrupt Priority High Bit - #define PX1H 0x04 // External Interrupt 1 Priority High Bit - #define PT0H 0x02 // Timer 0 Interrupt Priority High Bit - #define PX0H 0x01 // External Interrupt 0 Priority High Bit -SFR(IP1, 0xF8); // Interrupt Priority Reg A - SBIT(PBO, 0xF8, 4); // Brown-out interrupt priority bit - SBIT(PX2, 0xF8, 1); // External Interrupt 2 priority bit - SBIT(PX3, 0xF8, 2); // External Interrupt 3 priority bit -SFR(IP1H, 0xF7); // Interrupt Priority Reg A High - #define PBOH 0x08 // Brown-out Interrupt priority bit high - #define PX2H 0x02 // External Interrupt 2 priority bit high - #define PX3H 0x04 // External Interrupt 3 priority bit high -SFR(PCON, 0x87); // Power Control - #define SMOD1 0x80 // Double Baud rate bit - #define SMOD0 0x40 // FE/SM0 Selection bit - #define BOF 0x20 // Brown-out detection status bit - #define POF 0x10 // Power-on reset status bit - #define GF1 0x08 // General-purpose flag bit - #define GF0 0x04 // General-purpose flag bit - #define PD 0x02 // Power-down bit - #define IDL 0x01 // Idle mode bit -SFR(AUXR, 0x8E); // Auxiliary Reg - #define EXTRAM 0x02 // Internal/External RAM access - #define AO 0x01 // Disable/Enable ALE -SFR(AUXR1, 0xA2); // Auxiliary Reg 1 - #define GF2 0x08 // General purpose user-defined flag - #define DPS 0x01 // DPTR registers select bit -SFR(XICON, 0xAE); // External Interrupt Control - #define EX2 0x04 - #define IE2 0x02 - #define IT2 0x01 - #define EX3 0x40 - #define IE3 0x20 - #define IT3 0x10 - -// TABLE 3-6: Flash Memory Programming SFRs - -SFR(SFCF, 0xB1); // SuperFlash Configuration - #define IAPEN 0x40 // Enable IAP operation - #define SWR 0x02 // Software Reset - #define BSEL 0x01 // Program memory block switching bit -SFR(SFCM, 0xB2); // SuperFlash Command - #define FIE 0x80 // Flash Interrupt Enable - #define CHIP_ERASE 0x01 - #define SECTOR_ERASE 0x0B - #define BLOCK_ERASE 0x0D - #define BYTE_VERIFY 0x0C - #define BYTE_PROGRAM 0x0E - #define PROG_SB1 0x0F - #define PROG_SB2 0x03 - #define PROG_SB3 0x05 - #define PROG_SC0 0x09 - #define ENABLE_CLOCK_DOUBLE 0x08 -SFR(SFAL, 0xB3); // SuperFlash Address Low Register - A7 to A0 -SFR(SFAH, 0xB4); // SuperFlash Address High Register - A15 to A8 -SFR(SFDT, 0xB5); // SuperFlash Data Register -SFR(SFST, 0xB6); // SuperFlash Status - #define SB1_i 0x80 // Security Bit 1 status (inverse of SB1 bit) - #define SB2_i 0x40 // Security Bit 2 status (inverse of SB2 bit) - #define SB3_i 0x20 // Security Bit 3 status (inverse of SB3 bit) - #define EDC_i 0x08 // Double Clock Status - #define FLASH_BUSY 0x04 // Flash operation completion polling bit - -// TABLE 3-7: Watchdog Timer SFRs - -SFR(WDTC, 0xC0); // Watchdog Timer Control - SBIT(WDOUT, 0xC0, 4); // Watchdog output enable - SBIT(WDRE, 0xC0, 3); // Watchdog timer reset enable - SBIT(WDTS, 0xC0, 2); // Watchdog timer reset flag - SBIT(WDT, 0xC0, 1); // Watchdog timer refresh - SBIT(SWDT, 0xC0, 0); // Start watchdog timer -SFR(WDTD, 0x85); // Watchdog Timer Data/Reload - -// TABLE 3-8: Timer/Counters SFRs - -SFR(TMOD, 0x89); // Timer/Counter Mode Control GATE C/T# M1 M0 GATE C/T# M1 M0 - #define GATE1 0x80 // External enable for timer 1 - #define C_T1 0x40 // Timer or counter select for timer 1 - #define M1_1 0x20 // Operation mode bit 1 for timer 1 - #define M0_1 0x10 // Operation mode bit 0 for timer 1 - #define GATE0 0x08 // External enable for timer 0 - #define C_T0 0x04 // Timer or counter select for timer 0 - #define M1_0 0x02 // Operation mode bit 1 for timer 0 - #define M0_0 0x01 // Operation mode bit 0 for timer 0 -SFR(TCON, 0x88); // Timer/Counter Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 - SBIT(TF1, 0x88, 7); // Timer 1 overflow flag - SBIT(TR1, 0x88, 6); // Timer 1 run control flag - SBIT(TF0, 0x88, 5); // Timer 0 overflow flag - SBIT(TR0, 0x88, 4); // Timer 0 run control flag - SBIT(IE1, 0x88, 3); // Interrupt 1 flag - SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit - SBIT(IE0, 0x88, 1); // Interrupt 0 flag - SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit -SFR(TH0, 0x8C); // Timer 0 MSB -SFR(TL0, 0x8A); // Timer 0 LSB -SFR(TH1, 0x8D); // Timer 1 MSB -SFR(TL1, 0x8B); // Timer 1 LSB -SFR(T2CON, 0xC8); // Timer / Counter 2 Control - SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag - SBIT(EXF2, 0xC8, 6); // Timer 2 external flag - SBIT(RCLK, 0xC8, 5); // Receive clock flag - SBIT(TCLK, 0xC8, 4); // Transmit clock flag - SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag - SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2 - SBIT(C_T2, 0xC8, 1); // Timer or coutner select - SBIT(CP_RL2,0xC8, 0); // Capture/reload flag -SFR(T2MOD, 0xC9); // Timer 2 Mode Control - #define DCEN 0x02 // Down count enable bit - #define T2OE 0x01 // Timer 2 output enable bit -SFR(TH2, 0xCD); // Timer 2 MSB -SFR(TL2, 0xCC); // Timer 2 LSB -SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB -SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB - -// TABLE 3-9: Interface SFRs - -SFR(SBUF, 0x99); // Serial Data Buffer -SFR(SCON, 0x98); // Serial Port Control - SBIT(FE, 0x98, 7); // Framing Error when reading, SM0 when writing - SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0 - SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1 - SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2 - SBIT(REN, 0x98, 4); // Enables serial reception - SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3 - SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received - SBIT(TI, 0x98, 1); // Transmit interrupt flag - SBIT(RI, 0x98, 0); // Receive interrupt flag -SFR(SADDR, 0xA9); // Slave Address -SFR(SADEN, 0xB9); // Slave Address Mask -SFR(SPCR, 0xD5); // SPI Control Register - #define SPIE 0x80 // If both SPIE and ES are set to one, SPI interrupts are enabled - #define SPE 0x40 // SPI enable bit. When set enables SPI - #define DORD 0x20 // Data trans. order. 0=MSB first; 1=LSB first - #define MSTR 0x10 // 1=master mode. 0=slave mode - #define CPOL 0x08 // 1=SCK is high when idle (active low), 0=SCK is low when idle (active high) - #define CPHA 0x04 // 1=shift triggered on the trailing edge of SCK. 0=shift trig. on leading edge - #define SPR1 0x02 // SPI Clork Rate select bit 1 - #define SPR0 0x01 // SPI Clork Rate select bit 0 - // 00 = Fosc/4 - // 01 = Fosc/16 - // 10 = Fosc/64 - // 11 = Fosc/128 -SFR(SPSR, 0xAA); // SPI Status Register - #define SPIF 0x80 // SPI interrupt flag - #define WCOL 0x40 // Write collision Flag -SFR(SPDR, 0x86); // SPI Data Register -SFR(P0, 0x80); // Port 0 - SBIT(P0_0, 0x80, 0); // Port 0 bit 0 - SBIT(P0_1, 0x80, 1); // Port 0 bit 1 - SBIT(P0_2, 0x80, 2); // Port 0 bit 2 - SBIT(P0_3, 0x80, 3); // Port 0 bit 3 - SBIT(P0_4, 0x80, 4); // Port 0 bit 4 - SBIT(P0_5, 0x80, 5); // Port 0 bit 5 - SBIT(P0_6, 0x80, 6); // Port 0 bit 6 - SBIT(P0_7, 0x80, 7); // Port 0 bit 7 -SFR(P1, 0x90); // Port 1 - SBIT(P1_0, 0x90, 0); // Port 1 bit 0 - SBIT(P1_1, 0x90, 1); // Port 1 bit 1 - SBIT(P1_2, 0x90, 2); // Port 1 bit 2 - SBIT(P1_3, 0x90, 3); // Port 1 bit 3 - SBIT(P1_4, 0x90, 4); // Port 1 bit 4 - SBIT(P1_5, 0x90, 5); // Port 1 bit 5 - SBIT(P1_6, 0x90, 6); // Port 1 bit 6 - SBIT(P1_7, 0x90, 7); // Port 1 bit 7 - // Alternate names - SBIT(T2, 0x90, 0); // Port 1 bit 0 - SBIT(T2EX, 0x90, 1); // Port 1 bit 1 - SBIT(ECI, 0x90, 2); // Port 1 bit 2 - SBIT(CEX0, 0x90, 3); // Port 1 bit 3 - SBIT(CEX1, 0x90, 4); // Port 1 bit 4 - SBIT(CEX2, 0x90, 5); // Port 1 bit 5 - SBIT(CEX3, 0x90, 6); // Port 1 bit 6 - SBIT(CEX4, 0x90, 7); // Port 1 bit 7 - // More alternate names - SBIT(SS, 0x90, 4); // Port 1 bit 4 - SBIT(MOSI, 0x90, 5); // Port 1 bit 5 - SBIT(MISO, 0x90, 6); // Port 1 bit 6 - SBIT(SCK, 0x90, 7); // Port 1 bit 7 -SFR(P2, 0xA0); // Port 2 - SBIT(P2_0, 0xA0, 0); // Port 2 bit 0 - SBIT(P2_1, 0xA0, 1); // Port 2 bit 1 - SBIT(P2_2, 0xA0, 2); // Port 2 bit 2 - SBIT(P2_3, 0xA0, 3); // Port 2 bit 3 - SBIT(P2_4, 0xA0, 4); // Port 2 bit 4 - SBIT(P2_5, 0xA0, 5); // Port 2 bit 5 - SBIT(P2_6, 0xA0, 6); // Port 2 bit 6 - SBIT(P2_7, 0xA0, 7); // Port 2 bit 7 -SFR(P3, 0xB0); // Port 3 - SBIT(P3_0, 0xB0, 0); // Port 2 bit 0 - SBIT(P3_1, 0xB0, 1); // Port 2 bit 1 - SBIT(P3_2, 0xB0, 2); // Port 2 bit 2 - SBIT(P3_3, 0xB0, 3); // Port 2 bit 3 - SBIT(P3_4, 0xB0, 4); // Port 2 bit 4 - SBIT(P3_5, 0xB0, 5); // Port 2 bit 5 - SBIT(P3_6, 0xB0, 6); // Port 2 bit 6 - SBIT(P3_7, 0xB0, 7); // Port 2 bit 7 - // Alternate names - SBIT(RXD, 0xB0, 0); // Port 2 bit 0 - SBIT(TXD, 0xB0, 1); // Port 2 bit 1 - SBIT(INT0, 0xB0, 2); // Port 2 bit 2 - SBIT(INT1, 0xB0, 3); // Port 2 bit 3 - SBIT(T0, 0xB0, 4); // Port 2 bit 4 - SBIT(T1, 0xB0, 5); // Port 2 bit 5 - SBIT(WR, 0xB0, 6); // Port 2 bit 6 - SBIT(RD, 0xB0, 7); // Port 2 bit 7 -SFR(P4, 0xA5); // Port 4 - not bit addressable - #define P4_0 0x01 - #define P4_1 0x02 - #define P4_2 0x04 - #define P4_3 0x08 - -// TABLE 3-10: PCA SFRs - -SFR(CH, 0xF9); // PCA Timer/Counter High -SFR(CL, 0xE9); // PCA Timer/Counter Low -SFR(CCON, 0xD8); // PCA Timer/Counter Control Register CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 00x00000b - SBIT(CF, 0xD8, 7); // PCA Counter overflow flag - SBIT(CR, 0xD8, 6); // PCA Counter Run Control Bit - SBIT(CCF4, 0xD8, 4); // PCA Module 4 Interrupt Flag - SBIT(CCF3, 0xD8, 3); // PCA Module 3 Interrupt Flag - SBIT(CCF2, 0xD8, 2); // PCA Module 2 Interrupt Flag - SBIT(CCF1, 0xD8, 1); // PCA Module 1 Interrupt Flag - SBIT(CCF0, 0xD8, 0); // PCA Module 0 Interrupt Flag -SFR(CMOD, 0xD9); // PCA Timer/Counter Mode Register - #define CIDL 0x80 // CIDL=0 program the PCA counter to work during idle mode - #define WDTE 0x40 // Watchdog Timer Enable - #define CPS1 0x04 // PCA Count Pulse Select bit 1 - #define CPS0 0x02 // PCA Count Pulse Select bit 0 - // 00=Internal clock, Fosc/6 - // 01=Internal clock, Fosc/6 - // 10=Timer 0 overflow - // 11=External clock at ECI/P1.2 pin (max rate=Fosc/4) - #define ECF 0x01 // PCA Enable Counter Overflow Interrupt -SFR(CCAP0H, 0xFA); // PCA Module 0 Compare/Capture Register High -SFR(CCAP0L, 0xEA); // PCA Module 0 Compare/Capture Register Low -SFR(CCAP1H, 0xFB); // PCA Module 1 Compare/Capture Register High -SFR(CCAP1L, 0xEB); // PCA Module 1 Compare/Capture Register Low -SFR(CCAP2H, 0xFC); // PCA Module 2 Compare/Capture Register High -SFR(CCAP2L, 0xEC); // PCA Module 2 Compare/Capture Register Low -SFR(CCAP3H, 0xFD); // PCA Module 3 Compare/Capture Register High -SFR(CCAP3L, 0xED); // PCA Module 3 Compare/Capture Register Low -SFR(CCAP4H, 0xFE); // PCA Module 4 Compare/Capture Register High -SFR(CCAP4L, 0xEE); // PCA Module 4 Compare/Capture Register Low -SFR(CCAPM0, 0xDA); // PCA Compare/Capture Module 0 Mode Register -SFR(CCAPM1, 0xDB); // PCA Compare/Capture Module 1 Mode Register -SFR(CCAPM2, 0xDC); // PCA Compare/Capture Module 2 Mode Register -SFR(CCAPM3, 0xDD); // PCA Compare/Capture Module 3 Mode Register -SFR(CCAPM4, 0xDE); // PCA Compare/Capture Module 4 Mode Register -// The preceding five registers have the following bits: - #define ECOM 0x40 // Enable Comparator - #define CAPP 0x20 // 1=enables positive edge capture - #define CAPN 0x10 // 1=enables negative edge capture - #define MAT 0x08 // When counter matches sets CCFn bit causing and interrupt - #define TOG 0x04 // Toggle output on match - #define PWM 0x02 // Pulse width modulation mode - #define ECCF 0x01 // Enable CCF interrupt - -#endif /*REG_SST89x5xRDx_H*/ +/*------------------------------------------------------------------------- + Register Declarations for SST SST89E516RD2, ST89E516RD, SST89V516RD2, and + SST89V516RD Processors (Based on datasheed S71273-03-000 1/07) + + Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (February 2007) + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option); any later version + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + In other words, you are welcome to use, share and improve this program + You are forbidden to forbid anyone else to use, share and improve + what you give them. Help stamp out software-hoarding! +-------------------------------------------------------------------------*/ + +#ifndef REG_SST89x5xRDx_H +#define REG_SST89x5xRDx_H + +#include + +// From TABLE 3-5: CPU related SFRs + +SFR(ACC, 0xE0); // Accumulator + SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0 + SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1 + SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2 + SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3 + SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4 + SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5 + SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6 + SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7 +SFR(B, 0xF0); // B Register + SBIT(B_0, 0xF0, 0); // Register B bit 0 + SBIT(B_1, 0xF0, 1); // Register B bit 1 + SBIT(B_2, 0xF0, 2); // Register B bit 2 + SBIT(B_3, 0xF0, 3); // Register B bit 3 + SBIT(B_4, 0xF0, 4); // Register B bit 4 + SBIT(B_5, 0xF0, 5); // Register B bit 5 + SBIT(B_6, 0xF0, 6); // Register B bit 6 + SBIT(B_7, 0xF0, 7); // Register B bit 7 +SFR(PSW, 0xD0); // Program Status Word + SBIT(P, 0xD0, 0); // Parity Flag + SBIT(F1, 0xD0, 1); // User-Defined Flag + SBIT(OV, 0xD0, 2); // Overflow Flag + SBIT(RS0, 0xD0, 3); // Register Bank Select 0 + SBIT(RS1, 0xD0, 4); // Register Bank Select 1 + SBIT(F0, 0xD0, 5); // User-Defined Flag + SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag + SBIT(CY, 0xD0, 7); // Carry Flag +SFR(SP, 0x81); // Stack Pointer +SFR(DPL, 0x82); // Data Pointer Low +SFR(DPH, 0x83); // Data Pointer High +SFR(IE, 0xA8); // Interrupt Enable + SBIT(EA, 0xA8, 7); // Global Interrupt Enable + SBIT(EC, 0xA8, 6); // PCA Interrupt Enable + SBIT(ET2, 0xA8, 5); // Timer 2 Interrupt Enable + SBIT(ES, 0xA8, 4); // Serial Interrupt Enable + SBIT(ET1, 0xA8, 3); // Timer 1 Interrupt Enable + SBIT(EX1, 0xA8, 2); // External 1 Interrupt Enable + SBIT(ET0, 0xA8, 1); // Timer 0 Interrupt Enable + SBIT(EX0, 0xA8, 0); // External 0 Interrupt Enable +SFR(IEA, 0xE8); // Interrupt Enable A + SBIT(EBO, 0xE8, 3); // Brown-out Interrupt Enable. (Vector is 0x00b4) +SFR(IP, 0xB8); // Interrupt Priority Reg + SBIT(PPC, 0xB8, 6); // PCA interrupt priority bit + SBIT(PT2, 0xB8, 5); // Timer 2 interrupt priority bit + SBIT(PS, 0xB8, 4); // Serial Port interrupt priority bit + SBIT(PT1, 0xB8, 3); // Timer 1 interrupt priority bit + SBIT(PX1, 0xB8, 2); // External interrupt 1 priority bit + SBIT(PT0, 0xB8, 1); // Timer 0 interrupt priority bit + SBIT(PX0, 0xB8, 0); // External interrupt 0 priority bit +SFR(IPH, 0xB7); // Interrupt Priority Reg High + #define PPCH 0x40 // PCA Interrupt Priority High Bit + #define PT2H 0x20 // Timer 2 Interrupt Interrupt Priority High Bit + #define PSH 0x10 // Serial Port Interrupt Priority High Bit + #define PT1H 0x08 // Timer 1 Interrupt Priority High Bit + #define PX1H 0x04 // External Interrupt 1 Priority High Bit + #define PT0H 0x02 // Timer 0 Interrupt Priority High Bit + #define PX0H 0x01 // External Interrupt 0 Priority High Bit +SFR(IP1, 0xF8); // Interrupt Priority Reg A + SBIT(PBO, 0xF8, 4); // Brown-out interrupt priority bit + SBIT(PX2, 0xF8, 1); // External Interrupt 2 priority bit + SBIT(PX3, 0xF8, 2); // External Interrupt 3 priority bit +SFR(IP1H, 0xF7); // Interrupt Priority Reg A High + #define PBOH 0x08 // Brown-out Interrupt priority bit high + #define PX2H 0x02 // External Interrupt 2 priority bit high + #define PX3H 0x04 // External Interrupt 3 priority bit high +SFR(PCON, 0x87); // Power Control + #define SMOD1 0x80 // Double Baud rate bit + #define SMOD0 0x40 // FE/SM0 Selection bit + #define BOF 0x20 // Brown-out detection status bit + #define POF 0x10 // Power-on reset status bit + #define GF1 0x08 // General-purpose flag bit + #define GF0 0x04 // General-purpose flag bit + #define PD 0x02 // Power-down bit + #define IDL 0x01 // Idle mode bit +SFR(AUXR, 0x8E); // Auxiliary Reg + #define EXTRAM 0x02 // Internal/External RAM access + #define AO 0x01 // Disable/Enable ALE +SFR(AUXR1, 0xA2); // Auxiliary Reg 1 + #define GF2 0x08 // General purpose user-defined flag + #define DPS 0x01 // DPTR registers select bit +SFR(XICON, 0xAE); // External Interrupt Control + #define EX2 0x04 + #define IE2 0x02 + #define IT2 0x01 + #define EX3 0x40 + #define IE3 0x20 + #define IT3 0x10 + +// TABLE 3-6: Flash Memory Programming SFRs + +SFR(SFCF, 0xB1); // SuperFlash Configuration + #define IAPEN 0x40 // Enable IAP operation + #define SWR 0x02 // Software Reset + #define BSEL 0x01 // Program memory block switching bit +SFR(SFCM, 0xB2); // SuperFlash Command + #define FIE 0x80 // Flash Interrupt Enable + #define CHIP_ERASE 0x01 + #define SECTOR_ERASE 0x0B + #define BLOCK_ERASE 0x0D + #define BYTE_VERIFY 0x0C + #define BYTE_PROGRAM 0x0E + #define PROG_SB1 0x0F + #define PROG_SB2 0x03 + #define PROG_SB3 0x05 + #define PROG_SC0 0x09 + #define ENABLE_CLOCK_DOUBLE 0x08 +SFR(SFAL, 0xB3); // SuperFlash Address Low Register - A7 to A0 +SFR(SFAH, 0xB4); // SuperFlash Address High Register - A15 to A8 +SFR(SFDT, 0xB5); // SuperFlash Data Register +SFR(SFST, 0xB6); // SuperFlash Status + #define SB1_i 0x80 // Security Bit 1 status (inverse of SB1 bit) + #define SB2_i 0x40 // Security Bit 2 status (inverse of SB2 bit) + #define SB3_i 0x20 // Security Bit 3 status (inverse of SB3 bit) + #define EDC_i 0x08 // Double Clock Status + #define FLASH_BUSY 0x04 // Flash operation completion polling bit + +// TABLE 3-7: Watchdog Timer SFRs + +SFR(WDTC, 0xC0); // Watchdog Timer Control + SBIT(WDOUT, 0xC0, 4); // Watchdog output enable + SBIT(WDRE, 0xC0, 3); // Watchdog timer reset enable + SBIT(WDTS, 0xC0, 2); // Watchdog timer reset flag + SBIT(WDT, 0xC0, 1); // Watchdog timer refresh + SBIT(SWDT, 0xC0, 0); // Start watchdog timer +SFR(WDTD, 0x85); // Watchdog Timer Data/Reload + +// TABLE 3-8: Timer/Counters SFRs + +SFR(TMOD, 0x89); // Timer/Counter Mode Control GATE C/T# M1 M0 GATE C/T# M1 M0 + #define GATE1 0x80 // External enable for timer 1 + #define C_T1 0x40 // Timer or counter select for timer 1 + #define M1_1 0x20 // Operation mode bit 1 for timer 1 + #define M0_1 0x10 // Operation mode bit 0 for timer 1 + #define GATE0 0x08 // External enable for timer 0 + #define C_T0 0x04 // Timer or counter select for timer 0 + #define M1_0 0x02 // Operation mode bit 1 for timer 0 + #define M0_0 0x01 // Operation mode bit 0 for timer 0 +SFR(TCON, 0x88); // Timer/Counter Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 + SBIT(TF1, 0x88, 7); // Timer 1 overflow flag + SBIT(TR1, 0x88, 6); // Timer 1 run control flag + SBIT(TF0, 0x88, 5); // Timer 0 overflow flag + SBIT(TR0, 0x88, 4); // Timer 0 run control flag + SBIT(IE1, 0x88, 3); // Interrupt 1 flag + SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit + SBIT(IE0, 0x88, 1); // Interrupt 0 flag + SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit +SFR(TH0, 0x8C); // Timer 0 MSB +SFR(TL0, 0x8A); // Timer 0 LSB +SFR(TH1, 0x8D); // Timer 1 MSB +SFR(TL1, 0x8B); // Timer 1 LSB +SFR(T2CON, 0xC8); // Timer / Counter 2 Control + SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag + SBIT(EXF2, 0xC8, 6); // Timer 2 external flag + SBIT(RCLK, 0xC8, 5); // Receive clock flag + SBIT(TCLK, 0xC8, 4); // Transmit clock flag + SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag + SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2 + SBIT(C_T2, 0xC8, 1); // Timer or coutner select + SBIT(CP_RL2,0xC8, 0); // Capture/reload flag +SFR(T2MOD, 0xC9); // Timer 2 Mode Control + #define DCEN 0x02 // Down count enable bit + #define T2OE 0x01 // Timer 2 output enable bit +SFR(TH2, 0xCD); // Timer 2 MSB +SFR(TL2, 0xCC); // Timer 2 LSB +SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB +SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB + +// TABLE 3-9: Interface SFRs + +SFR(SBUF, 0x99); // Serial Data Buffer +SFR(SCON, 0x98); // Serial Port Control + SBIT(FE, 0x98, 7); // Framing Error when reading, SM0 when writing + SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0 + SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1 + SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2 + SBIT(REN, 0x98, 4); // Enables serial reception + SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3 + SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received + SBIT(TI, 0x98, 1); // Transmit interrupt flag + SBIT(RI, 0x98, 0); // Receive interrupt flag +SFR(SADDR, 0xA9); // Slave Address +SFR(SADEN, 0xB9); // Slave Address Mask +SFR(SPCR, 0xD5); // SPI Control Register + #define SPIE 0x80 // If both SPIE and ES are set to one, SPI interrupts are enabled + #define SPE 0x40 // SPI enable bit. When set enables SPI + #define DORD 0x20 // Data trans. order. 0=MSB first; 1=LSB first + #define MSTR 0x10 // 1=master mode. 0=slave mode + #define CPOL 0x08 // 1=SCK is high when idle (active low), 0=SCK is low when idle (active high) + #define CPHA 0x04 // 1=shift triggered on the trailing edge of SCK. 0=shift trig. on leading edge + #define SPR1 0x02 // SPI Clork Rate select bit 1 + #define SPR0 0x01 // SPI Clork Rate select bit 0 + // 00 = Fosc/4 + // 01 = Fosc/16 + // 10 = Fosc/64 + // 11 = Fosc/128 +SFR(SPSR, 0xAA); // SPI Status Register + #define SPIF 0x80 // SPI interrupt flag + #define WCOL 0x40 // Write collision Flag +SFR(SPDR, 0x86); // SPI Data Register +SFR(P0, 0x80); // Port 0 + SBIT(P0_0, 0x80, 0); // Port 0 bit 0 + SBIT(P0_1, 0x80, 1); // Port 0 bit 1 + SBIT(P0_2, 0x80, 2); // Port 0 bit 2 + SBIT(P0_3, 0x80, 3); // Port 0 bit 3 + SBIT(P0_4, 0x80, 4); // Port 0 bit 4 + SBIT(P0_5, 0x80, 5); // Port 0 bit 5 + SBIT(P0_6, 0x80, 6); // Port 0 bit 6 + SBIT(P0_7, 0x80, 7); // Port 0 bit 7 +SFR(P1, 0x90); // Port 1 + SBIT(P1_0, 0x90, 0); // Port 1 bit 0 + SBIT(P1_1, 0x90, 1); // Port 1 bit 1 + SBIT(P1_2, 0x90, 2); // Port 1 bit 2 + SBIT(P1_3, 0x90, 3); // Port 1 bit 3 + SBIT(P1_4, 0x90, 4); // Port 1 bit 4 + SBIT(P1_5, 0x90, 5); // Port 1 bit 5 + SBIT(P1_6, 0x90, 6); // Port 1 bit 6 + SBIT(P1_7, 0x90, 7); // Port 1 bit 7 + // Alternate names + SBIT(T2, 0x90, 0); // Port 1 bit 0 + SBIT(T2EX, 0x90, 1); // Port 1 bit 1 + SBIT(ECI, 0x90, 2); // Port 1 bit 2 + SBIT(CEX0, 0x90, 3); // Port 1 bit 3 + SBIT(CEX1, 0x90, 4); // Port 1 bit 4 + SBIT(CEX2, 0x90, 5); // Port 1 bit 5 + SBIT(CEX3, 0x90, 6); // Port 1 bit 6 + SBIT(CEX4, 0x90, 7); // Port 1 bit 7 + // More alternate names + SBIT(SS, 0x90, 4); // Port 1 bit 4 + SBIT(MOSI, 0x90, 5); // Port 1 bit 5 + SBIT(MISO, 0x90, 6); // Port 1 bit 6 + SBIT(SCK, 0x90, 7); // Port 1 bit 7 +SFR(P2, 0xA0); // Port 2 + SBIT(P2_0, 0xA0, 0); // Port 2 bit 0 + SBIT(P2_1, 0xA0, 1); // Port 2 bit 1 + SBIT(P2_2, 0xA0, 2); // Port 2 bit 2 + SBIT(P2_3, 0xA0, 3); // Port 2 bit 3 + SBIT(P2_4, 0xA0, 4); // Port 2 bit 4 + SBIT(P2_5, 0xA0, 5); // Port 2 bit 5 + SBIT(P2_6, 0xA0, 6); // Port 2 bit 6 + SBIT(P2_7, 0xA0, 7); // Port 2 bit 7 +SFR(P3, 0xB0); // Port 3 + SBIT(P3_0, 0xB0, 0); // Port 2 bit 0 + SBIT(P3_1, 0xB0, 1); // Port 2 bit 1 + SBIT(P3_2, 0xB0, 2); // Port 2 bit 2 + SBIT(P3_3, 0xB0, 3); // Port 2 bit 3 + SBIT(P3_4, 0xB0, 4); // Port 2 bit 4 + SBIT(P3_5, 0xB0, 5); // Port 2 bit 5 + SBIT(P3_6, 0xB0, 6); // Port 2 bit 6 + SBIT(P3_7, 0xB0, 7); // Port 2 bit 7 + // Alternate names + SBIT(RXD, 0xB0, 0); // Port 2 bit 0 + SBIT(TXD, 0xB0, 1); // Port 2 bit 1 + SBIT(INT0, 0xB0, 2); // Port 2 bit 2 + SBIT(INT1, 0xB0, 3); // Port 2 bit 3 + SBIT(T0, 0xB0, 4); // Port 2 bit 4 + SBIT(T1, 0xB0, 5); // Port 2 bit 5 + SBIT(WR, 0xB0, 6); // Port 2 bit 6 + SBIT(RD, 0xB0, 7); // Port 2 bit 7 +SFR(P4, 0xA5); // Port 4 - not bit addressable + #define P4_0 0x01 + #define P4_1 0x02 + #define P4_2 0x04 + #define P4_3 0x08 + +// TABLE 3-10: PCA SFRs + +SFR(CH, 0xF9); // PCA Timer/Counter High +SFR(CL, 0xE9); // PCA Timer/Counter Low +SFR(CCON, 0xD8); // PCA Timer/Counter Control Register CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 00x00000b + SBIT(CF, 0xD8, 7); // PCA Counter overflow flag + SBIT(CR, 0xD8, 6); // PCA Counter Run Control Bit + SBIT(CCF4, 0xD8, 4); // PCA Module 4 Interrupt Flag + SBIT(CCF3, 0xD8, 3); // PCA Module 3 Interrupt Flag + SBIT(CCF2, 0xD8, 2); // PCA Module 2 Interrupt Flag + SBIT(CCF1, 0xD8, 1); // PCA Module 1 Interrupt Flag + SBIT(CCF0, 0xD8, 0); // PCA Module 0 Interrupt Flag +SFR(CMOD, 0xD9); // PCA Timer/Counter Mode Register + #define CIDL 0x80 // CIDL=0 program the PCA counter to work during idle mode + #define WDTE 0x40 // Watchdog Timer Enable + #define CPS1 0x04 // PCA Count Pulse Select bit 1 + #define CPS0 0x02 // PCA Count Pulse Select bit 0 + // 00=Internal clock, Fosc/6 + // 01=Internal clock, Fosc/6 + // 10=Timer 0 overflow + // 11=External clock at ECI/P1.2 pin (max rate=Fosc/4) + #define ECF 0x01 // PCA Enable Counter Overflow Interrupt +SFR(CCAP0H, 0xFA); // PCA Module 0 Compare/Capture Register High +SFR(CCAP0L, 0xEA); // PCA Module 0 Compare/Capture Register Low +SFR(CCAP1H, 0xFB); // PCA Module 1 Compare/Capture Register High +SFR(CCAP1L, 0xEB); // PCA Module 1 Compare/Capture Register Low +SFR(CCAP2H, 0xFC); // PCA Module 2 Compare/Capture Register High +SFR(CCAP2L, 0xEC); // PCA Module 2 Compare/Capture Register Low +SFR(CCAP3H, 0xFD); // PCA Module 3 Compare/Capture Register High +SFR(CCAP3L, 0xED); // PCA Module 3 Compare/Capture Register Low +SFR(CCAP4H, 0xFE); // PCA Module 4 Compare/Capture Register High +SFR(CCAP4L, 0xEE); // PCA Module 4 Compare/Capture Register Low +SFR(CCAPM0, 0xDA); // PCA Compare/Capture Module 0 Mode Register +SFR(CCAPM1, 0xDB); // PCA Compare/Capture Module 1 Mode Register +SFR(CCAPM2, 0xDC); // PCA Compare/Capture Module 2 Mode Register +SFR(CCAPM3, 0xDD); // PCA Compare/Capture Module 3 Mode Register +SFR(CCAPM4, 0xDE); // PCA Compare/Capture Module 4 Mode Register +// The preceding five registers have the following bits: + #define ECOM 0x40 // Enable Comparator + #define CAPP 0x20 // 1=enables positive edge capture + #define CAPN 0x10 // 1=enables negative edge capture + #define MAT 0x08 // When counter matches sets CCFn bit causing and interrupt + #define TOG 0x04 // Toggle output on match + #define PWM 0x02 // Pulse width modulation mode + #define ECCF 0x01 // Enable CCF interrupt + +#endif /*REG_SST89x5xRDx_H*/ diff --git a/device/include/mcs51/cc2430.h b/device/include/mcs51/cc2430.h index 76ad5370..d4d455c5 100644 --- a/device/include/mcs51/cc2430.h +++ b/device/include/mcs51/cc2430.h @@ -1,431 +1,431 @@ -/*------------------------------------------------------------------------- - Register Declarations for Chipcon CC2430 - - Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (December 2006) - (Based on CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A) - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - In other words, you are welcome to use, share and improve this program. - You are forbidden to forbid anyone else to use, share and improve - what you give them. Help stamp out software-hoarding! --------------------------------------------------------------------------*/ - -#ifndef REG_CC2430_H -#define REG_CC2430_H - -#include - -// Interrupt Vectors - -#define RFERR_VECTOR 0 // RF TX FIFO underflow and RX FIFO overflow. -#define ADC_VECTOR 1 // ADC end of conversion -#define URX0_VECTOR 2 // USART0 RX complete -#define URX1_VECTOR 3 // USART1 RX complete -#define ENC_VECTOR 4 // AES encryption/decryption complete -#define ST_VECTOR 5 // Sleep Timer compare -#define P2INT_VECTOR 6 // Port 2 inputs -#define UTX0_VECTOR 7 // USART0 TX complete -#define DMA_VECTOR 8 // DMA transfer complete -#define T1_VECTOR 9 // Timer 1 (16-bit) capture/compare/overflow -#define T2_VECTOR 10 // Timer 2 (MAC Timer) -#define T3_VECTOR 11 // Timer 3 (8-bit) capture/compare/overflow -#define T4_VECTOR 12 // Timer 4 (8-bit) capture/compare/overflow -#define P0INT_VECTOR 13 // Port 0 inputs -#define UTX1_VECTOR 14 // USART1 TX complete -#define P1INT_VECTOR 15 // Port 1 inputs -#define RF_VECTOR 16 // RF general interrupts -#define WDT_VECTOR 17 // Watchdog overflow in timer mode - -// SFR Registers and BITs - -SFR(P0, 0x80); // Port 0 - SBIT(P0_0, 0x80, 0); // Port 0 bit 0 - SBIT(P0_1, 0x80, 1); // Port 0 bit 1 - SBIT(P0_2, 0x80, 2); // Port 0 bit 2 - SBIT(P0_3, 0x80, 3); // Port 0 bit 3 - SBIT(P0_4, 0x80, 4); // Port 0 bit 4 - SBIT(P0_5, 0x80, 5); // Port 0 bit 5 - SBIT(P0_6, 0x80, 6); // Port 0 bit 6 - SBIT(P0_7, 0x80, 7); // Port 0 bit 7 -SFR(SP, 0x81); // Stack Pointer -SFR(DPL0, 0x82); // Data Pointer 0 Low Byte -SFR(DPH0, 0x83); // Data Pointer 0 High Byte -SFR(DPL1, 0x84); // Data Pointer 1 Low Byte -SFR(DPH1, 0x85); // Data Pointer 1 High Byte -SFR(U0CSR, 0x86); // USART 0 Control and Status -SFR(PCON, 0x87); // Power Mode Control -SFR(TCON, 0x88); // Interrupt Flags - SBIT(IT0, 0x88, 0); // reserved (must always be set to 1) - SBIT(RFERRIF, 0x88, 1); // RFERR – RF TX/RX FIFO interrupt flag - SBIT(IT1, 0x88, 2); // reserved (must always be set to 1) - SBIT(URX0IF, 0x88, 3); // USART0 RX Interrupt Flag - SBIT(ADCIF, 0x88, 5); // ADC Interrupt Flag - SBIT(URX1IF, 0x88, 7); // USART1 RX Interrupt Flag -SFR(P0IFG, 0x89); // Port 0 Interrupt Status Flag -SFR(P1IFG, 0x8A); // Port 1 Interrupt Status Flag -SFR(P2IFG, 0x8B); // Port 2 Interrupt Status Flag -SFR(PICTL, 0x8C); // Port Interrupt Control -SFR(P1IEN, 0x8D); // Port 1 Interrupt Mask -SFR(P0INP, 0x8F); // Port 0 Input Mode -SFR(P1, 0x90); // Port 1 - SBIT(P1_0, 0x90, 0); // Port 1 bit 0 - SBIT(P1_1, 0x90, 1); // Port 1 bit 1 - SBIT(P1_2, 0x90, 2); // Port 1 bit 2 - SBIT(P1_3, 0x90, 3); // Port 1 bit 3 - SBIT(P1_4, 0x90, 4); // Port 1 bit 4 - SBIT(P1_5, 0x90, 5); // Port 1 bit 5 - SBIT(P1_6, 0x90, 6); // Port 1 bit 6 - SBIT(P1_7, 0x90, 7); // Port 1 bit 7 -SFR(RFIM, 0x91); // RF Interrupt Mask -SFR(DPS, 0x92); // Data Pointer Select -SFR(MPAGE, 0x93); // Memory Page Select -SFR(_XPAGE, 0x93); // Memory Page Select under the name SDCC needs it -SFR(T2CMP, 0x94); // Timer 2 Compare Value -SFR(ST0, 0x95); // Sleep Timer 0 -SFR(ST1, 0x96); // Sleep Timer 1 -SFR(ST2, 0x97); // Sleep Timer 2 -SFR(S0CON, 0x98); // Interrupt Flags 2 - SBIT(ENCIF_0, 0x98, 0); // AES Interrupt Flag 0 - SBIT(ENCIF_1, 0x98, 1); // AES Interrupt Flag 1 -SFR(IEN2, 0x9A); // Interrupt Enable 2 -SFR(S1CON, 0x9B); // Interrupt Flags 3 -SFR(T2PEROF0, 0x9C); // Timer 2 Overflow Capture/Compare 0 -SFR(T2PEROF1, 0x9D); // Timer 2 Overflow Capture/Compare 1 -SFR(T2PEROF2, 0x9E); // Timer 2 Overflow Capture/Compare 2 -SFR(P2, 0xA0); // Port 2 - SBIT(P2_0, 0xA0, 0); // Port 2 bit 0 - SBIT(P2_1, 0xA0, 1); // Port 2 bit 1 - SBIT(P2_2, 0xA0, 2); // Port 2 bit 2 - SBIT(P2_3, 0xA0, 3); // Port 2 bit 3 - SBIT(P2_4, 0xA0, 4); // Port 2 bit 4 - SBIT(P2_5, 0xA0, 5); // Port 2 bit 5 - SBIT(P2_6, 0xA0, 6); // Port 2 bit 6 - SBIT(P2_7, 0xA0, 7); // Port 2 bit 7 -SFR(T2OF0, 0xA1); // Timer 2 Overflow Count 0 -SFR(T2OF1, 0xA2); // Timer 2 Overflow Count 1 -SFR(T2OF2, 0xA3); // Timer 2 Overflow Count 2 -SFR(T2CAPLPL, 0xA4); // Timer 2 Period Low Byte -SFR(T2CAPHPH, 0xA5); // Timer 2 Period High Byte -SFR(T2TLD, 0xA6); // Timer 2 Timer Value Low Byte -SFR(T2THD, 0xA7); // Timer 2 Timer Value High Byte -SFR(IEN0, 0xA8); // Interrupt Enable 0 - SBIT(RFERRIE, 0xA8, 0); // RF TX/RX FIFO interrupt enable - SBIT(ADCIE, 0xA8, 1); // ADC Interrupt Enable - SBIT(URX0IE, 0xA8, 2); // USART0 RX Interrupt Enable - SBIT(URX1IE, 0xA8, 3); // USART1 RX Interrupt Enable - SBIT(ENCIE, 0xA8, 4); // AES Encryption/Decryption Interrupt Enable - SBIT(STIE, 0xA8, 5); // Sleep Timer Interrupt Enable - SBIT(EA, 0xA8, 7); // Global Interrupt Enable -SFR(IP0, 0xA9); // Interrupt Priority 0 -SFR(FWT, 0xAB); // Flash Write Timing -SFR(FADDRL, 0xAC); // Flash Address Low Byte -SFR(FADDRH, 0xAD); // Flash Address High Byte -SFR(FCTL, 0xAE); // Flash Control -SFR(FWDATA, 0xAF); // Flash Write Data -SFR(ENCDI, 0xB1); // Encryption Input Data -SFR(ENCDO, 0xB2); // Encryption Output Data -SFR(ENCCS, 0xB3); // Encryption Control and Status -SFR(ADCCON1, 0xB4); // ADC Control 1 -SFR(ADCCON2, 0xB5); // ADC Control 2 -SFR(ADCCON3, 0xB6); // ADC Control 3 -SFR(IEN1, 0xB8); // Interrupt Enable 1 - SBIT(DMAIE, 0xB8, 0); // DMA Transfer Interrupt Enable - SBIT(T1IE, 0xB8, 1); // Timer 1 Interrupt Enable - SBIT(T2IE, 0xB8, 2); // Timer 2 Interrupt Enable - SBIT(T3IE, 0xB8, 3); // Timer 3 Interrupt Enable - SBIT(T4IE, 0xB8, 4); // Timer 4 Interrupt Enable - SBIT(P0IE, 0xB8, 5); // Port 0 Interrupt Enable -SFR(IP1, 0xB9); // Interrupt Priority 1 -SFR(ADCL, 0xBA); // ADC Data Low -SFR(ADCH, 0xBB); // ADC Data High -SFR(RNDL, 0xBC); // Random Number Generator Data Low Byte -SFR(RNDH, 0xBD); // Random Number Generator Data High Byte -SFR(SLEEP, 0xBE); // Sleep Mode Control -SFR(IRCON, 0xC0); // Interrupt Flags 4 - SBIT(DMAIF, 0xC0, 0); // DMA Complete Interrupt Flag - SBIT(T1IF, 0xC0, 1); // Timer 1 Interrupt Flag - SBIT(T2IF, 0xC0, 2); // Timer 2 Interrupt Flag - SBIT(T3IF, 0xC0, 3); // Timer 3 Interrupt Flag - SBIT(T4IF, 0xC0, 4); // Timer 4 Interrupt Flag - SBIT(P0IF, 0xC0, 5); // Port 0 Interrupt Flag - SBIT(STIF, 0xC0, 7); // Sleep Timer Interrupt Flag -SFR(U0DBUF, 0xC1); // USART 0 Receive/Transmit Data Buffer -SFR(U0BAUD, 0xC2); // USART 0 Baud Rate Control -SFR(T2CNF, 0xC3); // Timer 2 Configuration -SFR(U0UCR, 0xC4); // USART 0 UART Control -SFR(U0GCR, 0xC5); // USART 0 Generic Control -SFR(CLKCON, 0xC6); // Clock Control -SFR(MEMCTR, 0xC7); // Memory Arbiter Control -SFR(WDCTL, 0xC9); // Watchdog Timer Control -SFR(T3CNT, 0xCA); // Timer 3 Counter -SFR(T3CTL, 0xCB); // Timer 3 Control -SFR(T3CCTL0, 0xCC); // Timer 3 Channel 0 Capture/Compare Control -SFR(T3CC0, 0xCD); // Timer 3 Channel 0 Capture/Compare Value -SFR(T3CCTL1, 0xCE); // Timer 3 Channel 1 Capture/Compare Control -SFR(T3CC1, 0xCF); // Timer 3 Channel 1 Capture/Compare Value -SFR(PSW, 0xD0); // Program Status Word - SBIT(P, 0xD0, 0); // Parity Flag - SBIT(F1, 0xD0, 1); // User-Defined Flag - SBIT(OV, 0xD0, 2); // Overflow Flag - SBIT(RS0, 0xD0, 3); // Register Bank Select 0 - SBIT(RS1, 0xD0, 4); // Register Bank Select 1 - SBIT(F0, 0xD0, 5); // User-Defined Flag - SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag - SBIT(CY, 0xD0, 7); // Carry Flag -SFR(DMAIRQ, 0xD1); // DMA Interrupt Flag -SFR(DMA1CFGL, 0xD2); // DMA Channel 1-4 Configuration Address Low Byte -SFR(DMA1CFGH, 0xD3); // DMA Channel 1-4 Configuration Address High Byte -SFR(DMA0CFGL, 0xD4); // DMA Channel 0 Configuration Address Low Byte -SFR(DMA0CFGH, 0xD5); // DMA Channel 0 Configuration Address High Byte -SFR(DMAARM, 0xD6); // DMA Channel Arm -SFR(DMAREQ, 0xD7); // DMA Channel Start Request and Status -SFR(TIMIF, 0xD8); // Timers 1/3/4 Interrupt Mask/Flag - SBIT(T3OVFIF, 0xD8, 0); // Timer 3 overflow interrupt flag 0:no pending 1:pending - SBIT(T3CH0IF, 0xD8, 1); // Timer 3 channel 0 interrupt flag 0:no pending 1:pending - SBIT(T3CH1IF, 0xD8, 2); // Timer 3 channel 1 interrupt flag 0:no pending 1:pending - SBIT(T4OVFIF, 0xD8, 3); // Timer 4 overflow interrupt flag 0:no pending 1:pending - SBIT(T4CH0IF, 0xD8, 4); // Timer 4 channel 0 interrupt flag 0:no pending 1:pending - SBIT(T4CH1IF, 0xD8, 5); // Timer 4 channel 1 interrupt flag 0:no pending 1:pending - SBIT(OVFIM, 0xD8, 6); // Timer 1 overflow interrupt mask -SFR(RFD, 0xD9); // RF Data -SFR(T1CC0L, 0xDA); // Timer 1 Channel 0 Capture/Compare Value Low -SFR(T1CC0H, 0xDB); // Timer 1 Channel 0 Capture/Compare Value High -SFR(T1CC1L, 0xDC); // Timer 1 Channel 1 Capture/Compare Value Low -SFR(T1CC1H, 0xDD); // Timer 1 Channel 1 Capture/Compare Value High -SFR(T1CC2L, 0xDE); // Timer 1 Channel 2 Capture/Compare Value Low -SFR(T1CC2H, 0xDF); // Timer 1 Channel 2 Capture/Compare Value High -SFR(ACC, 0xE0); // Accumulator - SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0 - SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1 - SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2 - SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3 - SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4 - SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5 - SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6 - SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7 -SFR(RFST, 0xE1); // RF CSMA-CA / Strobe Processor -SFR(T1CNTL, 0xE2); // Timer 1 Counter Low -SFR(T1CNTH, 0xE3); // Timer 1 Counter High -SFR(T1CTL, 0xE4); // Timer 1 Control and Status -SFR(T1CCTL0, 0xE5); // Timer 1 Channel 0 Capture/Compare Control -SFR(T1CCTL1, 0xE6); // Timer 1 Channel 1 Capture/Compare Control -SFR(T1CCTL2, 0xE7); // Timer 1 Channel 2 Capture/Compare Control -SFR(IRCON2, 0xE8); // Interrupt Flags 5 - SBIT(P2IF, 0xE8, 0); // Port 2 Interrupt Flag - SBIT(UTX0IF, 0xE8, 1); // USART0 TX Interrupt Flag - SBIT(UTX1IF, 0xE8, 2); // USART1 TX Interrupt Flag - SBIT(P1IF, 0xE8, 3); // Port 1 Interrupt Flag - SBIT(WDTIF, 0xE8, 4); // Watchdog Timer Interrupt Flag -SFR(RFIF, 0xE9); // RF Interrupt Flags -SFR(T4CNT, 0xEA); // Timer 4 Counter -SFR(T4CTL, 0xEB); // Timer 4 Control -SFR(T4CCTL0, 0xEC); // Timer 4 Channel 0 Capture/Compare Control -SFR(T4CC0, 0xED); // Timer 4 Channel 0 Capture/Compare Value -SFR(T4CCTL1, 0xEE); // Timer 4 Channel 1 Capture/Compare Control -SFR(T4CC1, 0xEF); // Timer 4 Channel 1 Capture/Compare Value -SFR(B, 0xF0); // B Register - SBIT(B_0, 0xF0, 0); // Register B bit 0 - SBIT(B_1, 0xF0, 1); // Register B bit 1 - SBIT(B_2, 0xF0, 2); // Register B bit 2 - SBIT(B_3, 0xF0, 3); // Register B bit 3 - SBIT(B_4, 0xF0, 4); // Register B bit 4 - SBIT(B_5, 0xF0, 5); // Register B bit 5 - SBIT(B_6, 0xF0, 6); // Register B bit 6 - SBIT(B_7, 0xF0, 7); // Register B bit 7 -SFR(PERCFG, 0xF1); // Peripheral Control -SFR(ADCCFG, 0xF2); // ADC Input Configuration -SFR(P0SEL, 0xF3); // Port 0 Function Select -SFR(P1SEL, 0xF4); // Port 1 Function Select -SFR(P2SEL, 0xF5); // Port 2 Function Select -SFR(P1INP, 0xF6); // Port 1 Input Mode -SFR(P2INP, 0xF7); // Port 2 Input Mode -SFR(U1CSR, 0xF8); // USART 1 Control and Status - SBIT(ACTIVE, 0xF8, 0); // USART transmit/receive active status 0:idle 1:busy - SBIT(TX_BYTE, 0xF8, 1); // Transmit byte status 0:Byte not transmitted 1:Last byte transmitted - SBIT(RX_BYTE, 0xF8, 2); // Receive byte status 0:No byte received 1:Received byte ready - SBIT(ERR, 0xF8, 3); // UART parity error status 0:No error 1:parity error - SBIT(FE, 0xF8, 4); // UART framing error status 0:No error 1:incorrect stop bit level - SBIT(SLAVE, 0xF8, 5); // SPI master or slave mode select 0:master 1:slave - SBIT(RE, 0xF8, 6); // UART receiver enable 0:disabled 1:enabled - SBIT(MODE, 0xF8, 7); // USART mode select 0:SPI 1:UART -SFR(U1DBUF, 0xF9); // USART 1 Receive/Transmit Data Buffer -SFR(U1BAUD, 0xFA); // USART 1 Baud Rate Control -SFR(U1UCR, 0xFB); // USART 1 UART Control -SFR(U1GCR, 0xFC); // USART 1 Generic Control -SFR(P0DIR, 0xFD); // Port 0 Direction -SFR(P1DIR, 0xFE); // Port 1 Direction -SFR(P2DIR, 0xFF); // Port 2 Direction - -// From Table 45 : Overview of RF registers - -SFRX(MDMCTRL0H, 0xDF02); // Modem Control 0, high -SFRX(MDMCTRL0L, 0xDF03); // Modem Control 0, low -SFRX(MDMCTRL1H, 0xDF04); // Modem Control 1, high -SFRX(MDMCTRL1L, 0xDF05); // Modem Control 1, low -SFRX(RSSIH, 0xDF06); // RSSI and CCA Status and Control, high -SFRX(RSSIL, 0xDF07); // RSSI and CCA Status and Control, low -SFRX(SYNCWORDH, 0xDF08); // Synchronisation Word Control, high -SFRX(SYNCWORDL, 0xDF09); // Synchronisation Word Control, low -SFRX(TXCTRLH, 0xDF0A); // Transmit Control, high -SFRX(TXCTRLL, 0xDF0B); // Transmit Control, low -SFRX(RXCTRL0H, 0xDF0C); // Receive Control 0, high -SFRX(RXCTRL0L, 0xDF0D); // Receive Control 0, low -SFRX(RXCTRL1H, 0xDF0E); // Receive Control 1, high -SFRX(RXCTRL1L, 0xDF0F); // Receive Control 1, low -SFRX(FSCTRLH, 0xDF10); // Frequency Synthesizer Control and Status, high -SFRX(FSCTRLL, 0xDF11); // Frequency Synthesizer Control and Status, low -SFRX(CSPX, 0xDF12); // CSP X Data -SFRX(CSPY, 0xDF13); // CSP Y Data -SFRX(CSPZ, 0xDF14); // CSP Z Data -SFRX(CSPCTRL, 0xDF15); // CSP Control -SFRX(CSPT, 0xDF16); // CSP T Data -SFRX(RFPWR, 0xDF17); // RF Power Control -SFRX(FSMTCH, 0xDF20); // Finite State Machine Time Constants, high -SFRX(FSMTCL, 0xDF21); // Finite State Machine Time Constants, low -SFRX(MANANDH, 0xDF22); // Manual AND Override, high -SFRX(MANANDL, 0xDF23); // Manual AND Override, low -SFRX(MANORH, 0xDF24); // Manual OR Override, high -SFRX(MANORL, 0xDF25); // Manual OR Override, low -SFRX(AGCCTRLH, 0xDF26); // AGC Control, high -SFRX(AGCCTRLL, 0xDF27); // AGC Control, low -SFRX(FSMSTATE, 0xDF39); // Finite State Machine State Status -SFRX(ADCTSTH, 0xDF3A); // ADC Test, high -SFRX(ADCTSTL, 0xDF3B); // ADC Test, low -SFRX(DACTSTH, 0xDF3C); // DAC Test, high -SFRX(DACTSTL, 0xDF3D); // DAC Test, low -SFRX(IEEE_ADDR0, 0xDF43); // IEEE Address 0 -SFRX(IEEE_ADDR1, 0xDF44); // IEEE Address 1 -SFRX(IEEE_ADDR2, 0xDF45); // IEEE Address 2 -SFRX(IEEE_ADDR3, 0xDF46); // IEEE Address 3 -SFRX(IEEE_ADDR4, 0xDF47); // IEEE Address 4 -SFRX(IEEE_ADDR5, 0xDF48); // IEEE Address 5 -SFRX(IEEE_ADDR6, 0xDF49); // IEEE Address 6 -SFRX(IEEE_ADDR7, 0xDF4A); // IEEE Address 7 -SFRX(PANIDH, 0xDF4B); // PAN Identifier, high -SFRX(PANIDL, 0xDF4C); // PAN Identifier, low -SFRX(SHORTADDRH, 0xDF4D); // Short Address, high -SFRX(SHORTADDRL, 0xDF4E); // Short Address, low -SFRX(IOCFG0, 0xDF4F); // I/O Configuration 0 -SFRX(IOCFG1, 0xDF50); // I/O Configuration 1 -SFRX(IOCFG2, 0xDF51); // I/O Configuration 2 -SFRX(IOCFG3, 0xDF52); // I/O Configuration 3 -SFRX(RXFIFOCNT, 0xDF53); // RX FIFO Count -SFRX(FSMTC1, 0xDF54); // Finite State Machine Control -SFRX(CHVER, 0xDF60); // Chip Version -SFRX(CHIPID, 0xDF61); // Chip Identification -SFRX(RFSTATUS, 0xDF62); // RF Status - -// SFRs also accesible through XDATA space - -SFRX(X_U0CSR, 0xDF86); // USART 0 Control and Status -SFRX(X_P0IFG, 0xDF89); // Port 0 Interrupt Status Flag -SFRX(X_P1IFG, 0xDF8A); // Port 1 Interrupt Status Flag -SFRX(X_P2IFG, 0xDF8B); // Port 2 Interrupt Status Flag -SFRX(X_PICTL, 0xDF8C); // Port Interrupt Control -SFRX(X_P1IEN, 0xDF8D); // Port 1 Interrupt Mask -SFRX(X_P0INP, 0xDF8F); // Port 0 Input Mode -SFRX(X_RFIM, 0xDF91); // RF Interrupt Mask -SFRX(X_MPAGE, 0xDF93); // Memory Page Select -SFRX(X_T2CMP, 0xDF94); // Timer 2 Compare Value -SFRX(X_ST0, 0xDF95); // Sleep Timer 0 -SFRX(X_ST1, 0xDF96); // Sleep Timer 1 -SFRX(X_ST2, 0xDF97); // Sleep Timer 2 -SFRX(X_T2PEROF0, 0xDF9C); // Timer 2 Overflow Capture/Compare 0 -SFRX(X_T2PEROF1, 0xDF9D); // Timer 2 Overflow Capture/Compare 1 -SFRX(X_T2PEROF2, 0xDF9E); // Timer 2 Overflow Capture/Compare 2 -SFRX(X_T2OF0, 0xDFA1); // Timer 2 Overflow Count 0 -SFRX(X_T2OF1, 0xDFA2); // Timer 2 Overflow Count 1 -SFRX(X_T2OF2, 0xDFA3); // Timer 2 Overflow Count 2 -SFRX(X_T2CAPLPL, 0xDFA4); // Timer 2 Period Low Byte -SFRX(X_T2CAPHPH, 0xDFA5); // Timer 2 Period High Byte -SFRX(X_T2TLD, 0xDFA6); // Timer 2 Timer Value Low Byte -SFRX(X_T2THD, 0xDFA7); // Timer 2 Timer Value High Byte -SFRX(X_FWT, 0xDFAB); // Flash Write Timing -SFRX(X_FADDRL, 0xDFAC); // Flash Address Low Byte -SFRX(X_FADDRH, 0xDFAD); // Flash Address High Byte -SFRX(X_FCTL, 0xDFAE); // Flash Control -SFRX(X_FWDATA, 0xDFAF); // Flash Write Data -SFRX(X_ENCDI, 0xDFB1); // Encryption Input Data -SFRX(X_ENCDO, 0xDFB2); // Encryption Output Data -SFRX(X_ENCCS, 0xDFB3); // Encryption Control and Status -SFRX(X_ADCCON1, 0xDFB4); // ADC Control 1 -SFRX(X_ADCCON2, 0xDFB5); // ADC Control 2 -SFRX(X_ADCCON3, 0xDFB6); // ADC Control 3 -SFRX(X_ADCL, 0xDFBA); // ADC Data Low -SFRX(X_ADCH, 0xDFBB); // ADC Data High -SFRX(X_RNDL, 0xDFBC); // Random Number Generator Data Low Byte -SFRX(X_RNDH, 0xDFBD); // Random Number Generator Data High Byte -SFRX(X_SLEEP, 0xDFBE); // Sleep Mode Control -SFRX(X_U0DBUF, 0xDFC1); // USART 0 Receive/Transmit Data Buffer -SFRX(X_U0BAUD, 0xDFC2); // USART 0 Baud Rate Control -SFRX(X_T2CNF, 0xDFC3); // Timer 2 Configuration -SFRX(X_U0UCR, 0xDFC4); // USART 0 UART Control -SFRX(X_U0GCR, 0xDFC5); // USART 0 Generic Control -SFRX(X_CLKCON, 0xDFC6); // Clock Control -SFRX(X_MEMCTR, 0xDFC7); // Memory Arbiter Control -SFRX(X_WDCTL, 0xDFC9); // Watchdog Timer Control -SFRX(X_T3CNT, 0xDFCA); // Timer 3 Counter -SFRX(X_T3CTL, 0xDFCB); // Timer 3 Control -SFRX(X_T3CCTL0, 0xDFCC); // Timer 3 Channel 0 Capture/Compare Control -SFRX(X_T3CC0, 0xDFCD); // Timer 3 Channel 0 Capture/Compare Value -SFRX(X_T3CCTL1, 0xDFCE); // Timer 3 Channel 1 Capture/Compare Control -SFRX(X_T3CC1, 0xDFCF); // Timer 3 Channel 1 Capture/Compare Value -SFRX(X_DMAIRQ, 0xDFD1); // DMA Interrupt Flag -SFRX(X_DMA1CFGL, 0xDFD2); // DMA Channel 1-4 Configuration Address Low Byte -SFRX(X_DMA1CFGH, 0xDFD3); // DMA Channel 1-4 Configuration Address High Byte -SFRX(X_DMA0CFGL, 0xDFD4); // DMA Channel 0 Configuration Address Low Byte -SFRX(X_DMA0CFGH, 0xDFD5); // DMA Channel 0 Configuration Address High Byte -SFRX(X_DMAARM, 0xDFD6); // DMA Channel Arm -SFRX(X_DMAREQ, 0xDFD7); // DMA Channel Start Request and Status -SFRX(X_TIMIF, 0xDFD8); // Timers 1/3/4 Interrupt Mask/Flag -SFRX(X_RFD, 0xDFD9); // RF Data -SFRX(X_T1CC0L, 0xDFDA); // Timer 1 Channel 0 Capture/Compare Value Low -SFRX(X_T1CC0H, 0xDFDB); // Timer 1 Channel 0 Capture/Compare Value High -SFRX(X_T1CC1L, 0xDFDC); // Timer 1 Channel 1 Capture/Compare Value Low -SFRX(X_T1CC1H, 0xDFDD); // Timer 1 Channel 1 Capture/Compare Value High -SFRX(X_T1CC2L, 0xDFDE); // Timer 1 Channel 2 Capture/Compare Value Low -SFRX(X_T1CC2H, 0xDFDF); // Timer 1 Channel 2 Capture/Compare Value High -SFRX(X_RFST, 0xDFE1); // RF CSMA-CA / Strobe Processor -SFRX(X_T1CNTL, 0xDFE2); // Timer 1 Counter Low -SFRX(X_T1CNTH, 0xDFE3); // Timer 1 Counter High -SFRX(X_T1CTL, 0xDFE4); // Timer 1 Control and Status -SFRX(X_T1CCTL0, 0xDFE5); // Timer 1 Channel 0 Capture/Compare Control -SFRX(X_T1CCTL1, 0xDFE6); // Timer 1 Channel 1 Capture/Compare Control -SFRX(X_T1CCTL2, 0xDFE7); // Timer 1 Channel 2 Capture/Compare Control -SFRX(X_RFIF, 0xDFE9); // RF Interrupt Flags -SFRX(X_T4CNT, 0xDFEA); // Timer 4 Counter -SFRX(X_T4CTL, 0xDFEB); // Timer 4 Control -SFRX(X_T4CCTL0, 0xDFEC); // Timer 4 Channel 0 Capture/Compare Control -SFRX(X_T4CC0, 0xDFED); // Timer 4 Channel 0 Capture/Compare Value -SFRX(X_T4CCTL1, 0xDFEE); // Timer 4 Channel 1 Capture/Compare Control -SFRX(X_T4CC1, 0xDFEF); // Timer 4 Channel 1 Capture/Compare Value -SFRX(X_PERCFG, 0xDFF1); // Peripheral Control -SFRX(X_ADCCFG, 0xDFF2); // ADC Input Configuration -SFRX(X_P0SEL, 0xDFF3); // Port 0 Function Select -SFRX(X_P1SEL, 0xDFF4); // Port 1 Function Select -SFRX(X_P2SEL, 0xDFF5); // Port 2 Function Select -SFRX(X_P1INP, 0xDFF6); // Port 1 Input Mode -SFRX(X_P2INP, 0xDFF7); // Port 2 Input Mode -SFRX(X_U1CSR, 0xDFF8); // USART 1 Control and Status -SFRX(X_U1DBUF, 0xDFF9); // USART 1 Receive/Transmit Data Buffer -SFRX(X_U1BAUD, 0xDFFA); // USART 1 Baud Rate Control -SFRX(X_U1UCR, 0xDFFB); // USART 1 UART Control -SFRX(X_U1GCR, 0xDFFC); // USART 1 Generic Control -SFRX(X_P0DIR, 0xDFFD); // Port 0 Direction -SFRX(X_P1DIR, 0xDFFE); // Port 1 Direction -SFRX(X_P2DIR, 0xDFFF); // Port 2 Direction - -#endif //REG_CC2430_H +/*------------------------------------------------------------------------- + Register Declarations for Chipcon CC2430 + + Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (December 2006) + (Based on CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A) + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + In other words, you are welcome to use, share and improve this program. + You are forbidden to forbid anyone else to use, share and improve + what you give them. Help stamp out software-hoarding! +-------------------------------------------------------------------------*/ + +#ifndef REG_CC2430_H +#define REG_CC2430_H + +#include + +// Interrupt Vectors + +#define RFERR_VECTOR 0 // RF TX FIFO underflow and RX FIFO overflow. +#define ADC_VECTOR 1 // ADC end of conversion +#define URX0_VECTOR 2 // USART0 RX complete +#define URX1_VECTOR 3 // USART1 RX complete +#define ENC_VECTOR 4 // AES encryption/decryption complete +#define ST_VECTOR 5 // Sleep Timer compare +#define P2INT_VECTOR 6 // Port 2 inputs +#define UTX0_VECTOR 7 // USART0 TX complete +#define DMA_VECTOR 8 // DMA transfer complete +#define T1_VECTOR 9 // Timer 1 (16-bit) capture/compare/overflow +#define T2_VECTOR 10 // Timer 2 (MAC Timer) +#define T3_VECTOR 11 // Timer 3 (8-bit) capture/compare/overflow +#define T4_VECTOR 12 // Timer 4 (8-bit) capture/compare/overflow +#define P0INT_VECTOR 13 // Port 0 inputs +#define UTX1_VECTOR 14 // USART1 TX complete +#define P1INT_VECTOR 15 // Port 1 inputs +#define RF_VECTOR 16 // RF general interrupts +#define WDT_VECTOR 17 // Watchdog overflow in timer mode + +// SFR Registers and BITs + +SFR(P0, 0x80); // Port 0 + SBIT(P0_0, 0x80, 0); // Port 0 bit 0 + SBIT(P0_1, 0x80, 1); // Port 0 bit 1 + SBIT(P0_2, 0x80, 2); // Port 0 bit 2 + SBIT(P0_3, 0x80, 3); // Port 0 bit 3 + SBIT(P0_4, 0x80, 4); // Port 0 bit 4 + SBIT(P0_5, 0x80, 5); // Port 0 bit 5 + SBIT(P0_6, 0x80, 6); // Port 0 bit 6 + SBIT(P0_7, 0x80, 7); // Port 0 bit 7 +SFR(SP, 0x81); // Stack Pointer +SFR(DPL0, 0x82); // Data Pointer 0 Low Byte +SFR(DPH0, 0x83); // Data Pointer 0 High Byte +SFR(DPL1, 0x84); // Data Pointer 1 Low Byte +SFR(DPH1, 0x85); // Data Pointer 1 High Byte +SFR(U0CSR, 0x86); // USART 0 Control and Status +SFR(PCON, 0x87); // Power Mode Control +SFR(TCON, 0x88); // Interrupt Flags + SBIT(IT0, 0x88, 0); // reserved (must always be set to 1) + SBIT(RFERRIF, 0x88, 1); // RFERR – RF TX/RX FIFO interrupt flag + SBIT(IT1, 0x88, 2); // reserved (must always be set to 1) + SBIT(URX0IF, 0x88, 3); // USART0 RX Interrupt Flag + SBIT(ADCIF, 0x88, 5); // ADC Interrupt Flag + SBIT(URX1IF, 0x88, 7); // USART1 RX Interrupt Flag +SFR(P0IFG, 0x89); // Port 0 Interrupt Status Flag +SFR(P1IFG, 0x8A); // Port 1 Interrupt Status Flag +SFR(P2IFG, 0x8B); // Port 2 Interrupt Status Flag +SFR(PICTL, 0x8C); // Port Interrupt Control +SFR(P1IEN, 0x8D); // Port 1 Interrupt Mask +SFR(P0INP, 0x8F); // Port 0 Input Mode +SFR(P1, 0x90); // Port 1 + SBIT(P1_0, 0x90, 0); // Port 1 bit 0 + SBIT(P1_1, 0x90, 1); // Port 1 bit 1 + SBIT(P1_2, 0x90, 2); // Port 1 bit 2 + SBIT(P1_3, 0x90, 3); // Port 1 bit 3 + SBIT(P1_4, 0x90, 4); // Port 1 bit 4 + SBIT(P1_5, 0x90, 5); // Port 1 bit 5 + SBIT(P1_6, 0x90, 6); // Port 1 bit 6 + SBIT(P1_7, 0x90, 7); // Port 1 bit 7 +SFR(RFIM, 0x91); // RF Interrupt Mask +SFR(DPS, 0x92); // Data Pointer Select +SFR(MPAGE, 0x93); // Memory Page Select +SFR(_XPAGE, 0x93); // Memory Page Select under the name SDCC needs it +SFR(T2CMP, 0x94); // Timer 2 Compare Value +SFR(ST0, 0x95); // Sleep Timer 0 +SFR(ST1, 0x96); // Sleep Timer 1 +SFR(ST2, 0x97); // Sleep Timer 2 +SFR(S0CON, 0x98); // Interrupt Flags 2 + SBIT(ENCIF_0, 0x98, 0); // AES Interrupt Flag 0 + SBIT(ENCIF_1, 0x98, 1); // AES Interrupt Flag 1 +SFR(IEN2, 0x9A); // Interrupt Enable 2 +SFR(S1CON, 0x9B); // Interrupt Flags 3 +SFR(T2PEROF0, 0x9C); // Timer 2 Overflow Capture/Compare 0 +SFR(T2PEROF1, 0x9D); // Timer 2 Overflow Capture/Compare 1 +SFR(T2PEROF2, 0x9E); // Timer 2 Overflow Capture/Compare 2 +SFR(P2, 0xA0); // Port 2 + SBIT(P2_0, 0xA0, 0); // Port 2 bit 0 + SBIT(P2_1, 0xA0, 1); // Port 2 bit 1 + SBIT(P2_2, 0xA0, 2); // Port 2 bit 2 + SBIT(P2_3, 0xA0, 3); // Port 2 bit 3 + SBIT(P2_4, 0xA0, 4); // Port 2 bit 4 + SBIT(P2_5, 0xA0, 5); // Port 2 bit 5 + SBIT(P2_6, 0xA0, 6); // Port 2 bit 6 + SBIT(P2_7, 0xA0, 7); // Port 2 bit 7 +SFR(T2OF0, 0xA1); // Timer 2 Overflow Count 0 +SFR(T2OF1, 0xA2); // Timer 2 Overflow Count 1 +SFR(T2OF2, 0xA3); // Timer 2 Overflow Count 2 +SFR(T2CAPLPL, 0xA4); // Timer 2 Period Low Byte +SFR(T2CAPHPH, 0xA5); // Timer 2 Period High Byte +SFR(T2TLD, 0xA6); // Timer 2 Timer Value Low Byte +SFR(T2THD, 0xA7); // Timer 2 Timer Value High Byte +SFR(IEN0, 0xA8); // Interrupt Enable 0 + SBIT(RFERRIE, 0xA8, 0); // RF TX/RX FIFO interrupt enable + SBIT(ADCIE, 0xA8, 1); // ADC Interrupt Enable + SBIT(URX0IE, 0xA8, 2); // USART0 RX Interrupt Enable + SBIT(URX1IE, 0xA8, 3); // USART1 RX Interrupt Enable + SBIT(ENCIE, 0xA8, 4); // AES Encryption/Decryption Interrupt Enable + SBIT(STIE, 0xA8, 5); // Sleep Timer Interrupt Enable + SBIT(EA, 0xA8, 7); // Global Interrupt Enable +SFR(IP0, 0xA9); // Interrupt Priority 0 +SFR(FWT, 0xAB); // Flash Write Timing +SFR(FADDRL, 0xAC); // Flash Address Low Byte +SFR(FADDRH, 0xAD); // Flash Address High Byte +SFR(FCTL, 0xAE); // Flash Control +SFR(FWDATA, 0xAF); // Flash Write Data +SFR(ENCDI, 0xB1); // Encryption Input Data +SFR(ENCDO, 0xB2); // Encryption Output Data +SFR(ENCCS, 0xB3); // Encryption Control and Status +SFR(ADCCON1, 0xB4); // ADC Control 1 +SFR(ADCCON2, 0xB5); // ADC Control 2 +SFR(ADCCON3, 0xB6); // ADC Control 3 +SFR(IEN1, 0xB8); // Interrupt Enable 1 + SBIT(DMAIE, 0xB8, 0); // DMA Transfer Interrupt Enable + SBIT(T1IE, 0xB8, 1); // Timer 1 Interrupt Enable + SBIT(T2IE, 0xB8, 2); // Timer 2 Interrupt Enable + SBIT(T3IE, 0xB8, 3); // Timer 3 Interrupt Enable + SBIT(T4IE, 0xB8, 4); // Timer 4 Interrupt Enable + SBIT(P0IE, 0xB8, 5); // Port 0 Interrupt Enable +SFR(IP1, 0xB9); // Interrupt Priority 1 +SFR(ADCL, 0xBA); // ADC Data Low +SFR(ADCH, 0xBB); // ADC Data High +SFR(RNDL, 0xBC); // Random Number Generator Data Low Byte +SFR(RNDH, 0xBD); // Random Number Generator Data High Byte +SFR(SLEEP, 0xBE); // Sleep Mode Control +SFR(IRCON, 0xC0); // Interrupt Flags 4 + SBIT(DMAIF, 0xC0, 0); // DMA Complete Interrupt Flag + SBIT(T1IF, 0xC0, 1); // Timer 1 Interrupt Flag + SBIT(T2IF, 0xC0, 2); // Timer 2 Interrupt Flag + SBIT(T3IF, 0xC0, 3); // Timer 3 Interrupt Flag + SBIT(T4IF, 0xC0, 4); // Timer 4 Interrupt Flag + SBIT(P0IF, 0xC0, 5); // Port 0 Interrupt Flag + SBIT(STIF, 0xC0, 7); // Sleep Timer Interrupt Flag +SFR(U0DBUF, 0xC1); // USART 0 Receive/Transmit Data Buffer +SFR(U0BAUD, 0xC2); // USART 0 Baud Rate Control +SFR(T2CNF, 0xC3); // Timer 2 Configuration +SFR(U0UCR, 0xC4); // USART 0 UART Control +SFR(U0GCR, 0xC5); // USART 0 Generic Control +SFR(CLKCON, 0xC6); // Clock Control +SFR(MEMCTR, 0xC7); // Memory Arbiter Control +SFR(WDCTL, 0xC9); // Watchdog Timer Control +SFR(T3CNT, 0xCA); // Timer 3 Counter +SFR(T3CTL, 0xCB); // Timer 3 Control +SFR(T3CCTL0, 0xCC); // Timer 3 Channel 0 Capture/Compare Control +SFR(T3CC0, 0xCD); // Timer 3 Channel 0 Capture/Compare Value +SFR(T3CCTL1, 0xCE); // Timer 3 Channel 1 Capture/Compare Control +SFR(T3CC1, 0xCF); // Timer 3 Channel 1 Capture/Compare Value +SFR(PSW, 0xD0); // Program Status Word + SBIT(P, 0xD0, 0); // Parity Flag + SBIT(F1, 0xD0, 1); // User-Defined Flag + SBIT(OV, 0xD0, 2); // Overflow Flag + SBIT(RS0, 0xD0, 3); // Register Bank Select 0 + SBIT(RS1, 0xD0, 4); // Register Bank Select 1 + SBIT(F0, 0xD0, 5); // User-Defined Flag + SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag + SBIT(CY, 0xD0, 7); // Carry Flag +SFR(DMAIRQ, 0xD1); // DMA Interrupt Flag +SFR(DMA1CFGL, 0xD2); // DMA Channel 1-4 Configuration Address Low Byte +SFR(DMA1CFGH, 0xD3); // DMA Channel 1-4 Configuration Address High Byte +SFR(DMA0CFGL, 0xD4); // DMA Channel 0 Configuration Address Low Byte +SFR(DMA0CFGH, 0xD5); // DMA Channel 0 Configuration Address High Byte +SFR(DMAARM, 0xD6); // DMA Channel Arm +SFR(DMAREQ, 0xD7); // DMA Channel Start Request and Status +SFR(TIMIF, 0xD8); // Timers 1/3/4 Interrupt Mask/Flag + SBIT(T3OVFIF, 0xD8, 0); // Timer 3 overflow interrupt flag 0:no pending 1:pending + SBIT(T3CH0IF, 0xD8, 1); // Timer 3 channel 0 interrupt flag 0:no pending 1:pending + SBIT(T3CH1IF, 0xD8, 2); // Timer 3 channel 1 interrupt flag 0:no pending 1:pending + SBIT(T4OVFIF, 0xD8, 3); // Timer 4 overflow interrupt flag 0:no pending 1:pending + SBIT(T4CH0IF, 0xD8, 4); // Timer 4 channel 0 interrupt flag 0:no pending 1:pending + SBIT(T4CH1IF, 0xD8, 5); // Timer 4 channel 1 interrupt flag 0:no pending 1:pending + SBIT(OVFIM, 0xD8, 6); // Timer 1 overflow interrupt mask +SFR(RFD, 0xD9); // RF Data +SFR(T1CC0L, 0xDA); // Timer 1 Channel 0 Capture/Compare Value Low +SFR(T1CC0H, 0xDB); // Timer 1 Channel 0 Capture/Compare Value High +SFR(T1CC1L, 0xDC); // Timer 1 Channel 1 Capture/Compare Value Low +SFR(T1CC1H, 0xDD); // Timer 1 Channel 1 Capture/Compare Value High +SFR(T1CC2L, 0xDE); // Timer 1 Channel 2 Capture/Compare Value Low +SFR(T1CC2H, 0xDF); // Timer 1 Channel 2 Capture/Compare Value High +SFR(ACC, 0xE0); // Accumulator + SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0 + SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1 + SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2 + SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3 + SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4 + SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5 + SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6 + SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7 +SFR(RFST, 0xE1); // RF CSMA-CA / Strobe Processor +SFR(T1CNTL, 0xE2); // Timer 1 Counter Low +SFR(T1CNTH, 0xE3); // Timer 1 Counter High +SFR(T1CTL, 0xE4); // Timer 1 Control and Status +SFR(T1CCTL0, 0xE5); // Timer 1 Channel 0 Capture/Compare Control +SFR(T1CCTL1, 0xE6); // Timer 1 Channel 1 Capture/Compare Control +SFR(T1CCTL2, 0xE7); // Timer 1 Channel 2 Capture/Compare Control +SFR(IRCON2, 0xE8); // Interrupt Flags 5 + SBIT(P2IF, 0xE8, 0); // Port 2 Interrupt Flag + SBIT(UTX0IF, 0xE8, 1); // USART0 TX Interrupt Flag + SBIT(UTX1IF, 0xE8, 2); // USART1 TX Interrupt Flag + SBIT(P1IF, 0xE8, 3); // Port 1 Interrupt Flag + SBIT(WDTIF, 0xE8, 4); // Watchdog Timer Interrupt Flag +SFR(RFIF, 0xE9); // RF Interrupt Flags +SFR(T4CNT, 0xEA); // Timer 4 Counter +SFR(T4CTL, 0xEB); // Timer 4 Control +SFR(T4CCTL0, 0xEC); // Timer 4 Channel 0 Capture/Compare Control +SFR(T4CC0, 0xED); // Timer 4 Channel 0 Capture/Compare Value +SFR(T4CCTL1, 0xEE); // Timer 4 Channel 1 Capture/Compare Control +SFR(T4CC1, 0xEF); // Timer 4 Channel 1 Capture/Compare Value +SFR(B, 0xF0); // B Register + SBIT(B_0, 0xF0, 0); // Register B bit 0 + SBIT(B_1, 0xF0, 1); // Register B bit 1 + SBIT(B_2, 0xF0, 2); // Register B bit 2 + SBIT(B_3, 0xF0, 3); // Register B bit 3 + SBIT(B_4, 0xF0, 4); // Register B bit 4 + SBIT(B_5, 0xF0, 5); // Register B bit 5 + SBIT(B_6, 0xF0, 6); // Register B bit 6 + SBIT(B_7, 0xF0, 7); // Register B bit 7 +SFR(PERCFG, 0xF1); // Peripheral Control +SFR(ADCCFG, 0xF2); // ADC Input Configuration +SFR(P0SEL, 0xF3); // Port 0 Function Select +SFR(P1SEL, 0xF4); // Port 1 Function Select +SFR(P2SEL, 0xF5); // Port 2 Function Select +SFR(P1INP, 0xF6); // Port 1 Input Mode +SFR(P2INP, 0xF7); // Port 2 Input Mode +SFR(U1CSR, 0xF8); // USART 1 Control and Status + SBIT(ACTIVE, 0xF8, 0); // USART transmit/receive active status 0:idle 1:busy + SBIT(TX_BYTE, 0xF8, 1); // Transmit byte status 0:Byte not transmitted 1:Last byte transmitted + SBIT(RX_BYTE, 0xF8, 2); // Receive byte status 0:No byte received 1:Received byte ready + SBIT(ERR, 0xF8, 3); // UART parity error status 0:No error 1:parity error + SBIT(FE, 0xF8, 4); // UART framing error status 0:No error 1:incorrect stop bit level + SBIT(SLAVE, 0xF8, 5); // SPI master or slave mode select 0:master 1:slave + SBIT(RE, 0xF8, 6); // UART receiver enable 0:disabled 1:enabled + SBIT(MODE, 0xF8, 7); // USART mode select 0:SPI 1:UART +SFR(U1DBUF, 0xF9); // USART 1 Receive/Transmit Data Buffer +SFR(U1BAUD, 0xFA); // USART 1 Baud Rate Control +SFR(U1UCR, 0xFB); // USART 1 UART Control +SFR(U1GCR, 0xFC); // USART 1 Generic Control +SFR(P0DIR, 0xFD); // Port 0 Direction +SFR(P1DIR, 0xFE); // Port 1 Direction +SFR(P2DIR, 0xFF); // Port 2 Direction + +// From Table 45 : Overview of RF registers + +SFRX(MDMCTRL0H, 0xDF02); // Modem Control 0, high +SFRX(MDMCTRL0L, 0xDF03); // Modem Control 0, low +SFRX(MDMCTRL1H, 0xDF04); // Modem Control 1, high +SFRX(MDMCTRL1L, 0xDF05); // Modem Control 1, low +SFRX(RSSIH, 0xDF06); // RSSI and CCA Status and Control, high +SFRX(RSSIL, 0xDF07); // RSSI and CCA Status and Control, low +SFRX(SYNCWORDH, 0xDF08); // Synchronisation Word Control, high +SFRX(SYNCWORDL, 0xDF09); // Synchronisation Word Control, low +SFRX(TXCTRLH, 0xDF0A); // Transmit Control, high +SFRX(TXCTRLL, 0xDF0B); // Transmit Control, low +SFRX(RXCTRL0H, 0xDF0C); // Receive Control 0, high +SFRX(RXCTRL0L, 0xDF0D); // Receive Control 0, low +SFRX(RXCTRL1H, 0xDF0E); // Receive Control 1, high +SFRX(RXCTRL1L, 0xDF0F); // Receive Control 1, low +SFRX(FSCTRLH, 0xDF10); // Frequency Synthesizer Control and Status, high +SFRX(FSCTRLL, 0xDF11); // Frequency Synthesizer Control and Status, low +SFRX(CSPX, 0xDF12); // CSP X Data +SFRX(CSPY, 0xDF13); // CSP Y Data +SFRX(CSPZ, 0xDF14); // CSP Z Data +SFRX(CSPCTRL, 0xDF15); // CSP Control +SFRX(CSPT, 0xDF16); // CSP T Data +SFRX(RFPWR, 0xDF17); // RF Power Control +SFRX(FSMTCH, 0xDF20); // Finite State Machine Time Constants, high +SFRX(FSMTCL, 0xDF21); // Finite State Machine Time Constants, low +SFRX(MANANDH, 0xDF22); // Manual AND Override, high +SFRX(MANANDL, 0xDF23); // Manual AND Override, low +SFRX(MANORH, 0xDF24); // Manual OR Override, high +SFRX(MANORL, 0xDF25); // Manual OR Override, low +SFRX(AGCCTRLH, 0xDF26); // AGC Control, high +SFRX(AGCCTRLL, 0xDF27); // AGC Control, low +SFRX(FSMSTATE, 0xDF39); // Finite State Machine State Status +SFRX(ADCTSTH, 0xDF3A); // ADC Test, high +SFRX(ADCTSTL, 0xDF3B); // ADC Test, low +SFRX(DACTSTH, 0xDF3C); // DAC Test, high +SFRX(DACTSTL, 0xDF3D); // DAC Test, low +SFRX(IEEE_ADDR0, 0xDF43); // IEEE Address 0 +SFRX(IEEE_ADDR1, 0xDF44); // IEEE Address 1 +SFRX(IEEE_ADDR2, 0xDF45); // IEEE Address 2 +SFRX(IEEE_ADDR3, 0xDF46); // IEEE Address 3 +SFRX(IEEE_ADDR4, 0xDF47); // IEEE Address 4 +SFRX(IEEE_ADDR5, 0xDF48); // IEEE Address 5 +SFRX(IEEE_ADDR6, 0xDF49); // IEEE Address 6 +SFRX(IEEE_ADDR7, 0xDF4A); // IEEE Address 7 +SFRX(PANIDH, 0xDF4B); // PAN Identifier, high +SFRX(PANIDL, 0xDF4C); // PAN Identifier, low +SFRX(SHORTADDRH, 0xDF4D); // Short Address, high +SFRX(SHORTADDRL, 0xDF4E); // Short Address, low +SFRX(IOCFG0, 0xDF4F); // I/O Configuration 0 +SFRX(IOCFG1, 0xDF50); // I/O Configuration 1 +SFRX(IOCFG2, 0xDF51); // I/O Configuration 2 +SFRX(IOCFG3, 0xDF52); // I/O Configuration 3 +SFRX(RXFIFOCNT, 0xDF53); // RX FIFO Count +SFRX(FSMTC1, 0xDF54); // Finite State Machine Control +SFRX(CHVER, 0xDF60); // Chip Version +SFRX(CHIPID, 0xDF61); // Chip Identification +SFRX(RFSTATUS, 0xDF62); // RF Status + +// SFRs also accesible through XDATA space + +SFRX(X_U0CSR, 0xDF86); // USART 0 Control and Status +SFRX(X_P0IFG, 0xDF89); // Port 0 Interrupt Status Flag +SFRX(X_P1IFG, 0xDF8A); // Port 1 Interrupt Status Flag +SFRX(X_P2IFG, 0xDF8B); // Port 2 Interrupt Status Flag +SFRX(X_PICTL, 0xDF8C); // Port Interrupt Control +SFRX(X_P1IEN, 0xDF8D); // Port 1 Interrupt Mask +SFRX(X_P0INP, 0xDF8F); // Port 0 Input Mode +SFRX(X_RFIM, 0xDF91); // RF Interrupt Mask +SFRX(X_MPAGE, 0xDF93); // Memory Page Select +SFRX(X_T2CMP, 0xDF94); // Timer 2 Compare Value +SFRX(X_ST0, 0xDF95); // Sleep Timer 0 +SFRX(X_ST1, 0xDF96); // Sleep Timer 1 +SFRX(X_ST2, 0xDF97); // Sleep Timer 2 +SFRX(X_T2PEROF0, 0xDF9C); // Timer 2 Overflow Capture/Compare 0 +SFRX(X_T2PEROF1, 0xDF9D); // Timer 2 Overflow Capture/Compare 1 +SFRX(X_T2PEROF2, 0xDF9E); // Timer 2 Overflow Capture/Compare 2 +SFRX(X_T2OF0, 0xDFA1); // Timer 2 Overflow Count 0 +SFRX(X_T2OF1, 0xDFA2); // Timer 2 Overflow Count 1 +SFRX(X_T2OF2, 0xDFA3); // Timer 2 Overflow Count 2 +SFRX(X_T2CAPLPL, 0xDFA4); // Timer 2 Period Low Byte +SFRX(X_T2CAPHPH, 0xDFA5); // Timer 2 Period High Byte +SFRX(X_T2TLD, 0xDFA6); // Timer 2 Timer Value Low Byte +SFRX(X_T2THD, 0xDFA7); // Timer 2 Timer Value High Byte +SFRX(X_FWT, 0xDFAB); // Flash Write Timing +SFRX(X_FADDRL, 0xDFAC); // Flash Address Low Byte +SFRX(X_FADDRH, 0xDFAD); // Flash Address High Byte +SFRX(X_FCTL, 0xDFAE); // Flash Control +SFRX(X_FWDATA, 0xDFAF); // Flash Write Data +SFRX(X_ENCDI, 0xDFB1); // Encryption Input Data +SFRX(X_ENCDO, 0xDFB2); // Encryption Output Data +SFRX(X_ENCCS, 0xDFB3); // Encryption Control and Status +SFRX(X_ADCCON1, 0xDFB4); // ADC Control 1 +SFRX(X_ADCCON2, 0xDFB5); // ADC Control 2 +SFRX(X_ADCCON3, 0xDFB6); // ADC Control 3 +SFRX(X_ADCL, 0xDFBA); // ADC Data Low +SFRX(X_ADCH, 0xDFBB); // ADC Data High +SFRX(X_RNDL, 0xDFBC); // Random Number Generator Data Low Byte +SFRX(X_RNDH, 0xDFBD); // Random Number Generator Data High Byte +SFRX(X_SLEEP, 0xDFBE); // Sleep Mode Control +SFRX(X_U0DBUF, 0xDFC1); // USART 0 Receive/Transmit Data Buffer +SFRX(X_U0BAUD, 0xDFC2); // USART 0 Baud Rate Control +SFRX(X_T2CNF, 0xDFC3); // Timer 2 Configuration +SFRX(X_U0UCR, 0xDFC4); // USART 0 UART Control +SFRX(X_U0GCR, 0xDFC5); // USART 0 Generic Control +SFRX(X_CLKCON, 0xDFC6); // Clock Control +SFRX(X_MEMCTR, 0xDFC7); // Memory Arbiter Control +SFRX(X_WDCTL, 0xDFC9); // Watchdog Timer Control +SFRX(X_T3CNT, 0xDFCA); // Timer 3 Counter +SFRX(X_T3CTL, 0xDFCB); // Timer 3 Control +SFRX(X_T3CCTL0, 0xDFCC); // Timer 3 Channel 0 Capture/Compare Control +SFRX(X_T3CC0, 0xDFCD); // Timer 3 Channel 0 Capture/Compare Value +SFRX(X_T3CCTL1, 0xDFCE); // Timer 3 Channel 1 Capture/Compare Control +SFRX(X_T3CC1, 0xDFCF); // Timer 3 Channel 1 Capture/Compare Value +SFRX(X_DMAIRQ, 0xDFD1); // DMA Interrupt Flag +SFRX(X_DMA1CFGL, 0xDFD2); // DMA Channel 1-4 Configuration Address Low Byte +SFRX(X_DMA1CFGH, 0xDFD3); // DMA Channel 1-4 Configuration Address High Byte +SFRX(X_DMA0CFGL, 0xDFD4); // DMA Channel 0 Configuration Address Low Byte +SFRX(X_DMA0CFGH, 0xDFD5); // DMA Channel 0 Configuration Address High Byte +SFRX(X_DMAARM, 0xDFD6); // DMA Channel Arm +SFRX(X_DMAREQ, 0xDFD7); // DMA Channel Start Request and Status +SFRX(X_TIMIF, 0xDFD8); // Timers 1/3/4 Interrupt Mask/Flag +SFRX(X_RFD, 0xDFD9); // RF Data +SFRX(X_T1CC0L, 0xDFDA); // Timer 1 Channel 0 Capture/Compare Value Low +SFRX(X_T1CC0H, 0xDFDB); // Timer 1 Channel 0 Capture/Compare Value High +SFRX(X_T1CC1L, 0xDFDC); // Timer 1 Channel 1 Capture/Compare Value Low +SFRX(X_T1CC1H, 0xDFDD); // Timer 1 Channel 1 Capture/Compare Value High +SFRX(X_T1CC2L, 0xDFDE); // Timer 1 Channel 2 Capture/Compare Value Low +SFRX(X_T1CC2H, 0xDFDF); // Timer 1 Channel 2 Capture/Compare Value High +SFRX(X_RFST, 0xDFE1); // RF CSMA-CA / Strobe Processor +SFRX(X_T1CNTL, 0xDFE2); // Timer 1 Counter Low +SFRX(X_T1CNTH, 0xDFE3); // Timer 1 Counter High +SFRX(X_T1CTL, 0xDFE4); // Timer 1 Control and Status +SFRX(X_T1CCTL0, 0xDFE5); // Timer 1 Channel 0 Capture/Compare Control +SFRX(X_T1CCTL1, 0xDFE6); // Timer 1 Channel 1 Capture/Compare Control +SFRX(X_T1CCTL2, 0xDFE7); // Timer 1 Channel 2 Capture/Compare Control +SFRX(X_RFIF, 0xDFE9); // RF Interrupt Flags +SFRX(X_T4CNT, 0xDFEA); // Timer 4 Counter +SFRX(X_T4CTL, 0xDFEB); // Timer 4 Control +SFRX(X_T4CCTL0, 0xDFEC); // Timer 4 Channel 0 Capture/Compare Control +SFRX(X_T4CC0, 0xDFED); // Timer 4 Channel 0 Capture/Compare Value +SFRX(X_T4CCTL1, 0xDFEE); // Timer 4 Channel 1 Capture/Compare Control +SFRX(X_T4CC1, 0xDFEF); // Timer 4 Channel 1 Capture/Compare Value +SFRX(X_PERCFG, 0xDFF1); // Peripheral Control +SFRX(X_ADCCFG, 0xDFF2); // ADC Input Configuration +SFRX(X_P0SEL, 0xDFF3); // Port 0 Function Select +SFRX(X_P1SEL, 0xDFF4); // Port 1 Function Select +SFRX(X_P2SEL, 0xDFF5); // Port 2 Function Select +SFRX(X_P1INP, 0xDFF6); // Port 1 Input Mode +SFRX(X_P2INP, 0xDFF7); // Port 2 Input Mode +SFRX(X_U1CSR, 0xDFF8); // USART 1 Control and Status +SFRX(X_U1DBUF, 0xDFF9); // USART 1 Receive/Transmit Data Buffer +SFRX(X_U1BAUD, 0xDFFA); // USART 1 Baud Rate Control +SFRX(X_U1UCR, 0xDFFB); // USART 1 UART Control +SFRX(X_U1GCR, 0xDFFC); // USART 1 Generic Control +SFRX(X_P0DIR, 0xDFFD); // Port 0 Direction +SFRX(X_P1DIR, 0xDFFE); // Port 1 Direction +SFRX(X_P2DIR, 0xDFFF); // Port 2 Direction + +#endif //REG_CC2430_H diff --git a/device/include/mcs51/cc2510fx.h b/device/include/mcs51/cc2510fx.h index 8c56c0fb..04de283d 100644 --- a/device/include/mcs51/cc2510fx.h +++ b/device/include/mcs51/cc2510fx.h @@ -1,472 +1,472 @@ -/*------------------------------------------------------------------------- - Register Declarations for Chipcon CC2510Fx/CC2511Fx - - Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (August 2006) - (Based on CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A) - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - In other words, you are welcome to use, share and improve this program. - You are forbidden to forbid anyone else to use, share and improve - what you give them. Help stamp out software-hoarding! --------------------------------------------------------------------------*/ - -#ifndef REG_CC2510FX_H -#define REG_CC2510FX_H - -#include - -// Interrupt Vectors -#define RFTXRX_VECTOR 0 // RF TX done / RX ready -#define ADC_VECTOR 1 // ADC end of conversion -#define URX0_VECTOR 2 // USART0 RX complete -#define URX1_VECTOR 3 // USART1 RX complete (I2S RX complete) -#define ENC_VECTOR 4 // AES encryption/decryption complete -#define ST_VECTOR 5 // Sleep Timer compare -#define P2INT_VECTOR 6 // Port 2 inputs (Also used for USB on CC2511Fx) -#define UTX0_VECTOR 7 // USART0 TX complete -#define DMA_VECTOR 8 // DMA transfer complete -#define T1_VECTOR 9 // Timer 1 (16-bit) capture/Compare/overflow -#define T2_VECTOR 10 // Timer 2 (MAC Timer) overflow -#define T3_VECTOR 11 // Timer 3 (8-bit) capture/compare/overflow -#define T4_VECTOR 12 // Timer 4 (8-bit) capture/compare/overflow -#define P0INT_VECTOR 13 // Port 0 inputs (Note: USB Resume from suspend interrupt on P0_7 on CC2511Fx ) -#define UTX1_VECTOR 14 // USART1 TX complete (I2S TX complete) -#define P1INT_VECTOR 15 // Port 1 inputs -#define RF_VECTOR 16 // RF general interrupts -#define WDT_VECTOR 17 // Watchdog overflow in timer mode - -//Shared Interrupt Vectors (I2S and USB) -#define I2SRX_VECTOR 3 //I2S RX complete -#define I2STX_VECTOR 14 //I2S TX complete -#define USB_VECTOR 6 //USB Interrupt pending ( CC2511Fx ) - -// SFR Registers and BITs - -SFR(P0, 0x80); // Port 0 - SBIT(P0_0, 0x80, 0); // Port 0 bit 0 - SBIT(P0_1, 0x80, 1); // Port 0 bit 1 - SBIT(P0_2, 0x80, 2); // Port 0 bit 2 - SBIT(P0_3, 0x80, 3); // Port 0 bit 3 - SBIT(P0_4, 0x80, 4); // Port 0 bit 4 - SBIT(P0_5, 0x80, 5); // Port 0 bit 5 - SBIT(P0_6, 0x80, 6); // Port 0 bit 6 - SBIT(P0_7, 0x80, 7); // Port 0 bit 7 -SFR(SP, 0x81); // Stack Pointer -SFR(DPL0, 0x82); // Data Pointer 0 Low Byte -SFR(DPH0, 0x83); // Data Pointer 0 High Byte -SFR(DPL1, 0x84); // Data Pointer 1 Low Byte -SFR(DPH1, 0x85); // Data Pointer 1 High Byte -SFR(U0CSR, 0x86); // USART 0 Control and Status -SFR(PCON, 0x87); // Power Mode Control -SFR(TCON, 0x88); // Interrupt Flag - SBIT(IT0, 0x88, 0); // reserved (must always be set to 1) - SBIT(RFTXRXIF, 0x88, 1); // RF TX/RX FIFO Interrupt Flag - SBIT(IT1, 0x88, 2); // reserved (must always be set to 1) - SBIT(URX0IF, 0x88, 3); // USART0 RX Interrupt Flag - SBIT(ADCIF, 0x88, 5); // ADC Interrupt Flag - SBIT(URX1IF, 0x88, 7); // USART1 RX Interrupt Flag - SBIT(I2SRXIF, 0x88, 7); // I2S RX interrupt flag (same loc as URX1IF) -SFR(P0IFG, 0x89); // Port 0 Interrupt Status Flag -SFR(P1IFG, 0x8A); // Port 1 Interrupt Status Flag -SFR(P2IFG, 0x8B); // Port 2 Interrupt Status Flag -SFR(PICTL, 0x8C); // Port Interrupt Control -SFR(P1IEN, 0x8D); // Port 1 Interrupt Mask -SFR(P0INP, 0x8F); // Port 0 Input Mode -SFR(P1, 0x90); // Port 1 - SBIT(P1_0, 0x90, 0); // Port 1 bit 0 - SBIT(P1_1, 0x90, 1); // Port 1 bit 1 - SBIT(P1_2, 0x90, 2); // Port 1 bit 2 - SBIT(P1_3, 0x90, 3); // Port 1 bit 3 - SBIT(P1_4, 0x90, 4); // Port 1 bit 4 - SBIT(P1_5, 0x90, 5); // Port 1 bit 5 - SBIT(P1_6, 0x90, 6); // Port 1 bit 6 - SBIT(P1_7, 0x90, 7); // Port 1 bit 7 -SFR(RFIM, 0x91); // RF Interrupt Mask -SFR(DPS, 0x92); // Data Pointer Select -SFR(MPAGE, 0x93); // Memory Page Select -SFR(ENDIAN, 0x95); // USB Endianess Control (CC2511Fx) -SFR(S0CON, 0x98); // Interrupt Flag 2 - SBIT(ENCIF_0, 0x98, 0); // AES Interrupt Flag 0 - SBIT(ENCIF_1, 0x98, 1); // AES Interrupt Flag 1 -SFR(IEN2, 0x9A); // Interrupt Enable 2 Register -SFR(S1CON, 0x9B); // Interrupt Flag 3 -SFR(T2CT, 0x9C); // Timer 2 Count -SFR(T2PR, 0x9D); // Timer 2 Prescaler -SFR(T2CTL, 0x9E); // Timer 2 Control -SFR(P2, 0xA0); // Port 2 - SBIT(P2_0, 0xA0, 0); // Port 2 bit 0 - SBIT(P2_1, 0xA0, 1); // Port 2 bit 1 - SBIT(P2_2, 0xA0, 2); // Port 2 bit 2 - SBIT(P2_3, 0xA0, 3); // Port 2 bit 3 - SBIT(P2_4, 0xA0, 4); // Port 2 bit 4 - SBIT(P2_5, 0xA0, 5); // Port 2 bit 5 - SBIT(P2_6, 0xA0, 6); // Port 2 bit 6 - SBIT(P2_7, 0xA0, 7); // Port 2 bit 7 -SFR(WORIRQ, 0xA1); // Sleep Timer Interrupt Control -SFR(WORCTL, 0xA2); // Sleep Timer Control -SFR(WORCTRL, 0xA2); // Sleep Timer Control (typo in datasheet?) -SFR(WOREVT0, 0xA3); // Sleep Timer Event0 Timeout Low -SFR(WOREVT1, 0xA4); // Sleep Timer Event0 Timeout High -SFR(WORTIME0, 0xA5); // Sleep Timer Low Byte -SFR(WORTIME1, 0xA6); // Sleep Timer High Byte -SFR(IEN0, 0xA8); // Interrupt Enable 0 Register - SBIT(RFTXRXIE, 0xA8, 0); // RF TX/RX done interrupt enable - SBIT(ADCIE, 0xA8, 1); // ADC Interrupt Enable - SBIT(URX0IE, 0xA8, 2); // USART0 RX Interrupt Enable - SBIT(URX1IE, 0xA8, 3); // USART1 RX Interrupt Enable - SBIT(I2SRXIE, 0xA8, 3); // I2S RX interrupt enable (Same loc as URX1IE) - SBIT(ENCIE, 0xA8, 4); // AES Encryption/Decryption Interrupt Enable - SBIT(STIE, 0xA8, 5); // Sleep Timer Interrupt Enable - SBIT(EA, 0xA8, 7); // Global Interrupt Enable -SFR(IP0, 0xA9); // Interrupt Priority 0 -SFR(FWT, 0xAB); // Flash Write Timing -SFR(FADDRL, 0xAC); // Flash Address Low Byte -SFR(FADDRH, 0xAD); // Flash Address High Byte -SFR(FCTL, 0xAE); // Flash Control -SFR(FWDATA, 0xAF); // Flash Write Data -SFR(ENCDI, 0xB1); // Encryption Input Data -SFR(ENCDO, 0xB2); // Encryption Output Data -SFR(ENCCS, 0xB3); // Encryption Control and Status -SFR(ADCCON1, 0xB4); // ADC Control 1 -SFR(ADCCON2, 0xB5); // ADC Control 2 -SFR(ADCCON3, 0xB6); // ADC Control 3 -SFR(IEN1, 0xB8); // Interrupt Enable 1 Register - SBIT(DMAIE, 0xB8, 0); // DMA Transfer Interrupt Enable - SBIT(T1IE, 0xB8, 1); // Timer 1 Interrupt Enable - SBIT(T2IE, 0xB8, 2); // Timer 2 Interrupt Enable - SBIT(T3IE, 0xB8, 3); // Timer 3 Interrupt Enable - SBIT(T4IE, 0xB8, 4); // Timer 4 Interrupt Enable - SBIT(P0IE, 0xB8, 5); // Port 0 Interrupt Enable -SFR(IP1, 0xB9); // Interrupt Priority 1 -SFR(ADCL, 0xBA); // ADC Data Low -SFR(ADCH, 0xBB); // ADC Data High -SFR(RNDL, 0xBC); // Random Number Generator Data Low Byte -SFR(RNDH, 0xBD); // Random Number Generator Data High Byte -SFR(SLEEP, 0xBE); // Sleep Mode Control -SFR(IRCON, 0xC0); // Interrupt Flag 4 - SBIT(DMAIF, 0xC0, 0); // DMA Complete Interrupt Flag - SBIT(T1IF, 0xC0, 1); // Timer 1 Interrupt Flag - SBIT(T2IF, 0xC0, 2); // Timer 2 Interrupt Flag - SBIT(T3IF, 0xC0, 3); // Timer 3 Interrupt Flag - SBIT(T4IF, 0xC0, 4); // Timer 4 Interrupt Flag - SBIT(P0IF, 0xC0, 5); // Port 0 Interrupt Flag - SBIT(STIF, 0xC0, 7); // Sleep Timer Interrupt Flag -SFR(U0DBUF, 0xC1); // USART 0 Receive/Transmit Data Buffer -SFR(U0BAUD, 0xC2); // USART 0 Baud Rate Control -SFR(U0UCR, 0xC4); // USART 0 UART Control -SFR(U0GCR, 0xC5); // USART 0 Generic Control -SFR(CLKCON, 0xC6); // Clock Control -SFR(MEMCTR, 0xC7); // Memory Arbiter Control -SFR(WDCTL, 0xC9); // Watchdog Timer Control -SFR(T3CNT, 0xCA); // Timer 3 Counter -SFR(T3CTL, 0xCB); // Timer 3 Control -SFR(T3CCTL0, 0xCC); // Timer 3 Channel 0 Capture/Compare Control -SFR(T3CC0, 0xCD); // Timer 3 Channel 0 Capture/Compare Value -SFR(T3CCTL1, 0xCE); // Timer 3 Channel 1 Capture/Compare Control -SFR(T3CC1, 0xCF); // Timer 3 Channel 1 Capture/Compare Value -SFR(PSW, 0xD0); // Program Status Word - SBIT(P, 0xD0, 0); // Parity Flag - SBIT(F1, 0xD0, 1); // User-Defined Flag - SBIT(OV, 0xD0, 2); // Overflow Flag - SBIT(RS0, 0xD0, 3); // Register Bank Select 0 - SBIT(RS1, 0xD0, 4); // Register Bank Select 1 - SBIT(F0, 0xD0, 5); // User-Defined Flag - SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag - SBIT(CY, 0xD0, 7); // Carry Flag -SFR(DMAIRQ, 0xD1); // DMA Interrupt Flag -SFR(DMA1CFGL, 0xD2); // DMA Channel 1-4 Configuration Address Low Byte -SFR(DMA1CFGH, 0xD3); // DMA Channel 1-4 Configuration Address High Byte -SFR(DMA0CFGL, 0xD4); // DMA Channel 0 Configuration Address Low Byte -SFR(DMA0CFGH, 0xD5); // DMA Channel 0 Configuration Address High Byte -SFR(DMAARM, 0xD6); // DMA Channel Arm -SFR(DMAREQ, 0xD7); // DMA Channel Start Request and Status -SFR(TIMIF, 0xD8); // Timers 1/3/4 Interrupt Mask/Flag - SBIT(T3OVFIF, 0xD8, 0); // Timer 3 overflow interrupt flag 0:no pending 1:pending - SBIT(T3CH0IF, 0xD8, 1); // Timer 3 channel 0 interrupt flag 0:no pending 1:pending - SBIT(T3CH1IF, 0xD8, 2); // Timer 3 channel 1 interrupt flag 0:no pending 1:pending - SBIT(T4OVFIF, 0xD8, 3); // Timer 4 overflow interrupt flag 0:no pending 1:pending - SBIT(T4CH0IF, 0xD8, 4); // Timer 4 channel 0 interrupt flag 0:no pending 1:pending - SBIT(T4CH1IF, 0xD8, 5); // Timer 4 channel 1 interrupt flag 0:no pending 1:pending - SBIT(OVFIM, 0xD8, 6); // Timer 1 overflow interrupt mask -SFR(RFD, 0xD9); // RF Data -SFR(T1CC0L, 0xDA); // Timer 1 Channel 0 Capture/Compare Value Low -SFR(T1CC0H, 0xDB); // Timer 1 Channel 0 Capture/Compare Value High -SFR(T1CC1L, 0xDC); // Timer 1 Channel 1 Capture/Compare Value Low -SFR(T1CC1H, 0xDD); // Timer 1 Channel 1 Capture/Compare Value High -SFR(T1CC2L, 0xDE); // Timer 1 Channel 2 Capture/Compare Value Low -SFR(T1CC2H, 0xDF); // Timer 1 Channel 2 Capture/Compare Value High -SFR(ACC, 0xE0); // Accumulator - SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0 - SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1 - SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2 - SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3 - SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4 - SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5 - SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6 - SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7 -SFR(RFST, 0xE1); // RF Strobe Commands -SFR(T1CNTL, 0xE2); // Timer 1 Counter Low -SFR(T1CNTH, 0xE3); // Timer 1 Counter High -SFR(T1CTL, 0xE4); // Timer 1 Control and Status -SFR(T1CCTL0, 0xE5); // Timer 1 Channel 0 Capture/Compare Control -SFR(T1CCTL1, 0xE6); // Timer 1 Channel 1 Capture/Compare Control -SFR(T1CCTL2, 0xE7); // Timer 1 Channel 2 Capture/Compare Control -SFR(IRCON2, 0xE8); // Interrupt Flag 5 - SBIT(P2IF, 0xE8, 0); // Port 2 Interrupt Flag - SBIT(USBIF, 0xE8, 0); // USB Interrupt Flag (same bit as P2IF) - SBIT(UTX0IF, 0xE8, 1); // USART0 TX Interrupt Flag - SBIT(UTX1IF, 0xE8, 2); // USART1 TX Interrupt Flag - SBIT(I2STXIF, 0xE8, 2); // I2S TX Interrupt Flag (same bit as UTX1FIF) - SBIT(P1IF, 0xE8, 3); // Port 1 Interrupt Flag - SBIT(WDTIF, 0xE8, 4); // Watchdog Timer Interrupt Flag -SFR(RFIF, 0xE9); // RF Interrupt Flags -SFR(T4CNT, 0xEA); // Timer 4 Counter -SFR(T4CTL, 0xEB); // Timer 4 Control -SFR(T4CCTL0, 0xEC); // Timer 4 Channel 0 Capture/Compare Control -SFR(T4CC0, 0xED); // Timer 4 Channel 0 Capture/Compare Value -SFR(T4CCTL1, 0xEE); // Timer 4 Channel 1 Capture/Compare Control -SFR(T4CC1, 0xEF); // Timer 4 Channel 1 Capture/Compare Value -SFR(B, 0xF0); // B Register - SBIT(B_0, 0xF0, 0); // Register B bit 0 - SBIT(B_1, 0xF0, 1); // Register B bit 1 - SBIT(B_2, 0xF0, 2); // Register B bit 2 - SBIT(B_3, 0xF0, 3); // Register B bit 3 - SBIT(B_4, 0xF0, 4); // Register B bit 4 - SBIT(B_5, 0xF0, 5); // Register B bit 5 - SBIT(B_6, 0xF0, 6); // Register B bit 6 - SBIT(B_7, 0xF0, 7); // Register B bit 7 -SFR(PERCFG, 0xF1); // Peripheral Control -SFR(ADCCFG, 0xF2); // ADC Input Configuration -SFR(P0SEL, 0xF3); // Port 0 Function Select -SFR(P1SEL, 0xF4); // Port 1 Function Select -SFR(P2SEL, 0xF5); // Port 2 Function Select -SFR(P1INP, 0xF6); // Port 1 Input Mode -SFR(P2INP, 0xF7); // Port 2 Input Mode -SFR(U1CSR, 0xF8); // USART 1 Control and Status - SBIT(ACTIVE, 0xF8, 0); // USART transmit/receive active status 0:idle 1:busy - SBIT(TX_BYTE, 0xF8, 1); // Transmit byte status 0:Byte not transmitted 1:Last byte transmitted - SBIT(RX_BYTE, 0xF8, 2); // Receive byte status 0:No byte received 1:Received byte ready - SBIT(ERR, 0xF8, 3); // UART parity error status 0:No error 1:parity error - SBIT(FE, 0xF8, 4); // UART framing error status 0:No error 1:incorrect stop bit level - SBIT(SLAVE, 0xF8, 5); // SPI master or slave mode select 0:master 1:slave - SBIT(RE, 0xF8, 6); // UART receiver enable 0:disabled 1:enabled - SBIT(MODE, 0xF8, 7); // USART mode select 0:SPI 1:UART -SFR(U1DBUF, 0xF9); // USART 1 Receive/Transmit Data Buffer -SFR(U1BAUD, 0xFA); // USART 1 Baud Rate Control -SFR(U1UCR, 0xFB); // USART 1 UART Control -SFR(U1GCR, 0xFC); // USART 1 Generic Control -SFR(P0DIR, 0xFD); // Port 0 Direction -SFR(P1DIR, 0xFE); // Port 1 Direction -SFR(P2DIR, 0xFF); // Port 2 Direction - -// From table 68: xdata RF registers - -SFRX(SYNC1, 0xDF00); // Sync word, high byte -SFRX(SYNC0, 0xDF01); // Sync word, low byte -SFRX(PKTLEN, 0xDF02); // Packet length -SFRX(PKTCTRL1, 0xDF03); // Packet automation control -SFRX(PKTCTRL0, 0xDF04); // Packet automation control -SFRX(ADDR, 0xDF05); // Device address -SFRX(CHANNR, 0xDF06); // Channel number -SFRX(FSCTRL1, 0xDF07); // Frequency synthesizer control -SFRX(FSCTRL0, 0xDF08); // Frequency synthesizer control -SFRX(FREQ2, 0xDF09); // Frequency control word, high byte -SFRX(FREQ1, 0xDF0A); // Frequency control word, middle byte -SFRX(FREQ0, 0xDF0B); // Frequency control word, low byte -SFRX(MDMCFG4, 0xDF0C); // Modem configuration -SFRX(MDMCFG3, 0xDF0D); // Modem configuration -SFRX(MDMCFG2, 0xDF0E); // Modem configuration -SFRX(MDMCFG1, 0xDF0F); // Modem configuration -SFRX(MDMCFG0, 0xDF10); // Modem configuration -SFRX(DEVIATN, 0xDF11); // Modem deviation setting -SFRX(MCSM2, 0xDF12); // Main Radio Control State Machine configuration -SFRX(MCSM1, 0xDF13); // Main Radio Control State Machine configuration -SFRX(MCSM0, 0xDF14); // Main Radio Control State Machine configuration -SFRX(FOCCFG, 0xDF15); // Frequency Offset Compensation configuration -SFRX(BSCFG, 0xDF16); // Bit Synchronization configuration -SFRX(AGCCTRL2, 0xDF17); // AGC control -SFRX(AGCCTRL1, 0xDF18); // AGC control -SFRX(AGCCTRL0, 0xDF19); // AGC control -SFRX(FREND1, 0xDF1A); // Front end RX configuration -SFRX(FREND0, 0xDF1B); // Front end TX configuration -SFRX(FSCAL3, 0xDF1C); // Frequency synthesizer calibration -SFRX(FSCAL2, 0xDF1D); // Frequency synthesizer calibration -SFRX(FSCAL1, 0xDF1E); // Frequency synthesizer calibration -SFRX(FSCAL0, 0xDF1F); // Frequency synthesizer calibration -SFRX(PA_TABLE7, 0xDF27); // PA output power setting -SFRX(PA_TABLE6, 0xDF28); // PA output power setting -SFRX(PA_TABLE5, 0xDF29); // PA output power setting -SFRX(PA_TABLE4, 0xDF2A); // PA output power setting -SFRX(PA_TABLE3, 0xDF2B); // PA output power setting -SFRX(PA_TABLE2, 0xDF2C); // PA output power setting -SFRX(PA_TABLE1, 0xDF2D); // PA output power setting -SFRX(PA_TABLE0, 0xDF2E); // PA output power setting -SFRX(IOCFG2, 0xDF2F); // GDO2 output pin configuration -SFRX(IOCFG1, 0xDF30); // GDO1 output pin configuration -SFRX(IOCFG0, 0xDF31); // GDO0 output pin configuration -SFRX(PARTNUM, 0xDF36); // Chip Identifier -SFRX(VERSION, 0xDF37); // Configuration -SFRX(FREQEST, 0xDF38); // Frequency Offset Estimate -SFRX(LQI, 0xDF39); // Link Quality Indicator -SFRX(RSSI, 0xDF3A); // Received Signal Strength Indication -SFRX(MARCSTATE, 0xDF3B); // Main Radio Control State -SFRX(PKTSTATUS, 0xDF3C); // Packet status -SFRX(VCO_VC_DAC, 0xDF3D); // PLL calibration current - -// I2S Registers - -SFRX(I2SCFG0, 0xDF40); // I2S Configuration Register 0 -SFRX(I2SCFG1, 0xDF41); // I2S Configuration Register 1 -SFRX(I2SDATL, 0xDF42); // I2S Data Low Byte -SFRX(I2SDATH, 0xDF43); // I2S Data High Byte -SFRX(I2SWCNT, 0xDF44); // I2S Word Count Register -SFRX(I2SSTAT, 0xDF45); // I2S Status Register -SFRX(I2SCLKF0, 0xDF46); // I2S Clock Configuration Register 0 -SFRX(I2SCLKF1, 0xDF47); // I2S Clock Configuration Register 1 -SFRX(I2SCLKF2, 0xDF48); // I2S Clock Configuration Register 2 - -// Common USB Registers - -SFRX(USBADDR, 0xDE00); // Function Address -SFRX(USBPOW, 0xDE01); // Power/Control Register -SFRX(USBIIF, 0xDE02); // IN Endpoints and EP0 Interrupt Flags -SFRX(USBOIF, 0xDE04); // OUT Endpoints Interrupt Flags -SFRX(USBCIF, 0xDE06); // Common USB Interrupt Flags -SFRX(USBIIE, 0xDE07); // IN Endpoints and EP0 Interrupt Enable Mask -SFRX(USBOIE, 0xDE09); // Out Endpoints Interrupt Enable Mask -SFRX(USBCIE, 0xDE0B); // Common USB Interrupt Enable Mask -SFRX(USBFRML, 0xDE0C); // Current Frame Number (Low byte) -SFRX(USBFRMH, 0xDE0D); // Current Frame Number (High byte) -SFRX(USBINDEX, 0xDE0E); // Selects current endpoint. - -// Indexed Endpoint Registers - -SFRX(USBMAXI, 0xDE10); // Max. packet size for IN endpoint -SFRX(USBCS0, 0xDE11); // EP0 Control and Status (USBINDEX = 0) -SFRX(USBCSIL, 0xDE11); // IN EP{1-5} Control and Status Low -SFRX(USBCSIH, 0xDE12); // IN EP{1-5} Control and Status High -SFRX(USBMAXO, 0xDE13); // Max. packet size for OUT endpoint -SFRX(USBCSOL, 0xDE14); // OUT EP{1-5} Control and Status Low -SFRX(USBCSOH, 0xDE15); // OUT EP{1-5} Control and Status High -SFRX(USBCNT0, 0xDE16); // Number of received bytes in EP0 FIFO (USBINDEX = 0) -SFRX(USBCNTL, 0xDE16); // Number of bytes in OUT FIFO Low -SFRX(USBCNTH, 0xDE17); // Number of bytes in OUT FIFO High - -// Endpoint FIFO Registers - -SFRX(USBF0, 0xDE20); // Endpoint 0 FIFO -SFRX(USBF1, 0xDE22); // Endpoint 1 FIFO -SFRX(USBF2, 0xDE24); // Endpoint 2 FIFO -SFRX(USBF3, 0xDE26); // Endpoint 3 FIFO -SFRX(USBF4, 0xDE28); // Endpoint 4 FIFO -SFRX(USBF5, 0xDE2A); // Endpoint 5 FIFO - -// SFRs also accesible through XDATA space - -SFRX(X_U0CSR, 0xDF86); // USART 0 Control and Status -SFRX(X_P0IFG, 0xDF89); // Port 0 Interrupt Status Flag -SFRX(X_P1IFG, 0xDF8A); // Port 1 Interrupt Status Flag -SFRX(X_P2IFG, 0xDF8B); // Port 2 Interrupt Status Flag -SFRX(X_PICTL, 0xDF8C); // Port Pins Interrupt Mask and Edge -SFRX(X_P1IEN, 0xDF8D); // Port 1 Interrupt Mask -SFRX(X_P0INP, 0xDF8F); // Port 0 Input Mode -SFRX(X_RFIM, 0xDF91); // RF Interrupt Mask -SFRX(X_MPAGE, 0xDF93); // Memory Page Select -SFRX(X_T2CT, 0xDF9C); // Timer 2 Control -SFRX(X_T2PR, 0xDF9D); // Timer 2 Prescaler -SFRX(X_T2CTL, 0xDF9E); // Timer 2 Control -SFRX(X_WORIRQ, 0xDFA1); // Timer Sleep Timer Interrupts -SFRX(X_WORCTL, 0xDFA2); // Sleep Timer Control -SFRX(X_WOREVT0, 0xDFA3); // Timer Sleep Timer Event 0 Timeout Low Byte -SFRX(X_WOREVT1, 0xDFA4); // Timer Sleep Timer Event 0 Timeout High Byte -SFRX(X_WORTIME0, 0xDFA5); // Sleep Timer Value 0 -SFRX(X_WORTIME1, 0xDFA6); // Sleep Timer Value 1 -SFRX(X_FWT, 0xDFAB); // Flash Write Timing -SFRX(X_FADDRL, 0xDFAC); // Flash Address Low -SFRX(X_FADDRH, 0xDFAD); // Flash Address High -SFRX(X_FCTL, 0xDFAE); // Flash Control -SFRX(X_FWDATA, 0xDFAF); // Flash Write Data -SFRX(X_ENCDI, 0xDFB1); // Encryption/Decryption Input Data -SFRX(X_ENCDO, 0xDFB2); // Encryption/Decryption Output Data -SFRX(X_ENCCS, 0xDFB3); // Encryption/Decryption Control and Status -SFRX(X_ADCCON1, 0xDFB4); // ADC Control 1 -SFRX(X_ADCCON2, 0xDFB5); // ADC Control 2 -SFRX(X_ADCCON3, 0xDFB6); // ADC Control 3 -SFRX(X_ADCL, 0xDFBA); // ADC Data Low -SFRX(X_ADCH, 0xDFBB); // ADC Data High -SFRX(X_RNDL, 0xDFBC); // Random Number Generator Data Low -SFRX(X_RNDH, 0xDFBD); // Random Number Generator Data High -SFRX(X_SLEEP, 0xDFBE); // Flash Write Timing -SFRX(X_U0DBUF, 0xDFC1); // USART 0 Receive/Transmit Data Buffer -SFRX(X_U0BAUD, 0xDFC2); // USART 0 Baud Rate Control -SFRX(X_U0UCR, 0xDFC4); // USART 0 UART Control -SFRX(X_U0GCR, 0xDFC5); // USART 0 Generic Control -SFRX(X_CLKCON, 0xDFC6); // Clock Control -SFRX(X_MEMCTR, 0xDFC7); // Memory System Control -SFRX(X_WDCTL, 0xDFC9); // Watchdog Timer Control -SFRX(X_T3CNT, 0xDFCA); // Timer 3 Counter -SFRX(X_T3CTL, 0xDFCB); // Timer 3 Control -SFRX(X_T3CCTL0, 0xDFCC); // Timer 3 Channel 0 Capture/Compare Control -SFRX(X_T3CC0, 0xDFCD); // Timer 3 Channel 0 Capture/Compare Value -SFRX(X_T3CCTL1, 0xDFCE); // Timer 3 Channel 1 Capture/Compare Control -SFRX(X_T3CC1, 0xDFCF); // Timer 3 Channel 1 Capture/Compare Value -SFRX(X_DMAIRQ, 0xDFD1); // DMA Interrupt Flag -SFRX(X_DMA1CFGL, 0xDFD2); // DMA Channel 1-4 Configuration Address Low Byte -SFRX(X_DMA1CFGH, 0xDFD3); // DMA Channel 1-4 Configuration Address High Byte -SFRX(X_DMA0CFGL, 0xDFD4); // DMA Channel 0 Configuration Address Low Byte -SFRX(X_DMA0CFGH, 0xDFD5); // DMA Channel 0 Configuration Address High Byte -SFRX(X_DMAARM, 0xDFD6); // DMA Channel Arm -SFRX(X_DMAREQ, 0xDFD7); // DMA Channel Start Request and Status -SFRX(X_TIMIF, 0xDFD8); // Timers 1/3/4 Joint Interrupt Mask/Flags -SFRX(X_RFD, 0xDFD9); // RF Data -SFRX(X_T1CC0L, 0xDFDA); // Timer 1 Channel 0 Capture/Compare Value Low -SFRX(X_T1CC0H, 0xDFDB); // Timer 1 Channel 0 Capture/Compare Value High -SFRX(X_T1CC1L, 0xDFDC); // Timer 1 Channel 1 Capture/Compare Value Low -SFRX(X_T1CC1H, 0xDFDD); // Timer 1 Channel 1 Capture/Compare Value High -SFRX(X_T1CC2L, 0xDFDE); // Timer 1 Channel 2 Capture/Compare Value Low -SFRX(X_T1CC2H, 0xDFDF); // Timer 1 Channel 2 Capture/Compare Value High -SFRX(X_RFST, 0xDFE1); // RF Strobe Commands -SFRX(X_T1CNTL, 0xDFE2); // Timer 1 Counter Low -SFRX(X_T1CNTH, 0xDFE3); // Timer 1 Counter High -SFRX(X_T1CTL, 0xDFE4); // Timer 1 Control and Status -SFRX(X_T1CCTL0, 0xDFE5); // Timer 1 Channel 0 Capture/Compare Control -SFRX(X_T1CCTL1, 0xDFE6); // Timer 1 Channel 1 Capture/Compare Control -SFRX(X_T1CCTL2, 0xDFE7); // Timer 1 Channel 2 Capture/Compare Control -SFRX(X_RFIF, 0xDFE9); // RF Interrupt flags -SFRX(X_T4CNT, 0xDFEA); // Timer 4 Counter -SFRX(X_T4CTL, 0xDFEB); // Timer 4 Control -SFRX(X_T4CCTL0, 0xDFEC); // Timer 4 Channel 0 Capture/Compare Control -SFRX(X_T4CC0, 0xDFED); // Timer 4 Channel 0 Capture/Compare Value -SFRX(X_T4CCTL1, 0xDFEE); // Timer 4 Channel 1 Capture/Compare Control -SFRX(X_T4CC1, 0xDFEF); // Timer 4 Channel 1 Capture/Compare Value -SFRX(X_PERCFG, 0xDFF1); // Peripheral I/O Control -SFRX(X_ADCCFG, 0xDFF2); // ADC Input Configuration -SFRX(X_P0SEL, 0xDFF3); // Port 0 Function Select -SFRX(X_P1SEL, 0xDFF4); // Port 1 Function Select -SFRX(X_P2SEL, 0xDFF5); // Port 2 Function Select -SFRX(X_P1INP, 0xDFF6); // Port 1 Input Mode -SFRX(X_P2INP, 0xDFF7); // Port 2 Input Mode -SFRX(X_U1CSR, 0xDFF8); // USART 1 Control and Status -SFRX(X_U1DBUF, 0xDFF9); // USART 1 Receive/Transmit Data Buffer -SFRX(X_U1BAUD, 0xDFFA); // USART 1 Baud Rate Control -SFRX(X_U1UCR, 0xDFFB); // USART 1 UART Control -SFRX(X_U1GCR, 0xDFFC); // USART 1 Generic Control -SFRX(X_P0DIR, 0xDFFD); // Port 0 Direction -SFRX(X_P1DIR, 0xDFFE); // Port 1 Direction -SFRX(X_P2DIR, 0xDFFF); // Port 2 Direction - -#endif //REG_CC2510FX_H - +/*------------------------------------------------------------------------- + Register Declarations for Chipcon CC2510Fx/CC2511Fx + + Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (August 2006) + (Based on CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A) + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + In other words, you are welcome to use, share and improve this program. + You are forbidden to forbid anyone else to use, share and improve + what you give them. Help stamp out software-hoarding! +-------------------------------------------------------------------------*/ + +#ifndef REG_CC2510FX_H +#define REG_CC2510FX_H + +#include + +// Interrupt Vectors +#define RFTXRX_VECTOR 0 // RF TX done / RX ready +#define ADC_VECTOR 1 // ADC end of conversion +#define URX0_VECTOR 2 // USART0 RX complete +#define URX1_VECTOR 3 // USART1 RX complete (I2S RX complete) +#define ENC_VECTOR 4 // AES encryption/decryption complete +#define ST_VECTOR 5 // Sleep Timer compare +#define P2INT_VECTOR 6 // Port 2 inputs (Also used for USB on CC2511Fx) +#define UTX0_VECTOR 7 // USART0 TX complete +#define DMA_VECTOR 8 // DMA transfer complete +#define T1_VECTOR 9 // Timer 1 (16-bit) capture/Compare/overflow +#define T2_VECTOR 10 // Timer 2 (MAC Timer) overflow +#define T3_VECTOR 11 // Timer 3 (8-bit) capture/compare/overflow +#define T4_VECTOR 12 // Timer 4 (8-bit) capture/compare/overflow +#define P0INT_VECTOR 13 // Port 0 inputs (Note: USB Resume from suspend interrupt on P0_7 on CC2511Fx ) +#define UTX1_VECTOR 14 // USART1 TX complete (I2S TX complete) +#define P1INT_VECTOR 15 // Port 1 inputs +#define RF_VECTOR 16 // RF general interrupts +#define WDT_VECTOR 17 // Watchdog overflow in timer mode + +//Shared Interrupt Vectors (I2S and USB) +#define I2SRX_VECTOR 3 //I2S RX complete +#define I2STX_VECTOR 14 //I2S TX complete +#define USB_VECTOR 6 //USB Interrupt pending ( CC2511Fx ) + +// SFR Registers and BITs + +SFR(P0, 0x80); // Port 0 + SBIT(P0_0, 0x80, 0); // Port 0 bit 0 + SBIT(P0_1, 0x80, 1); // Port 0 bit 1 + SBIT(P0_2, 0x80, 2); // Port 0 bit 2 + SBIT(P0_3, 0x80, 3); // Port 0 bit 3 + SBIT(P0_4, 0x80, 4); // Port 0 bit 4 + SBIT(P0_5, 0x80, 5); // Port 0 bit 5 + SBIT(P0_6, 0x80, 6); // Port 0 bit 6 + SBIT(P0_7, 0x80, 7); // Port 0 bit 7 +SFR(SP, 0x81); // Stack Pointer +SFR(DPL0, 0x82); // Data Pointer 0 Low Byte +SFR(DPH0, 0x83); // Data Pointer 0 High Byte +SFR(DPL1, 0x84); // Data Pointer 1 Low Byte +SFR(DPH1, 0x85); // Data Pointer 1 High Byte +SFR(U0CSR, 0x86); // USART 0 Control and Status +SFR(PCON, 0x87); // Power Mode Control +SFR(TCON, 0x88); // Interrupt Flag + SBIT(IT0, 0x88, 0); // reserved (must always be set to 1) + SBIT(RFTXRXIF, 0x88, 1); // RF TX/RX FIFO Interrupt Flag + SBIT(IT1, 0x88, 2); // reserved (must always be set to 1) + SBIT(URX0IF, 0x88, 3); // USART0 RX Interrupt Flag + SBIT(ADCIF, 0x88, 5); // ADC Interrupt Flag + SBIT(URX1IF, 0x88, 7); // USART1 RX Interrupt Flag + SBIT(I2SRXIF, 0x88, 7); // I2S RX interrupt flag (same loc as URX1IF) +SFR(P0IFG, 0x89); // Port 0 Interrupt Status Flag +SFR(P1IFG, 0x8A); // Port 1 Interrupt Status Flag +SFR(P2IFG, 0x8B); // Port 2 Interrupt Status Flag +SFR(PICTL, 0x8C); // Port Interrupt Control +SFR(P1IEN, 0x8D); // Port 1 Interrupt Mask +SFR(P0INP, 0x8F); // Port 0 Input Mode +SFR(P1, 0x90); // Port 1 + SBIT(P1_0, 0x90, 0); // Port 1 bit 0 + SBIT(P1_1, 0x90, 1); // Port 1 bit 1 + SBIT(P1_2, 0x90, 2); // Port 1 bit 2 + SBIT(P1_3, 0x90, 3); // Port 1 bit 3 + SBIT(P1_4, 0x90, 4); // Port 1 bit 4 + SBIT(P1_5, 0x90, 5); // Port 1 bit 5 + SBIT(P1_6, 0x90, 6); // Port 1 bit 6 + SBIT(P1_7, 0x90, 7); // Port 1 bit 7 +SFR(RFIM, 0x91); // RF Interrupt Mask +SFR(DPS, 0x92); // Data Pointer Select +SFR(MPAGE, 0x93); // Memory Page Select +SFR(ENDIAN, 0x95); // USB Endianess Control (CC2511Fx) +SFR(S0CON, 0x98); // Interrupt Flag 2 + SBIT(ENCIF_0, 0x98, 0); // AES Interrupt Flag 0 + SBIT(ENCIF_1, 0x98, 1); // AES Interrupt Flag 1 +SFR(IEN2, 0x9A); // Interrupt Enable 2 Register +SFR(S1CON, 0x9B); // Interrupt Flag 3 +SFR(T2CT, 0x9C); // Timer 2 Count +SFR(T2PR, 0x9D); // Timer 2 Prescaler +SFR(T2CTL, 0x9E); // Timer 2 Control +SFR(P2, 0xA0); // Port 2 + SBIT(P2_0, 0xA0, 0); // Port 2 bit 0 + SBIT(P2_1, 0xA0, 1); // Port 2 bit 1 + SBIT(P2_2, 0xA0, 2); // Port 2 bit 2 + SBIT(P2_3, 0xA0, 3); // Port 2 bit 3 + SBIT(P2_4, 0xA0, 4); // Port 2 bit 4 + SBIT(P2_5, 0xA0, 5); // Port 2 bit 5 + SBIT(P2_6, 0xA0, 6); // Port 2 bit 6 + SBIT(P2_7, 0xA0, 7); // Port 2 bit 7 +SFR(WORIRQ, 0xA1); // Sleep Timer Interrupt Control +SFR(WORCTL, 0xA2); // Sleep Timer Control +SFR(WORCTRL, 0xA2); // Sleep Timer Control (typo in datasheet?) +SFR(WOREVT0, 0xA3); // Sleep Timer Event0 Timeout Low +SFR(WOREVT1, 0xA4); // Sleep Timer Event0 Timeout High +SFR(WORTIME0, 0xA5); // Sleep Timer Low Byte +SFR(WORTIME1, 0xA6); // Sleep Timer High Byte +SFR(IEN0, 0xA8); // Interrupt Enable 0 Register + SBIT(RFTXRXIE, 0xA8, 0); // RF TX/RX done interrupt enable + SBIT(ADCIE, 0xA8, 1); // ADC Interrupt Enable + SBIT(URX0IE, 0xA8, 2); // USART0 RX Interrupt Enable + SBIT(URX1IE, 0xA8, 3); // USART1 RX Interrupt Enable + SBIT(I2SRXIE, 0xA8, 3); // I2S RX interrupt enable (Same loc as URX1IE) + SBIT(ENCIE, 0xA8, 4); // AES Encryption/Decryption Interrupt Enable + SBIT(STIE, 0xA8, 5); // Sleep Timer Interrupt Enable + SBIT(EA, 0xA8, 7); // Global Interrupt Enable +SFR(IP0, 0xA9); // Interrupt Priority 0 +SFR(FWT, 0xAB); // Flash Write Timing +SFR(FADDRL, 0xAC); // Flash Address Low Byte +SFR(FADDRH, 0xAD); // Flash Address High Byte +SFR(FCTL, 0xAE); // Flash Control +SFR(FWDATA, 0xAF); // Flash Write Data +SFR(ENCDI, 0xB1); // Encryption Input Data +SFR(ENCDO, 0xB2); // Encryption Output Data +SFR(ENCCS, 0xB3); // Encryption Control and Status +SFR(ADCCON1, 0xB4); // ADC Control 1 +SFR(ADCCON2, 0xB5); // ADC Control 2 +SFR(ADCCON3, 0xB6); // ADC Control 3 +SFR(IEN1, 0xB8); // Interrupt Enable 1 Register + SBIT(DMAIE, 0xB8, 0); // DMA Transfer Interrupt Enable + SBIT(T1IE, 0xB8, 1); // Timer 1 Interrupt Enable + SBIT(T2IE, 0xB8, 2); // Timer 2 Interrupt Enable + SBIT(T3IE, 0xB8, 3); // Timer 3 Interrupt Enable + SBIT(T4IE, 0xB8, 4); // Timer 4 Interrupt Enable + SBIT(P0IE, 0xB8, 5); // Port 0 Interrupt Enable +SFR(IP1, 0xB9); // Interrupt Priority 1 +SFR(ADCL, 0xBA); // ADC Data Low +SFR(ADCH, 0xBB); // ADC Data High +SFR(RNDL, 0xBC); // Random Number Generator Data Low Byte +SFR(RNDH, 0xBD); // Random Number Generator Data High Byte +SFR(SLEEP, 0xBE); // Sleep Mode Control +SFR(IRCON, 0xC0); // Interrupt Flag 4 + SBIT(DMAIF, 0xC0, 0); // DMA Complete Interrupt Flag + SBIT(T1IF, 0xC0, 1); // Timer 1 Interrupt Flag + SBIT(T2IF, 0xC0, 2); // Timer 2 Interrupt Flag + SBIT(T3IF, 0xC0, 3); // Timer 3 Interrupt Flag + SBIT(T4IF, 0xC0, 4); // Timer 4 Interrupt Flag + SBIT(P0IF, 0xC0, 5); // Port 0 Interrupt Flag + SBIT(STIF, 0xC0, 7); // Sleep Timer Interrupt Flag +SFR(U0DBUF, 0xC1); // USART 0 Receive/Transmit Data Buffer +SFR(U0BAUD, 0xC2); // USART 0 Baud Rate Control +SFR(U0UCR, 0xC4); // USART 0 UART Control +SFR(U0GCR, 0xC5); // USART 0 Generic Control +SFR(CLKCON, 0xC6); // Clock Control +SFR(MEMCTR, 0xC7); // Memory Arbiter Control +SFR(WDCTL, 0xC9); // Watchdog Timer Control +SFR(T3CNT, 0xCA); // Timer 3 Counter +SFR(T3CTL, 0xCB); // Timer 3 Control +SFR(T3CCTL0, 0xCC); // Timer 3 Channel 0 Capture/Compare Control +SFR(T3CC0, 0xCD); // Timer 3 Channel 0 Capture/Compare Value +SFR(T3CCTL1, 0xCE); // Timer 3 Channel 1 Capture/Compare Control +SFR(T3CC1, 0xCF); // Timer 3 Channel 1 Capture/Compare Value +SFR(PSW, 0xD0); // Program Status Word + SBIT(P, 0xD0, 0); // Parity Flag + SBIT(F1, 0xD0, 1); // User-Defined Flag + SBIT(OV, 0xD0, 2); // Overflow Flag + SBIT(RS0, 0xD0, 3); // Register Bank Select 0 + SBIT(RS1, 0xD0, 4); // Register Bank Select 1 + SBIT(F0, 0xD0, 5); // User-Defined Flag + SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag + SBIT(CY, 0xD0, 7); // Carry Flag +SFR(DMAIRQ, 0xD1); // DMA Interrupt Flag +SFR(DMA1CFGL, 0xD2); // DMA Channel 1-4 Configuration Address Low Byte +SFR(DMA1CFGH, 0xD3); // DMA Channel 1-4 Configuration Address High Byte +SFR(DMA0CFGL, 0xD4); // DMA Channel 0 Configuration Address Low Byte +SFR(DMA0CFGH, 0xD5); // DMA Channel 0 Configuration Address High Byte +SFR(DMAARM, 0xD6); // DMA Channel Arm +SFR(DMAREQ, 0xD7); // DMA Channel Start Request and Status +SFR(TIMIF, 0xD8); // Timers 1/3/4 Interrupt Mask/Flag + SBIT(T3OVFIF, 0xD8, 0); // Timer 3 overflow interrupt flag 0:no pending 1:pending + SBIT(T3CH0IF, 0xD8, 1); // Timer 3 channel 0 interrupt flag 0:no pending 1:pending + SBIT(T3CH1IF, 0xD8, 2); // Timer 3 channel 1 interrupt flag 0:no pending 1:pending + SBIT(T4OVFIF, 0xD8, 3); // Timer 4 overflow interrupt flag 0:no pending 1:pending + SBIT(T4CH0IF, 0xD8, 4); // Timer 4 channel 0 interrupt flag 0:no pending 1:pending + SBIT(T4CH1IF, 0xD8, 5); // Timer 4 channel 1 interrupt flag 0:no pending 1:pending + SBIT(OVFIM, 0xD8, 6); // Timer 1 overflow interrupt mask +SFR(RFD, 0xD9); // RF Data +SFR(T1CC0L, 0xDA); // Timer 1 Channel 0 Capture/Compare Value Low +SFR(T1CC0H, 0xDB); // Timer 1 Channel 0 Capture/Compare Value High +SFR(T1CC1L, 0xDC); // Timer 1 Channel 1 Capture/Compare Value Low +SFR(T1CC1H, 0xDD); // Timer 1 Channel 1 Capture/Compare Value High +SFR(T1CC2L, 0xDE); // Timer 1 Channel 2 Capture/Compare Value Low +SFR(T1CC2H, 0xDF); // Timer 1 Channel 2 Capture/Compare Value High +SFR(ACC, 0xE0); // Accumulator + SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0 + SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1 + SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2 + SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3 + SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4 + SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5 + SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6 + SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7 +SFR(RFST, 0xE1); // RF Strobe Commands +SFR(T1CNTL, 0xE2); // Timer 1 Counter Low +SFR(T1CNTH, 0xE3); // Timer 1 Counter High +SFR(T1CTL, 0xE4); // Timer 1 Control and Status +SFR(T1CCTL0, 0xE5); // Timer 1 Channel 0 Capture/Compare Control +SFR(T1CCTL1, 0xE6); // Timer 1 Channel 1 Capture/Compare Control +SFR(T1CCTL2, 0xE7); // Timer 1 Channel 2 Capture/Compare Control +SFR(IRCON2, 0xE8); // Interrupt Flag 5 + SBIT(P2IF, 0xE8, 0); // Port 2 Interrupt Flag + SBIT(USBIF, 0xE8, 0); // USB Interrupt Flag (same bit as P2IF) + SBIT(UTX0IF, 0xE8, 1); // USART0 TX Interrupt Flag + SBIT(UTX1IF, 0xE8, 2); // USART1 TX Interrupt Flag + SBIT(I2STXIF, 0xE8, 2); // I2S TX Interrupt Flag (same bit as UTX1FIF) + SBIT(P1IF, 0xE8, 3); // Port 1 Interrupt Flag + SBIT(WDTIF, 0xE8, 4); // Watchdog Timer Interrupt Flag +SFR(RFIF, 0xE9); // RF Interrupt Flags +SFR(T4CNT, 0xEA); // Timer 4 Counter +SFR(T4CTL, 0xEB); // Timer 4 Control +SFR(T4CCTL0, 0xEC); // Timer 4 Channel 0 Capture/Compare Control +SFR(T4CC0, 0xED); // Timer 4 Channel 0 Capture/Compare Value +SFR(T4CCTL1, 0xEE); // Timer 4 Channel 1 Capture/Compare Control +SFR(T4CC1, 0xEF); // Timer 4 Channel 1 Capture/Compare Value +SFR(B, 0xF0); // B Register + SBIT(B_0, 0xF0, 0); // Register B bit 0 + SBIT(B_1, 0xF0, 1); // Register B bit 1 + SBIT(B_2, 0xF0, 2); // Register B bit 2 + SBIT(B_3, 0xF0, 3); // Register B bit 3 + SBIT(B_4, 0xF0, 4); // Register B bit 4 + SBIT(B_5, 0xF0, 5); // Register B bit 5 + SBIT(B_6, 0xF0, 6); // Register B bit 6 + SBIT(B_7, 0xF0, 7); // Register B bit 7 +SFR(PERCFG, 0xF1); // Peripheral Control +SFR(ADCCFG, 0xF2); // ADC Input Configuration +SFR(P0SEL, 0xF3); // Port 0 Function Select +SFR(P1SEL, 0xF4); // Port 1 Function Select +SFR(P2SEL, 0xF5); // Port 2 Function Select +SFR(P1INP, 0xF6); // Port 1 Input Mode +SFR(P2INP, 0xF7); // Port 2 Input Mode +SFR(U1CSR, 0xF8); // USART 1 Control and Status + SBIT(ACTIVE, 0xF8, 0); // USART transmit/receive active status 0:idle 1:busy + SBIT(TX_BYTE, 0xF8, 1); // Transmit byte status 0:Byte not transmitted 1:Last byte transmitted + SBIT(RX_BYTE, 0xF8, 2); // Receive byte status 0:No byte received 1:Received byte ready + SBIT(ERR, 0xF8, 3); // UART parity error status 0:No error 1:parity error + SBIT(FE, 0xF8, 4); // UART framing error status 0:No error 1:incorrect stop bit level + SBIT(SLAVE, 0xF8, 5); // SPI master or slave mode select 0:master 1:slave + SBIT(RE, 0xF8, 6); // UART receiver enable 0:disabled 1:enabled + SBIT(MODE, 0xF8, 7); // USART mode select 0:SPI 1:UART +SFR(U1DBUF, 0xF9); // USART 1 Receive/Transmit Data Buffer +SFR(U1BAUD, 0xFA); // USART 1 Baud Rate Control +SFR(U1UCR, 0xFB); // USART 1 UART Control +SFR(U1GCR, 0xFC); // USART 1 Generic Control +SFR(P0DIR, 0xFD); // Port 0 Direction +SFR(P1DIR, 0xFE); // Port 1 Direction +SFR(P2DIR, 0xFF); // Port 2 Direction + +// From table 68: xdata RF registers + +SFRX(SYNC1, 0xDF00); // Sync word, high byte +SFRX(SYNC0, 0xDF01); // Sync word, low byte +SFRX(PKTLEN, 0xDF02); // Packet length +SFRX(PKTCTRL1, 0xDF03); // Packet automation control +SFRX(PKTCTRL0, 0xDF04); // Packet automation control +SFRX(ADDR, 0xDF05); // Device address +SFRX(CHANNR, 0xDF06); // Channel number +SFRX(FSCTRL1, 0xDF07); // Frequency synthesizer control +SFRX(FSCTRL0, 0xDF08); // Frequency synthesizer control +SFRX(FREQ2, 0xDF09); // Frequency control word, high byte +SFRX(FREQ1, 0xDF0A); // Frequency control word, middle byte +SFRX(FREQ0, 0xDF0B); // Frequency control word, low byte +SFRX(MDMCFG4, 0xDF0C); // Modem configuration +SFRX(MDMCFG3, 0xDF0D); // Modem configuration +SFRX(MDMCFG2, 0xDF0E); // Modem configuration +SFRX(MDMCFG1, 0xDF0F); // Modem configuration +SFRX(MDMCFG0, 0xDF10); // Modem configuration +SFRX(DEVIATN, 0xDF11); // Modem deviation setting +SFRX(MCSM2, 0xDF12); // Main Radio Control State Machine configuration +SFRX(MCSM1, 0xDF13); // Main Radio Control State Machine configuration +SFRX(MCSM0, 0xDF14); // Main Radio Control State Machine configuration +SFRX(FOCCFG, 0xDF15); // Frequency Offset Compensation configuration +SFRX(BSCFG, 0xDF16); // Bit Synchronization configuration +SFRX(AGCCTRL2, 0xDF17); // AGC control +SFRX(AGCCTRL1, 0xDF18); // AGC control +SFRX(AGCCTRL0, 0xDF19); // AGC control +SFRX(FREND1, 0xDF1A); // Front end RX configuration +SFRX(FREND0, 0xDF1B); // Front end TX configuration +SFRX(FSCAL3, 0xDF1C); // Frequency synthesizer calibration +SFRX(FSCAL2, 0xDF1D); // Frequency synthesizer calibration +SFRX(FSCAL1, 0xDF1E); // Frequency synthesizer calibration +SFRX(FSCAL0, 0xDF1F); // Frequency synthesizer calibration +SFRX(PA_TABLE7, 0xDF27); // PA output power setting +SFRX(PA_TABLE6, 0xDF28); // PA output power setting +SFRX(PA_TABLE5, 0xDF29); // PA output power setting +SFRX(PA_TABLE4, 0xDF2A); // PA output power setting +SFRX(PA_TABLE3, 0xDF2B); // PA output power setting +SFRX(PA_TABLE2, 0xDF2C); // PA output power setting +SFRX(PA_TABLE1, 0xDF2D); // PA output power setting +SFRX(PA_TABLE0, 0xDF2E); // PA output power setting +SFRX(IOCFG2, 0xDF2F); // GDO2 output pin configuration +SFRX(IOCFG1, 0xDF30); // GDO1 output pin configuration +SFRX(IOCFG0, 0xDF31); // GDO0 output pin configuration +SFRX(PARTNUM, 0xDF36); // Chip Identifier +SFRX(VERSION, 0xDF37); // Configuration +SFRX(FREQEST, 0xDF38); // Frequency Offset Estimate +SFRX(LQI, 0xDF39); // Link Quality Indicator +SFRX(RSSI, 0xDF3A); // Received Signal Strength Indication +SFRX(MARCSTATE, 0xDF3B); // Main Radio Control State +SFRX(PKTSTATUS, 0xDF3C); // Packet status +SFRX(VCO_VC_DAC, 0xDF3D); // PLL calibration current + +// I2S Registers + +SFRX(I2SCFG0, 0xDF40); // I2S Configuration Register 0 +SFRX(I2SCFG1, 0xDF41); // I2S Configuration Register 1 +SFRX(I2SDATL, 0xDF42); // I2S Data Low Byte +SFRX(I2SDATH, 0xDF43); // I2S Data High Byte +SFRX(I2SWCNT, 0xDF44); // I2S Word Count Register +SFRX(I2SSTAT, 0xDF45); // I2S Status Register +SFRX(I2SCLKF0, 0xDF46); // I2S Clock Configuration Register 0 +SFRX(I2SCLKF1, 0xDF47); // I2S Clock Configuration Register 1 +SFRX(I2SCLKF2, 0xDF48); // I2S Clock Configuration Register 2 + +// Common USB Registers + +SFRX(USBADDR, 0xDE00); // Function Address +SFRX(USBPOW, 0xDE01); // Power/Control Register +SFRX(USBIIF, 0xDE02); // IN Endpoints and EP0 Interrupt Flags +SFRX(USBOIF, 0xDE04); // OUT Endpoints Interrupt Flags +SFRX(USBCIF, 0xDE06); // Common USB Interrupt Flags +SFRX(USBIIE, 0xDE07); // IN Endpoints and EP0 Interrupt Enable Mask +SFRX(USBOIE, 0xDE09); // Out Endpoints Interrupt Enable Mask +SFRX(USBCIE, 0xDE0B); // Common USB Interrupt Enable Mask +SFRX(USBFRML, 0xDE0C); // Current Frame Number (Low byte) +SFRX(USBFRMH, 0xDE0D); // Current Frame Number (High byte) +SFRX(USBINDEX, 0xDE0E); // Selects current endpoint. + +// Indexed Endpoint Registers + +SFRX(USBMAXI, 0xDE10); // Max. packet size for IN endpoint +SFRX(USBCS0, 0xDE11); // EP0 Control and Status (USBINDEX = 0) +SFRX(USBCSIL, 0xDE11); // IN EP{1-5} Control and Status Low +SFRX(USBCSIH, 0xDE12); // IN EP{1-5} Control and Status High +SFRX(USBMAXO, 0xDE13); // Max. packet size for OUT endpoint +SFRX(USBCSOL, 0xDE14); // OUT EP{1-5} Control and Status Low +SFRX(USBCSOH, 0xDE15); // OUT EP{1-5} Control and Status High +SFRX(USBCNT0, 0xDE16); // Number of received bytes in EP0 FIFO (USBINDEX = 0) +SFRX(USBCNTL, 0xDE16); // Number of bytes in OUT FIFO Low +SFRX(USBCNTH, 0xDE17); // Number of bytes in OUT FIFO High + +// Endpoint FIFO Registers + +SFRX(USBF0, 0xDE20); // Endpoint 0 FIFO +SFRX(USBF1, 0xDE22); // Endpoint 1 FIFO +SFRX(USBF2, 0xDE24); // Endpoint 2 FIFO +SFRX(USBF3, 0xDE26); // Endpoint 3 FIFO +SFRX(USBF4, 0xDE28); // Endpoint 4 FIFO +SFRX(USBF5, 0xDE2A); // Endpoint 5 FIFO + +// SFRs also accesible through XDATA space + +SFRX(X_U0CSR, 0xDF86); // USART 0 Control and Status +SFRX(X_P0IFG, 0xDF89); // Port 0 Interrupt Status Flag +SFRX(X_P1IFG, 0xDF8A); // Port 1 Interrupt Status Flag +SFRX(X_P2IFG, 0xDF8B); // Port 2 Interrupt Status Flag +SFRX(X_PICTL, 0xDF8C); // Port Pins Interrupt Mask and Edge +SFRX(X_P1IEN, 0xDF8D); // Port 1 Interrupt Mask +SFRX(X_P0INP, 0xDF8F); // Port 0 Input Mode +SFRX(X_RFIM, 0xDF91); // RF Interrupt Mask +SFRX(X_MPAGE, 0xDF93); // Memory Page Select +SFRX(X_T2CT, 0xDF9C); // Timer 2 Control +SFRX(X_T2PR, 0xDF9D); // Timer 2 Prescaler +SFRX(X_T2CTL, 0xDF9E); // Timer 2 Control +SFRX(X_WORIRQ, 0xDFA1); // Timer Sleep Timer Interrupts +SFRX(X_WORCTL, 0xDFA2); // Sleep Timer Control +SFRX(X_WOREVT0, 0xDFA3); // Timer Sleep Timer Event 0 Timeout Low Byte +SFRX(X_WOREVT1, 0xDFA4); // Timer Sleep Timer Event 0 Timeout High Byte +SFRX(X_WORTIME0, 0xDFA5); // Sleep Timer Value 0 +SFRX(X_WORTIME1, 0xDFA6); // Sleep Timer Value 1 +SFRX(X_FWT, 0xDFAB); // Flash Write Timing +SFRX(X_FADDRL, 0xDFAC); // Flash Address Low +SFRX(X_FADDRH, 0xDFAD); // Flash Address High +SFRX(X_FCTL, 0xDFAE); // Flash Control +SFRX(X_FWDATA, 0xDFAF); // Flash Write Data +SFRX(X_ENCDI, 0xDFB1); // Encryption/Decryption Input Data +SFRX(X_ENCDO, 0xDFB2); // Encryption/Decryption Output Data +SFRX(X_ENCCS, 0xDFB3); // Encryption/Decryption Control and Status +SFRX(X_ADCCON1, 0xDFB4); // ADC Control 1 +SFRX(X_ADCCON2, 0xDFB5); // ADC Control 2 +SFRX(X_ADCCON3, 0xDFB6); // ADC Control 3 +SFRX(X_ADCL, 0xDFBA); // ADC Data Low +SFRX(X_ADCH, 0xDFBB); // ADC Data High +SFRX(X_RNDL, 0xDFBC); // Random Number Generator Data Low +SFRX(X_RNDH, 0xDFBD); // Random Number Generator Data High +SFRX(X_SLEEP, 0xDFBE); // Flash Write Timing +SFRX(X_U0DBUF, 0xDFC1); // USART 0 Receive/Transmit Data Buffer +SFRX(X_U0BAUD, 0xDFC2); // USART 0 Baud Rate Control +SFRX(X_U0UCR, 0xDFC4); // USART 0 UART Control +SFRX(X_U0GCR, 0xDFC5); // USART 0 Generic Control +SFRX(X_CLKCON, 0xDFC6); // Clock Control +SFRX(X_MEMCTR, 0xDFC7); // Memory System Control +SFRX(X_WDCTL, 0xDFC9); // Watchdog Timer Control +SFRX(X_T3CNT, 0xDFCA); // Timer 3 Counter +SFRX(X_T3CTL, 0xDFCB); // Timer 3 Control +SFRX(X_T3CCTL0, 0xDFCC); // Timer 3 Channel 0 Capture/Compare Control +SFRX(X_T3CC0, 0xDFCD); // Timer 3 Channel 0 Capture/Compare Value +SFRX(X_T3CCTL1, 0xDFCE); // Timer 3 Channel 1 Capture/Compare Control +SFRX(X_T3CC1, 0xDFCF); // Timer 3 Channel 1 Capture/Compare Value +SFRX(X_DMAIRQ, 0xDFD1); // DMA Interrupt Flag +SFRX(X_DMA1CFGL, 0xDFD2); // DMA Channel 1-4 Configuration Address Low Byte +SFRX(X_DMA1CFGH, 0xDFD3); // DMA Channel 1-4 Configuration Address High Byte +SFRX(X_DMA0CFGL, 0xDFD4); // DMA Channel 0 Configuration Address Low Byte +SFRX(X_DMA0CFGH, 0xDFD5); // DMA Channel 0 Configuration Address High Byte +SFRX(X_DMAARM, 0xDFD6); // DMA Channel Arm +SFRX(X_DMAREQ, 0xDFD7); // DMA Channel Start Request and Status +SFRX(X_TIMIF, 0xDFD8); // Timers 1/3/4 Joint Interrupt Mask/Flags +SFRX(X_RFD, 0xDFD9); // RF Data +SFRX(X_T1CC0L, 0xDFDA); // Timer 1 Channel 0 Capture/Compare Value Low +SFRX(X_T1CC0H, 0xDFDB); // Timer 1 Channel 0 Capture/Compare Value High +SFRX(X_T1CC1L, 0xDFDC); // Timer 1 Channel 1 Capture/Compare Value Low +SFRX(X_T1CC1H, 0xDFDD); // Timer 1 Channel 1 Capture/Compare Value High +SFRX(X_T1CC2L, 0xDFDE); // Timer 1 Channel 2 Capture/Compare Value Low +SFRX(X_T1CC2H, 0xDFDF); // Timer 1 Channel 2 Capture/Compare Value High +SFRX(X_RFST, 0xDFE1); // RF Strobe Commands +SFRX(X_T1CNTL, 0xDFE2); // Timer 1 Counter Low +SFRX(X_T1CNTH, 0xDFE3); // Timer 1 Counter High +SFRX(X_T1CTL, 0xDFE4); // Timer 1 Control and Status +SFRX(X_T1CCTL0, 0xDFE5); // Timer 1 Channel 0 Capture/Compare Control +SFRX(X_T1CCTL1, 0xDFE6); // Timer 1 Channel 1 Capture/Compare Control +SFRX(X_T1CCTL2, 0xDFE7); // Timer 1 Channel 2 Capture/Compare Control +SFRX(X_RFIF, 0xDFE9); // RF Interrupt flags +SFRX(X_T4CNT, 0xDFEA); // Timer 4 Counter +SFRX(X_T4CTL, 0xDFEB); // Timer 4 Control +SFRX(X_T4CCTL0, 0xDFEC); // Timer 4 Channel 0 Capture/Compare Control +SFRX(X_T4CC0, 0xDFED); // Timer 4 Channel 0 Capture/Compare Value +SFRX(X_T4CCTL1, 0xDFEE); // Timer 4 Channel 1 Capture/Compare Control +SFRX(X_T4CC1, 0xDFEF); // Timer 4 Channel 1 Capture/Compare Value +SFRX(X_PERCFG, 0xDFF1); // Peripheral I/O Control +SFRX(X_ADCCFG, 0xDFF2); // ADC Input Configuration +SFRX(X_P0SEL, 0xDFF3); // Port 0 Function Select +SFRX(X_P1SEL, 0xDFF4); // Port 1 Function Select +SFRX(X_P2SEL, 0xDFF5); // Port 2 Function Select +SFRX(X_P1INP, 0xDFF6); // Port 1 Input Mode +SFRX(X_P2INP, 0xDFF7); // Port 2 Input Mode +SFRX(X_U1CSR, 0xDFF8); // USART 1 Control and Status +SFRX(X_U1DBUF, 0xDFF9); // USART 1 Receive/Transmit Data Buffer +SFRX(X_U1BAUD, 0xDFFA); // USART 1 Baud Rate Control +SFRX(X_U1UCR, 0xDFFB); // USART 1 UART Control +SFRX(X_U1GCR, 0xDFFC); // USART 1 Generic Control +SFRX(X_P0DIR, 0xDFFD); // Port 0 Direction +SFRX(X_P1DIR, 0xDFFE); // Port 1 Direction +SFRX(X_P2DIR, 0xDFFF); // Port 2 Direction + +#endif //REG_CC2510FX_H + diff --git a/device/include/mcs51/compiler.h b/device/include/mcs51/compiler.h index e8bdc283..a21bc0fd 100644 --- a/device/include/mcs51/compiler.h +++ b/device/include/mcs51/compiler.h @@ -1,177 +1,177 @@ -/** \file compiler.h - * \author Maarten Brock - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * In other words, you are welcome to use, share and improve this program. - * You are forbidden to forbid anyone else to use, share and improve - * what you give them. Help stamp out software-hoarding! - * - * Header file to overcome 8051 compiler differences for specifying - * special function registers. The following compilers are supported: - * SDCC, Keil, Raisonance, IAR, Hi-Tech, Tasking, Crossware, Wickenhäuser. - * Unfortunately not for use with Dunfield. The compilers are identified by - * their unique predefined macros. See also: - * http://predef.sourceforge.net/precomp.html - * - * SBIT and SFR define special bit and special function registers at the given - * address. SFR16 and SFR32 define sfr combinations at adjacent addresses in - * little-endian format. SFR16E and SFR32E define sfr combinations without - * prerequisite byte order or adjacency. None of these multi-byte sfr - * combinations will guarantee the order in which they are accessed when read - * or written. - * SFR16X and SFR32X for 16 bit and 32 bit xdata registers are not defined - * to avoid portability issues because of compiler endianness. - * This file is to be included in every microcontroller specific header file. - * Example: - * - * // my_mcu.h: sfr definitions for my mcu - * #include - * - * SBIT (P0_1, 0x80, 1); // Port 0 pin 1 - * - * SFR (P0, 0x80); // Port 0 - * - * SFRX (CPUCS, 0xE600); // Cypress FX2 Control and Status register in xdata memory at 0xE600 - * - * SFR16 (TMR2, 0xCC); // Timer 2, lsb at 0xCC, msb at 0xCD - * - * SFR16E(TMR0, 0x8C8A); // Timer 0, lsb at 0x8A, msb at 0x8C - * - * SFR32 (MAC0ACC, 0x93); // SiLabs C8051F120 32 bits MAC0 Accumulator, lsb at 0x93, msb at 0x96 - * - * SFR32E(SUMR, 0xE5E4E3E2); // TI MSC1210 SUMR 32 bits Summation register, lsb at 0xE2, msb at 0xE5 - * - */ - -#ifndef COMPILER_H -#define COMPILER_H - -/** SDCC - Small Device C Compiler - * http://sdcc.sf.net - */ -#if defined SDCC -# define SBIT(name, addr, bit) __sbit __at(addr+bit) name -# define SFR(name, addr) __sfr __at(addr) name -# define SFRX(name, addr) xdata volatile unsigned char __at(addr) name -# define SFR16(name, addr) __sfr16 __at(((addr+1U)<<8) | addr) name -# define SFR16E(name, fulladdr) __sfr16 __at(fulladdr) name -# define SFR32(name, addr) __sfr32 __at(((addr+3UL)<<24) | ((addr+2UL)<<16) | ((addr+1UL)<<8) | addr) name -# define SFR32E(name, fulladdr) __sfr32 __at(fulladdr) name - -/** Keil C51 - * http://www.keil.com - */ -#elif defined __CX51__ -# define SBIT(name, addr, bit) sbit name = addr^bit -# define SFR(name, addr) sfr name = addr -# define SFRX(name, addr) volatile unsigned char xdata name _at_ addr -# define SFR16(name, addr) sfr16 name = addr -# define SFR16E(name, fulladdr) /* not supported */ -# define SFR32(name, fulladdr) /* not supported */ -# define SFR32E(name, fulladdr) /* not supported */ - -/** Raisonance - * http://www.raisonance.com - */ -#elif defined __RC51__ -# define SBIT(name, addr, bit) at (addr+bit) sbit name -# define SFR(name, addr) sfr at addr name -# define SFRX(name, addr) xdata at addr volatile unsigned char name -# define SFR16(name, addr) sfr16 at addr name -# define SFR16E(name, fulladdr) /* not supported */ -# define SFR32(name, fulladdr) /* not supported */ -# define SFR32E(name, fulladdr) /* not supported */ - -/** IAR 8051 - * http://www.iar.com - */ -#elif defined __ICC8051__ -# define SBIT(name, addr, bit) __bit __no_init volatile bool name @ (addr+bit) -# define SFR(name, addr) __sfr __no_init volatile unsigned char name @ addr -# define SFRX(name, addr) __xdata __no_init volatile unsigned char name @ addr -# define SFR16(name, addr) __sfr __no_init volatile unsigned int name @ addr -# define SFR16E(name, fulladdr) /* not supported */ -# define SFR32(name, fulladdr) __sfr __no_init volatile unsigned long name @ addr -# define SFR32E(name, fulladdr) /* not supported */ - -/** Tasking / Altium - * http://www.altium.com/tasking - */ -#elif defined _CC51 -# define SBIT(name, addr, bit) _sfrbit name _at(addr+bit) -# define SFR(name, addr) _sfrbyte name _at(addr) -# define SFRX(name, addr) _xdat volatile unsigned char name _at(addr) -#if _CC51 > 71 -# define SFR16(name, addr) _sfrword _little name _at(addr) -#else -# define SFR16(name, addr) /* not supported */ -#endif -# define SFR16E(name, fulladdr) /* not supported */ -# define SFR32(name, fulladdr) /* not supported */ -# define SFR32E(name, fulladdr) /* not supported */ - -/** Hi-Tech 8051 - * http://www.htsoft.com - */ -#elif defined HI_TECH_C -# define SBIT(name, addr, bit) volatile bit name @ (addr+bit) -# define SFR(name, addr) volatile unsigned char name @ addr -# define SFRX(name, addr) volatile far unsigned char name @ addr -# define SFR16(name, addr) /* not supported */ -# define SFR16E(name, fulladdr) /* not supported */ -# define SFR32(name, fulladdr) /* not supported */ -# define SFR32E(name, fulladdr) /* not supported */ - -/** Crossware - * http://www.crossware.com - */ -#elif defined _XC51_VER -# define SBIT(name, addr, bit) _sfrbit name = (addr+bit) -# define SFR(name, addr) _sfr name = addr -# define SFRX(name, addr) volatile unsigned char _xdata name _at addr -# define SFR16(name, addr) _sfrword name = addr -# define SFR16E(name, fulladdr) /* not supported */ -# define SFR32(name, fulladdr) /* not supported */ -# define SFR32E(name, fulladdr) /* not supported */ - -/** Wickenhäuser - * http://www.wickenhaeuser.de - */ -#elif defined __UC__ -# define SBIT(name, addr, bit) unsigned char bit name @ (addr+bit) -# define SFR(name, addr) near unsigned char name @ addr -# define SFRX(name, addr) xdata volatile unsigned char name @ addr -# define SFR16(name, addr) /* not supported */ -# define SFR16E(name, fulladdr) /* not supported */ -# define SFR32(name, fulladdr) /* not supported */ -# define SFR32E(name, fulladdr) /* not supported */ - -/** default - * unknown compiler - */ -#elif -# warning unknown compiler -# define SBIT(name, addr, bit) volatile bool name -# define SFR(name, addr) volatile unsigned char name -# define SFRX(name, addr) volatile unsigned char name -# define SFR16(name, addr) volatile unsigned short name -# define SFR16E(name, fulladdr) volatile unsigned short name -# define SFR32(name, fulladdr) volatile unsigned long name -# define SFR32E(name, fulladdr) volatile unsigned long name - -#endif - -#endif //COMPILER_H +/** \file compiler.h + * \author Maarten Brock + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * In other words, you are welcome to use, share and improve this program. + * You are forbidden to forbid anyone else to use, share and improve + * what you give them. Help stamp out software-hoarding! + * + * Header file to overcome 8051 compiler differences for specifying + * special function registers. The following compilers are supported: + * SDCC, Keil, Raisonance, IAR, Hi-Tech, Tasking, Crossware, Wickenhäuser. + * Unfortunately not for use with Dunfield. The compilers are identified by + * their unique predefined macros. See also: + * http://predef.sourceforge.net/precomp.html + * + * SBIT and SFR define special bit and special function registers at the given + * address. SFR16 and SFR32 define sfr combinations at adjacent addresses in + * little-endian format. SFR16E and SFR32E define sfr combinations without + * prerequisite byte order or adjacency. None of these multi-byte sfr + * combinations will guarantee the order in which they are accessed when read + * or written. + * SFR16X and SFR32X for 16 bit and 32 bit xdata registers are not defined + * to avoid portability issues because of compiler endianness. + * This file is to be included in every microcontroller specific header file. + * Example: + * + * // my_mcu.h: sfr definitions for my mcu + * #include + * + * SBIT (P0_1, 0x80, 1); // Port 0 pin 1 + * + * SFR (P0, 0x80); // Port 0 + * + * SFRX (CPUCS, 0xE600); // Cypress FX2 Control and Status register in xdata memory at 0xE600 + * + * SFR16 (TMR2, 0xCC); // Timer 2, lsb at 0xCC, msb at 0xCD + * + * SFR16E(TMR0, 0x8C8A); // Timer 0, lsb at 0x8A, msb at 0x8C + * + * SFR32 (MAC0ACC, 0x93); // SiLabs C8051F120 32 bits MAC0 Accumulator, lsb at 0x93, msb at 0x96 + * + * SFR32E(SUMR, 0xE5E4E3E2); // TI MSC1210 SUMR 32 bits Summation register, lsb at 0xE2, msb at 0xE5 + * + */ + +#ifndef COMPILER_H +#define COMPILER_H + +/** SDCC - Small Device C Compiler + * http://sdcc.sf.net + */ +#if defined SDCC +# define SBIT(name, addr, bit) __sbit __at(addr+bit) name +# define SFR(name, addr) __sfr __at(addr) name +# define SFRX(name, addr) xdata volatile unsigned char __at(addr) name +# define SFR16(name, addr) __sfr16 __at(((addr+1U)<<8) | addr) name +# define SFR16E(name, fulladdr) __sfr16 __at(fulladdr) name +# define SFR32(name, addr) __sfr32 __at(((addr+3UL)<<24) | ((addr+2UL)<<16) | ((addr+1UL)<<8) | addr) name +# define SFR32E(name, fulladdr) __sfr32 __at(fulladdr) name + +/** Keil C51 + * http://www.keil.com + */ +#elif defined __CX51__ +# define SBIT(name, addr, bit) sbit name = addr^bit +# define SFR(name, addr) sfr name = addr +# define SFRX(name, addr) volatile unsigned char xdata name _at_ addr +# define SFR16(name, addr) sfr16 name = addr +# define SFR16E(name, fulladdr) /* not supported */ +# define SFR32(name, fulladdr) /* not supported */ +# define SFR32E(name, fulladdr) /* not supported */ + +/** Raisonance + * http://www.raisonance.com + */ +#elif defined __RC51__ +# define SBIT(name, addr, bit) at (addr+bit) sbit name +# define SFR(name, addr) sfr at addr name +# define SFRX(name, addr) xdata at addr volatile unsigned char name +# define SFR16(name, addr) sfr16 at addr name +# define SFR16E(name, fulladdr) /* not supported */ +# define SFR32(name, fulladdr) /* not supported */ +# define SFR32E(name, fulladdr) /* not supported */ + +/** IAR 8051 + * http://www.iar.com + */ +#elif defined __ICC8051__ +# define SBIT(name, addr, bit) __bit __no_init volatile bool name @ (addr+bit) +# define SFR(name, addr) __sfr __no_init volatile unsigned char name @ addr +# define SFRX(name, addr) __xdata __no_init volatile unsigned char name @ addr +# define SFR16(name, addr) __sfr __no_init volatile unsigned int name @ addr +# define SFR16E(name, fulladdr) /* not supported */ +# define SFR32(name, fulladdr) __sfr __no_init volatile unsigned long name @ addr +# define SFR32E(name, fulladdr) /* not supported */ + +/** Tasking / Altium + * http://www.altium.com/tasking + */ +#elif defined _CC51 +# define SBIT(name, addr, bit) _sfrbit name _at(addr+bit) +# define SFR(name, addr) _sfrbyte name _at(addr) +# define SFRX(name, addr) _xdat volatile unsigned char name _at(addr) +#if _CC51 > 71 +# define SFR16(name, addr) _sfrword _little name _at(addr) +#else +# define SFR16(name, addr) /* not supported */ +#endif +# define SFR16E(name, fulladdr) /* not supported */ +# define SFR32(name, fulladdr) /* not supported */ +# define SFR32E(name, fulladdr) /* not supported */ + +/** Hi-Tech 8051 + * http://www.htsoft.com + */ +#elif defined HI_TECH_C +# define SBIT(name, addr, bit) volatile bit name @ (addr+bit) +# define SFR(name, addr) volatile unsigned char name @ addr +# define SFRX(name, addr) volatile far unsigned char name @ addr +# define SFR16(name, addr) /* not supported */ +# define SFR16E(name, fulladdr) /* not supported */ +# define SFR32(name, fulladdr) /* not supported */ +# define SFR32E(name, fulladdr) /* not supported */ + +/** Crossware + * http://www.crossware.com + */ +#elif defined _XC51_VER +# define SBIT(name, addr, bit) _sfrbit name = (addr+bit) +# define SFR(name, addr) _sfr name = addr +# define SFRX(name, addr) volatile unsigned char _xdata name _at addr +# define SFR16(name, addr) _sfrword name = addr +# define SFR16E(name, fulladdr) /* not supported */ +# define SFR32(name, fulladdr) /* not supported */ +# define SFR32E(name, fulladdr) /* not supported */ + +/** Wickenhäuser + * http://www.wickenhaeuser.de + */ +#elif defined __UC__ +# define SBIT(name, addr, bit) unsigned char bit name @ (addr+bit) +# define SFR(name, addr) near unsigned char name @ addr +# define SFRX(name, addr) xdata volatile unsigned char name @ addr +# define SFR16(name, addr) /* not supported */ +# define SFR16E(name, fulladdr) /* not supported */ +# define SFR32(name, fulladdr) /* not supported */ +# define SFR32E(name, fulladdr) /* not supported */ + +/** default + * unknown compiler + */ +#elif +# warning unknown compiler +# define SBIT(name, addr, bit) volatile bool name +# define SFR(name, addr) volatile unsigned char name +# define SFRX(name, addr) volatile unsigned char name +# define SFR16(name, addr) volatile unsigned short name +# define SFR16E(name, fulladdr) volatile unsigned short name +# define SFR32(name, fulladdr) volatile unsigned long name +# define SFR32E(name, fulladdr) volatile unsigned long name + +#endif + +#endif //COMPILER_H diff --git a/device/include/mcs51/msc1210.h b/device/include/mcs51/msc1210.h index 3f5c95a6..fcd84566 100644 --- a/device/include/mcs51/msc1210.h +++ b/device/include/mcs51/msc1210.h @@ -1,316 +1,316 @@ -/*-------------------------------------------------------------------------- - * Register Declarations for Texas Intruments MSC12xx MCU family - * - * Written By - Philippe Latu / philippe.latu(at)linux-france.org - * $Id: msc1210.h 893 2006-05-10 21:32:22Z latu $ - * - * Copyright (C) 2006 Philippe Latu - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - * - *---------------------------------------------------------------------------*/ - -#ifndef __MSC1210_H__ -#define __MSC1210_H__ - -/* BYTE Registers with bit definitions */ - -__sfr __at (0x80) P0; /* Port 0 */ -__sfr __at (0x81) SP; /* Stack Pointer */ -__sfr __at (0x82) DPL; /* Data Pointer 0: low byte */ -__sfr __at (0x82) DPL0; /* Data Pointer 0: low byte */ -__sfr __at (0x83) DPH; /* Data Pointer 0: high byte */ -__sfr __at (0x83) DPH0; /* Data Pointer 0: high byte */ -__sfr __at (0x84) DPL1; /* Data Pointer 1: low byte */ -__sfr __at (0x85) DPH1; /* Data Pointer 1: high byte */ -__sfr __at (0x86) DPS; /* Data Pointer Select */ -__sfr __at (0x87) PCON; /* Power Control */ -__sfr __at (0x88) TCON; /* Timer Control */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* |TF1|TR1|TF0|TR0|IE1|IT1|IE0|IT0| */ - __sbit __at (0x88) IT0; /* External Interrupt 0 Type */ - __sbit __at (0x89) IE0; /* External Interrupt 0 Edge Flag */ - __sbit __at (0x8a) IT1; /* External Interrupt 1 Type */ - __sbit __at (0x8b) IE1; /* External Interrupt 1 Edge Flag */ - __sbit __at (0x8c) TR0; /* Timer 0 On/Off Control */ - __sbit __at (0x8d) TF0; /* Timer 0 Overflow Flag */ - __sbit __at (0x8e) TR1; /* Timer 1 On/Off Control */ - __sbit __at (0x8f) TF1; /* Timer 1 Overflow Flag */ -__sfr __at (0x89) TMOD; /* Timer Mode */ -__sfr __at (0x8a) TL0; /* Timer 0: low byte */ -__sfr __at (0x8b) TL1; /* Timer 1: low byte */ -__sfr __at (0x8c) TH0; /* Timer 0: high byte */ -__sfr __at (0x8d) TH1; /* Timer 1: high byte */ -__sfr __at (0x8e) CKCON; /* Clock Control */ -__sfr __at (0x8f) MWS; /* Memory Write Select */ -__sfr __at (0x90) P1; /* Port 1 */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* | | | | | | |T2EX|T2 | */ - __sbit __at (0x90) T2; /* Timer 2 External Input */ - __sbit __at (0x91) T2EX; /* Timer 2 Capture/Reload */ -__sfr __at (0x91) EXIF; /* External Interrupt Flag */ -__sfr __at (0x92) MPAGE; /* Memory Page */ -__sfr __at (0x92) _XPAGE; /* XDATA/PDATA PAGE */ -__sfr __at (0x93) CADDR; /* Configuration Address Register */ -__sfr __at (0x94) CDATA; /* Configuration Data Register */ -__sfr __at (0x95) MCON; /* Memory Configuration */ -__sfr __at (0x98) SCON; /* Serial Control 0 */ -__sfr __at (0x98) SCON0; /* Serial Control 0 */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* |SM0|SM1|SM2|REN|TB8|RB8|TI |RI | */ - __sbit __at (0x98) RI; /* Receive Interrupt Flag */ - __sbit __at (0x98) RI0; /* Receive Interrupt Flag */ - __sbit __at (0x98) RI_0; /* Receive Interrupt Flag */ - __sbit __at (0x99) TI; /* Transmit Interrupt Flag */ - __sbit __at (0x99) TI0; /* Transmit Interrupt Flag */ - __sbit __at (0x99) TI_0; /* Transmit Interrupt Flag */ - __sbit __at (0x9a) RB8; /* Receive Bit 8 */ - __sbit __at (0x9a) RB8_0; /* Receive Bit 8 */ - __sbit __at (0x9b) TB8; /* Transmit Bit 8 */ - __sbit __at (0x9b) TB8_0; /* Transmit Bit 8 */ - __sbit __at (0x9c) REN; /* Receive Enable */ - __sbit __at (0x9c) REN_0; /* Receive Enable */ - __sbit __at (0x9d) SM2; /* Multiprocessor Communication Enable*/ - __sbit __at (0x9d) SM2_0; /* Multiprocessor Communication Enable*/ - __sbit __at (0x9e) SM1; /* Serial Port Select Mode 1 */ - __sbit __at (0x9e) SM1_0; /* Serial Port Select Mode 1 */ - __sbit __at (0x9f) SM0; /* Serial Port Select Mode 0 */ - __sbit __at (0x9f) SM0_0; /* Serial Port Select Mode 0 */ -__sfr __at (0x99) SBUF; /* Serial Buffer 0 */ -__sfr __at (0x99) SBUF0; /* Serial Buffer 0 */ -__sfr __at (0x9a) SPICON; /* SPI Control */ -__sfr __at (0x9a) I2CCON; /* I2C Control */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* |SCLK2|SCLK1|SCLK0|FIFO|ORDER|MSTR|CPHA|CPOL| */ - __sbit __at (0x9a) CPOL; /* Serial Clock Polarity */ - __sbit __at (0x9b) CPHA; /* Serial Clock Phase Control */ - __sbit __at (0x9c) MSTR; /* Set Master Mode */ - __sbit __at (0x9d) ORDER; /* Set Bit Order Transmit/Receive */ - __sbit __at (0x9e) FIFO; /* Enable Fifo Buffer */ - __sbit __at (0x9f) SCLK0; /* Clock Divider Select 0 */ - __sbit __at (0xa0) SCLK1; /* Clock Divider Select 1 */ - __sbit __at (0xa1) SCLK2; /* Clock Divider Select 2 */ -__sfr __at (0x9b) SPIDATA; /* SPI Data */ -__sfr __at (0x9b) I2CDATA; /* I2C Data */ -__sfr __at (0x9c) SPIRCON; /* SPI Receive Control */ -__sfr __at (0x9c) I2CGM; /* I2C GM Register */ -__sfr __at (0x9d) SPITCON; /* SPI Transmit Control */ -__sfr __at (0x9d) I2CSTAT; /* I2C Status */ -__sfr __at (0x9e) SPISTART; /* SPI Buffer Start Address */ -__sfr __at (0x9e) I2CSTART; /* I2C Start */ -__sfr __at (0x9f) SPIEND; /* SPI Buffer End Address */ -__sfr __at (0xa0) P2; /* Port 2 */ -__sfr __at (0xa1) PWMCON; /* PWM Control */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* | | |PPOL|PWMSEL|SPDSEL|TPCNTL2|TPCNTL1|TPCNTL0| */ - __sbit __at (0xa1) TPCNTL0; /* Generator Control */ - __sbit __at (0xa2) TPCNTL1; /* Generator Control */ - __sbit __at (0xa3) TPCNTL2; /* Generator Control */ - __sbit __at (0xa4) SPDSEL; /* Speed Selection */ - __sbit __at (0xa5) PWMSEL; /* PWM Register Select */ - __sbit __at (0xa6) PPOL; /* Period Polarity */ -__sfr __at (0xa2) PWMLOW; /* PWM low byte */ -__sfr __at (0xa2) TONELOW; /* Tone low byte */ -__sfr __at (0xa3) PWMHI; /* PWM high byte */ -__sfr __at (0xa3) TONEHI; /* Tone high byte */ -__sfr __at (0xa4) AIPOL; /* Auxiliary Interrupt Poll */ -__sfr __at (0xa5) PAI; /* Pending Auxiliary Interrupt */ -__sfr __at (0xa6) AIE; /* Auxiliary Interrupt Enable */ -__sfr __at (0xa7) AISTAT; /* Auxiliary Interrupt Status */ -__sfr __at (0xa8) IE; /* Interrupt Enable */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* |EA |ES1|ET2|ES0|ET1|EX1|ET0|EX0| */ - __sbit __at (0xa8) EX0; /* Enable External Interrupt 0 */ - __sbit __at (0xa9) ET0; /* Enable Timer 0 Interrupt */ - __sbit __at (0xaa) EX1; /* Enable External Interrupt 1 */ - __sbit __at (0xab) ET1; /* Enable Timer 1 Interrupt */ - __sbit __at (0xac) ES0; /* Enable Serial Port 0 Interrupt */ - __sbit __at (0xad) ET2; /* Enable Timer 2 Interrupt */ - __sbit __at (0xae) ES1; /* Enable Serial Port 1 Interrupt */ - __sbit __at (0xaf) EA; /* Global Interrupt Enable */ -__sfr __at (0xa9) BPCON; /* Breakpoint Control */ -__sfr __at (0xaa) BPL; /* Breakpoint Address Low */ -__sfr __at (0xab) BPH; /* Breakpoint Address High */ -__sfr __at (0xac) P0DDRL; /* Port 0 Data Direction Low */ -__sfr __at (0xad) P0DDRH; /* Port 0 Data Direction High */ -__sfr __at (0xae) P1DDRL; /* Port 1 Data Direction Low */ -__sfr __at (0xaf) P1DDRH; /* Port 1 Data Direction High */ -__sfr __at (0xb0) P3; /* Port 3 */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* |RD |WR |T1 |T0 |INT1|INT0|TXD|RXD| */ - __sbit __at (0xb0) RXD; /* Serial Port 0 Receive */ - __sbit __at (0xb0) RXD0; /* Serial Port 0 Receive */ - __sbit __at (0xb1) TXD; /* Serial Port 0 Transmit */ - __sbit __at (0xb1) TXD0; /* Serial Port 0 Transmit */ - __sbit __at (0xb2) INT0; /* External Interrupt 0 */ - __sbit __at (0xb3) INT1; /* External Interrupt 1 */ - __sbit __at (0xb4) T0; /* Timer 0 External Input */ - __sbit __at (0xb5) T1; /* Timer 1 External Input */ - __sbit __at (0xb6) WR; /* External Memory Write Strobe */ - __sbit __at (0xb7) RD; /* External Memory Read Strobe */ -__sfr __at (0xb1) P2DDRL; /* Port 2 Data Direction Low */ -__sfr __at (0xb2) P2DDRH; /* Port 2 Data Direction High */ -__sfr __at (0xb3) P3DDRL; /* Port 3 Data Direction Low */ -__sfr __at (0xb4) P3DDRH; /* Port 3 Data Direction High */ -__sfr __at (0xb5) DACL; /* Digital-to-Analog Converter Low */ -__sfr __at (0xb6) DACH; /* Digital-to-Analog Converter High */ -__sfr __at (0xb7) DACSEL; /* Digital-to-Analog Converter Select */ -__sfr __at (0xb8) IP; /* Interrupt Priority */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* | | |PT2|PS |PT1|PX1|PT0|PX0| */ - __sbit __at (0xb8) PX0; /* External Interrupt 0 */ - __sbit __at (0xb9) PT0; /* Timer 0 */ - __sbit __at (0xba) PX1; /* External Interrupt 1 */ - __sbit __at (0xbb) PT1; /* Timer 1 */ - __sbit __at (0xbc) PS; /* Serial Port */ - __sbit __at (0xbd) PT2; /* Timer 2 */ -__sfr __at (0xc0) SCON1; /* Serial Control 1 */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* |SM0|SM1|SM2|REN|TB8|RB8|TI |RI | */ - __sbit __at (0xc0) RI1; /* Receive Interrupt Flag */ - __sbit __at (0xc0) RI_1; /* Receive Interrupt Flag */ - __sbit __at (0xc1) TI1; /* Transmit Interrupt Flag */ - __sbit __at (0xc1) TI_1; /* Transmit Interrupt Flag */ - __sbit __at (0xc2) RB8_1; /* Receive Bit 8 */ - __sbit __at (0xc3) TB8_1; /* Transmit Bit 8 */ - __sbit __at (0xc4) REN_1; /* Receive Enable */ - __sbit __at (0xc5) SM2_1; /* Multiprocessor Communication Enable*/ - __sbit __at (0xc6) SM1_1; /* Serial Port Select Mode 1 */ - __sbit __at (0xc7) SM0_1; /* Serial Port Select Mode 0 */ -__sfr __at (0xc1) SBUF1; /* Serial Buffer 1 */ -__sfr __at (0xc6) EWU; /* Enable Wake Up */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* | | | | | |EWUEX1|EWUEX0|EWUWDT| */ - __sbit __at (0xc6) EWUWDT; /* Enable Watchdog Interrupt */ - __sbit __at (0xc7) EWUEX0; /* Enable External Interrupt 0 */ - __sbit __at (0xc8) EWUEX1; /* Enable External Interrupt 1 */ -__sfr __at (0xc7) SYSCLK; /* System Clock Divider */ -__sfr __at (0xc8) T2CON; /* Timer 2 Control */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* |TF2|EXF2|RCLK|TCLK|EXEN2|TR2|C_T2|CP_RL2 | */ - __sbit __at (0xc8) CP_RL2; /* Capture/Reload Flag */ - __sbit __at (0xc9) C_T2; /* Overflow Flag */ - __sbit __at (0xca) TR2; /* Timer Run */ - __sbit __at (0xcb) EXEN2; /* Timer External Enable */ - __sbit __at (0xcc) TCLK; /* Transmit Clock Flag */ - __sbit __at (0xcd) RCLK; /* Receive Clock Flag */ - __sbit __at (0xce) EXF2; /* External Flag */ - __sbit __at (0xcf) TF2; /* Overflow Flag */ -__sfr __at (0xca) RCAP2L; /* Timer 2 Capture Low */ -__sfr __at (0xcb) RCAP2H; /* Timer 2 Capture High */ -__sfr __at (0xcc) TL2; /* Timer 2 Low byte */ -__sfr __at (0xcd) TH2; /* Timer 2 High byte */ -__sfr __at (0xd0) PSW; /* Program Status Word */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* |CY |AC |F0 |RS1|RS0|OV |F1 |P | */ - __sbit __at (0xd0) P; /* Parity Flag */ - __sbit __at (0xd1) F1; /* General Purpose User Flag 1 */ - __sbit __at (0xd2) OV; /* Overflow Flag */ - __sbit __at (0xd3) RS0; /* Register Bank Select 0 Flag */ - __sbit __at (0xd4) RS1; /* Register Bank Select 1 Flag */ - __sbit __at (0xd5) F0; /* General Purpose User Flag 0 */ - __sbit __at (0xd6) AC; /* Auxiliary Carry Flag */ - __sbit __at (0xd7) CY; /* Carry Flag */ -__sfr __at (0xd1) OCL; /* (ADC) Offset Calibration Low byte */ -__sfr __at (0xd2) OCM; /* (ADC) Offset Calibration Middle byte */ -__sfr __at (0xd3) OCH; /* (ADC) Offset Calibration High byte */ -__sfr __at (0xd4) GCL; /* (ADC) Gain Low byte */ -__sfr __at (0xd5) GCM; /* (ADC) Gain Middle byte */ -__sfr __at (0xd6) GCH; /* (ADC) Gain High byte */ -__sfr __at (0xd7) ADMUX; /* ADC Multiplexer Register */ -__sfr __at (0xd8) EICON; /* Enable Interrupt Control */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* |SMOD1| |EAI|AI |WDTI| | | | */ - __sbit __at (0xdb) WDTI; /* Watchdog Timer Interrupt Flag */ - __sbit __at (0xdc) AI; /* Auxiliary Interrupt Flag */ - __sbit __at (0xdd) EAI; /* Enable Auxiliary Interrupt */ - __sbit __at (0xdf) SMOD1; /* Serial Port 1 Mode */ -__sfr __at (0xd9) ADRESL; /* ADC Conversion Result Low byte */ -__sfr __at (0xda) ADRESM; /* ADC Conversion Result Middle byte */ -__sfr __at (0xdb) ADRESH; /* ADC Conversion Result High byte */ -__sfr __at (0xdc) ADCON0; /* ADC Control 0 */ -__sfr __at (0xdd) ADCON1; /* ADC Control 1 */ -__sfr __at (0xde) ADCON2; /* ADC Control 2 */ -__sfr __at (0xdf) ADCON3; /* ADC Control 3 */ -__sfr __at (0xe0) ACC; /* Accumulator */ -__sfr __at (0xe1) SSCON; /* Summation and Shift Control */ -__sfr __at (0xe2) SUMR0; /* Summation Register 0 (LSB) */ -__sfr __at (0xe3) SUMR1; /* Summation Register 1 */ -__sfr __at (0xe4) SUMR2; /* Summation Register 2 */ -__sfr __at (0xe5) SUMR3; /* Summation Register 3 (MSB) */ -__sfr __at (0xe6) ODAC; /* (ADC) Offset DAC Register */ -__sfr __at (0xe7) LVDCON; /* Low Voltage Detection Control */ -__sfr __at (0xe8) EIE; /* Extended Interrupt Enable */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* | | | |EWDI|EX5|EX4|EX3|EX2| */ - __sbit __at (0xe8) EX2; /* Enable External Interrupt 2 */ - __sbit __at (0xe9) EX3; /* Enable External Interrupt 3 */ - __sbit __at (0xea) EX4; /* Enable External Interrupt 4 */ - __sbit __at (0xeb) EX5; /* Enable External Interrupt 5 */ - __sbit __at (0xec) EWDI; /* Enable Watchdog Interrupt */ -__sfr __at (0xe9) HWPC0; /* Hardware Product Code 0 */ -__sfr __at (0xea) HWPC1; /* Hardware Product Code 1 */ -__sfr __at (0xeb) HWVER; /* Hardware Version number */ -__sfr __at (0xee) FMCON; /* Flash Memory Control */ -__sfr __at (0xef) FTCON; /* Flash Memory Timing Control */ -__sfr __at (0xf0) B; /* B Register */ -__sfr __at (0xf1) PDCON; /* Power Down Control */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* | | | |PDPWM|PDAD|PDWDT|PDST|PDSPI| */ - __sbit __at (0xf1) PDSPI; /* SPI System Control */ - __sbit __at (0xf2) PDST; /* System Timer Control */ - __sbit __at (0xf3) PDWDT; /* Watchdog Timer Control */ - __sbit __at (0xf4) PDAD; /* A/D Control */ - __sbit __at (0xf5) PDPWM; /* PWM Control */ -__sfr __at (0xf2) PASEL; /* /PSEN|ALE Select */ -__sfr __at (0xf6) ACLK; /* Analog Clock */ -__sfr __at (0xf7) SRST; /* System Reset Register */ -__sfr __at (0xf8) EIP; /* Extended Interrupt Priority */ - /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ - /* | | | |PWDI|PX5|PX4|PX3|PX2| */ - __sbit __at (0xf8) PX2; /* External Interrupt 2 Priority */ - __sbit __at (0xf9) PX3; /* External Interrupt 3 Priority */ - __sbit __at (0xfa) PX4; /* External Interrupt 4 Priority */ - __sbit __at (0xfb) PX5; /* External Interrupt 5 Priority */ - __sbit __at (0xfc) PWDI; /* Watchdog Interrupt Priority */ -__sfr __at (0xf9) SECINT; /* Seconds Timer Interrupt */ -__sfr __at (0xfa) MSINT; /* Milliseconds Interrupt */ -__sfr __at (0xfb) USEC; /* Microsecond Register */ -__sfr __at (0xfc) MSECL; /* Millisecond Low byte */ -__sfr __at (0xfd) MSECH; /* Millisecond High byte */ -__sfr __at (0xfe) HMSEC; /* Hundred Millisecond Clock */ -__sfr __at (0xff) WDTCON; /* Watchdog Control */ - -/* Word Registers */ -__sfr16 __at (0x8c8a) TMR0; -__sfr16 __at (0x8d8b) TMR1; -__sfr16 __at (0xa3a2) PWM; -__sfr16 __at (0xa3a2) TONE; -__sfr16 __at (0xabaa) BP; -__sfr16 __at (0xabaa) BREAKPT; -__sfr16 __at (0xadac) P0DDR; -__sfr16 __at (0xafae) P1DDR; -__sfr16 __at (0xb2b1) P2DDR; -__sfr16 __at (0xb4b3) P3DDR; -__sfr16 __at (0xcbca) RCAP2; -__sfr16 __at (0xcdcc) TMR2; -__sfr16 __at (0xdfde) DECIMATION; -__sfr16 __at (0xfdfc) ONEMS; -__sfr16 __at (0xfdfc) MSEC; - -/* Double Word Registers */ -__sfr32 __at (0xe5e4e3e2) SUMR; - -#endif +/*-------------------------------------------------------------------------- + * Register Declarations for Texas Intruments MSC12xx MCU family + * + * Written By - Philippe Latu / philippe.latu(at)linux-france.org + * $Id$ + * + * Copyright (C) 2006 Philippe Latu + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + * + *---------------------------------------------------------------------------*/ + +#ifndef __MSC1210_H__ +#define __MSC1210_H__ + +/* BYTE Registers with bit definitions */ + +__sfr __at (0x80) P0; /* Port 0 */ +__sfr __at (0x81) SP; /* Stack Pointer */ +__sfr __at (0x82) DPL; /* Data Pointer 0: low byte */ +__sfr __at (0x82) DPL0; /* Data Pointer 0: low byte */ +__sfr __at (0x83) DPH; /* Data Pointer 0: high byte */ +__sfr __at (0x83) DPH0; /* Data Pointer 0: high byte */ +__sfr __at (0x84) DPL1; /* Data Pointer 1: low byte */ +__sfr __at (0x85) DPH1; /* Data Pointer 1: high byte */ +__sfr __at (0x86) DPS; /* Data Pointer Select */ +__sfr __at (0x87) PCON; /* Power Control */ +__sfr __at (0x88) TCON; /* Timer Control */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* |TF1|TR1|TF0|TR0|IE1|IT1|IE0|IT0| */ + __sbit __at (0x88) IT0; /* External Interrupt 0 Type */ + __sbit __at (0x89) IE0; /* External Interrupt 0 Edge Flag */ + __sbit __at (0x8a) IT1; /* External Interrupt 1 Type */ + __sbit __at (0x8b) IE1; /* External Interrupt 1 Edge Flag */ + __sbit __at (0x8c) TR0; /* Timer 0 On/Off Control */ + __sbit __at (0x8d) TF0; /* Timer 0 Overflow Flag */ + __sbit __at (0x8e) TR1; /* Timer 1 On/Off Control */ + __sbit __at (0x8f) TF1; /* Timer 1 Overflow Flag */ +__sfr __at (0x89) TMOD; /* Timer Mode */ +__sfr __at (0x8a) TL0; /* Timer 0: low byte */ +__sfr __at (0x8b) TL1; /* Timer 1: low byte */ +__sfr __at (0x8c) TH0; /* Timer 0: high byte */ +__sfr __at (0x8d) TH1; /* Timer 1: high byte */ +__sfr __at (0x8e) CKCON; /* Clock Control */ +__sfr __at (0x8f) MWS; /* Memory Write Select */ +__sfr __at (0x90) P1; /* Port 1 */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* | | | | | | |T2EX|T2 | */ + __sbit __at (0x90) T2; /* Timer 2 External Input */ + __sbit __at (0x91) T2EX; /* Timer 2 Capture/Reload */ +__sfr __at (0x91) EXIF; /* External Interrupt Flag */ +__sfr __at (0x92) MPAGE; /* Memory Page */ +__sfr __at (0x92) _XPAGE; /* XDATA/PDATA PAGE */ +__sfr __at (0x93) CADDR; /* Configuration Address Register */ +__sfr __at (0x94) CDATA; /* Configuration Data Register */ +__sfr __at (0x95) MCON; /* Memory Configuration */ +__sfr __at (0x98) SCON; /* Serial Control 0 */ +__sfr __at (0x98) SCON0; /* Serial Control 0 */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* |SM0|SM1|SM2|REN|TB8|RB8|TI |RI | */ + __sbit __at (0x98) RI; /* Receive Interrupt Flag */ + __sbit __at (0x98) RI0; /* Receive Interrupt Flag */ + __sbit __at (0x98) RI_0; /* Receive Interrupt Flag */ + __sbit __at (0x99) TI; /* Transmit Interrupt Flag */ + __sbit __at (0x99) TI0; /* Transmit Interrupt Flag */ + __sbit __at (0x99) TI_0; /* Transmit Interrupt Flag */ + __sbit __at (0x9a) RB8; /* Receive Bit 8 */ + __sbit __at (0x9a) RB8_0; /* Receive Bit 8 */ + __sbit __at (0x9b) TB8; /* Transmit Bit 8 */ + __sbit __at (0x9b) TB8_0; /* Transmit Bit 8 */ + __sbit __at (0x9c) REN; /* Receive Enable */ + __sbit __at (0x9c) REN_0; /* Receive Enable */ + __sbit __at (0x9d) SM2; /* Multiprocessor Communication Enable*/ + __sbit __at (0x9d) SM2_0; /* Multiprocessor Communication Enable*/ + __sbit __at (0x9e) SM1; /* Serial Port Select Mode 1 */ + __sbit __at (0x9e) SM1_0; /* Serial Port Select Mode 1 */ + __sbit __at (0x9f) SM0; /* Serial Port Select Mode 0 */ + __sbit __at (0x9f) SM0_0; /* Serial Port Select Mode 0 */ +__sfr __at (0x99) SBUF; /* Serial Buffer 0 */ +__sfr __at (0x99) SBUF0; /* Serial Buffer 0 */ +__sfr __at (0x9a) SPICON; /* SPI Control */ +__sfr __at (0x9a) I2CCON; /* I2C Control */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* |SCLK2|SCLK1|SCLK0|FIFO|ORDER|MSTR|CPHA|CPOL| */ + __sbit __at (0x9a) CPOL; /* Serial Clock Polarity */ + __sbit __at (0x9b) CPHA; /* Serial Clock Phase Control */ + __sbit __at (0x9c) MSTR; /* Set Master Mode */ + __sbit __at (0x9d) ORDER; /* Set Bit Order Transmit/Receive */ + __sbit __at (0x9e) FIFO; /* Enable Fifo Buffer */ + __sbit __at (0x9f) SCLK0; /* Clock Divider Select 0 */ + __sbit __at (0xa0) SCLK1; /* Clock Divider Select 1 */ + __sbit __at (0xa1) SCLK2; /* Clock Divider Select 2 */ +__sfr __at (0x9b) SPIDATA; /* SPI Data */ +__sfr __at (0x9b) I2CDATA; /* I2C Data */ +__sfr __at (0x9c) SPIRCON; /* SPI Receive Control */ +__sfr __at (0x9c) I2CGM; /* I2C GM Register */ +__sfr __at (0x9d) SPITCON; /* SPI Transmit Control */ +__sfr __at (0x9d) I2CSTAT; /* I2C Status */ +__sfr __at (0x9e) SPISTART; /* SPI Buffer Start Address */ +__sfr __at (0x9e) I2CSTART; /* I2C Start */ +__sfr __at (0x9f) SPIEND; /* SPI Buffer End Address */ +__sfr __at (0xa0) P2; /* Port 2 */ +__sfr __at (0xa1) PWMCON; /* PWM Control */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* | | |PPOL|PWMSEL|SPDSEL|TPCNTL2|TPCNTL1|TPCNTL0| */ + __sbit __at (0xa1) TPCNTL0; /* Generator Control */ + __sbit __at (0xa2) TPCNTL1; /* Generator Control */ + __sbit __at (0xa3) TPCNTL2; /* Generator Control */ + __sbit __at (0xa4) SPDSEL; /* Speed Selection */ + __sbit __at (0xa5) PWMSEL; /* PWM Register Select */ + __sbit __at (0xa6) PPOL; /* Period Polarity */ +__sfr __at (0xa2) PWMLOW; /* PWM low byte */ +__sfr __at (0xa2) TONELOW; /* Tone low byte */ +__sfr __at (0xa3) PWMHI; /* PWM high byte */ +__sfr __at (0xa3) TONEHI; /* Tone high byte */ +__sfr __at (0xa4) AIPOL; /* Auxiliary Interrupt Poll */ +__sfr __at (0xa5) PAI; /* Pending Auxiliary Interrupt */ +__sfr __at (0xa6) AIE; /* Auxiliary Interrupt Enable */ +__sfr __at (0xa7) AISTAT; /* Auxiliary Interrupt Status */ +__sfr __at (0xa8) IE; /* Interrupt Enable */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* |EA |ES1|ET2|ES0|ET1|EX1|ET0|EX0| */ + __sbit __at (0xa8) EX0; /* Enable External Interrupt 0 */ + __sbit __at (0xa9) ET0; /* Enable Timer 0 Interrupt */ + __sbit __at (0xaa) EX1; /* Enable External Interrupt 1 */ + __sbit __at (0xab) ET1; /* Enable Timer 1 Interrupt */ + __sbit __at (0xac) ES0; /* Enable Serial Port 0 Interrupt */ + __sbit __at (0xad) ET2; /* Enable Timer 2 Interrupt */ + __sbit __at (0xae) ES1; /* Enable Serial Port 1 Interrupt */ + __sbit __at (0xaf) EA; /* Global Interrupt Enable */ +__sfr __at (0xa9) BPCON; /* Breakpoint Control */ +__sfr __at (0xaa) BPL; /* Breakpoint Address Low */ +__sfr __at (0xab) BPH; /* Breakpoint Address High */ +__sfr __at (0xac) P0DDRL; /* Port 0 Data Direction Low */ +__sfr __at (0xad) P0DDRH; /* Port 0 Data Direction High */ +__sfr __at (0xae) P1DDRL; /* Port 1 Data Direction Low */ +__sfr __at (0xaf) P1DDRH; /* Port 1 Data Direction High */ +__sfr __at (0xb0) P3; /* Port 3 */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* |RD |WR |T1 |T0 |INT1|INT0|TXD|RXD| */ + __sbit __at (0xb0) RXD; /* Serial Port 0 Receive */ + __sbit __at (0xb0) RXD0; /* Serial Port 0 Receive */ + __sbit __at (0xb1) TXD; /* Serial Port 0 Transmit */ + __sbit __at (0xb1) TXD0; /* Serial Port 0 Transmit */ + __sbit __at (0xb2) INT0; /* External Interrupt 0 */ + __sbit __at (0xb3) INT1; /* External Interrupt 1 */ + __sbit __at (0xb4) T0; /* Timer 0 External Input */ + __sbit __at (0xb5) T1; /* Timer 1 External Input */ + __sbit __at (0xb6) WR; /* External Memory Write Strobe */ + __sbit __at (0xb7) RD; /* External Memory Read Strobe */ +__sfr __at (0xb1) P2DDRL; /* Port 2 Data Direction Low */ +__sfr __at (0xb2) P2DDRH; /* Port 2 Data Direction High */ +__sfr __at (0xb3) P3DDRL; /* Port 3 Data Direction Low */ +__sfr __at (0xb4) P3DDRH; /* Port 3 Data Direction High */ +__sfr __at (0xb5) DACL; /* Digital-to-Analog Converter Low */ +__sfr __at (0xb6) DACH; /* Digital-to-Analog Converter High */ +__sfr __at (0xb7) DACSEL; /* Digital-to-Analog Converter Select */ +__sfr __at (0xb8) IP; /* Interrupt Priority */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* | | |PT2|PS |PT1|PX1|PT0|PX0| */ + __sbit __at (0xb8) PX0; /* External Interrupt 0 */ + __sbit __at (0xb9) PT0; /* Timer 0 */ + __sbit __at (0xba) PX1; /* External Interrupt 1 */ + __sbit __at (0xbb) PT1; /* Timer 1 */ + __sbit __at (0xbc) PS; /* Serial Port */ + __sbit __at (0xbd) PT2; /* Timer 2 */ +__sfr __at (0xc0) SCON1; /* Serial Control 1 */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* |SM0|SM1|SM2|REN|TB8|RB8|TI |RI | */ + __sbit __at (0xc0) RI1; /* Receive Interrupt Flag */ + __sbit __at (0xc0) RI_1; /* Receive Interrupt Flag */ + __sbit __at (0xc1) TI1; /* Transmit Interrupt Flag */ + __sbit __at (0xc1) TI_1; /* Transmit Interrupt Flag */ + __sbit __at (0xc2) RB8_1; /* Receive Bit 8 */ + __sbit __at (0xc3) TB8_1; /* Transmit Bit 8 */ + __sbit __at (0xc4) REN_1; /* Receive Enable */ + __sbit __at (0xc5) SM2_1; /* Multiprocessor Communication Enable*/ + __sbit __at (0xc6) SM1_1; /* Serial Port Select Mode 1 */ + __sbit __at (0xc7) SM0_1; /* Serial Port Select Mode 0 */ +__sfr __at (0xc1) SBUF1; /* Serial Buffer 1 */ +__sfr __at (0xc6) EWU; /* Enable Wake Up */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* | | | | | |EWUEX1|EWUEX0|EWUWDT| */ + __sbit __at (0xc6) EWUWDT; /* Enable Watchdog Interrupt */ + __sbit __at (0xc7) EWUEX0; /* Enable External Interrupt 0 */ + __sbit __at (0xc8) EWUEX1; /* Enable External Interrupt 1 */ +__sfr __at (0xc7) SYSCLK; /* System Clock Divider */ +__sfr __at (0xc8) T2CON; /* Timer 2 Control */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* |TF2|EXF2|RCLK|TCLK|EXEN2|TR2|C_T2|CP_RL2 | */ + __sbit __at (0xc8) CP_RL2; /* Capture/Reload Flag */ + __sbit __at (0xc9) C_T2; /* Overflow Flag */ + __sbit __at (0xca) TR2; /* Timer Run */ + __sbit __at (0xcb) EXEN2; /* Timer External Enable */ + __sbit __at (0xcc) TCLK; /* Transmit Clock Flag */ + __sbit __at (0xcd) RCLK; /* Receive Clock Flag */ + __sbit __at (0xce) EXF2; /* External Flag */ + __sbit __at (0xcf) TF2; /* Overflow Flag */ +__sfr __at (0xca) RCAP2L; /* Timer 2 Capture Low */ +__sfr __at (0xcb) RCAP2H; /* Timer 2 Capture High */ +__sfr __at (0xcc) TL2; /* Timer 2 Low byte */ +__sfr __at (0xcd) TH2; /* Timer 2 High byte */ +__sfr __at (0xd0) PSW; /* Program Status Word */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* |CY |AC |F0 |RS1|RS0|OV |F1 |P | */ + __sbit __at (0xd0) P; /* Parity Flag */ + __sbit __at (0xd1) F1; /* General Purpose User Flag 1 */ + __sbit __at (0xd2) OV; /* Overflow Flag */ + __sbit __at (0xd3) RS0; /* Register Bank Select 0 Flag */ + __sbit __at (0xd4) RS1; /* Register Bank Select 1 Flag */ + __sbit __at (0xd5) F0; /* General Purpose User Flag 0 */ + __sbit __at (0xd6) AC; /* Auxiliary Carry Flag */ + __sbit __at (0xd7) CY; /* Carry Flag */ +__sfr __at (0xd1) OCL; /* (ADC) Offset Calibration Low byte */ +__sfr __at (0xd2) OCM; /* (ADC) Offset Calibration Middle byte */ +__sfr __at (0xd3) OCH; /* (ADC) Offset Calibration High byte */ +__sfr __at (0xd4) GCL; /* (ADC) Gain Low byte */ +__sfr __at (0xd5) GCM; /* (ADC) Gain Middle byte */ +__sfr __at (0xd6) GCH; /* (ADC) Gain High byte */ +__sfr __at (0xd7) ADMUX; /* ADC Multiplexer Register */ +__sfr __at (0xd8) EICON; /* Enable Interrupt Control */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* |SMOD1| |EAI|AI |WDTI| | | | */ + __sbit __at (0xdb) WDTI; /* Watchdog Timer Interrupt Flag */ + __sbit __at (0xdc) AI; /* Auxiliary Interrupt Flag */ + __sbit __at (0xdd) EAI; /* Enable Auxiliary Interrupt */ + __sbit __at (0xdf) SMOD1; /* Serial Port 1 Mode */ +__sfr __at (0xd9) ADRESL; /* ADC Conversion Result Low byte */ +__sfr __at (0xda) ADRESM; /* ADC Conversion Result Middle byte */ +__sfr __at (0xdb) ADRESH; /* ADC Conversion Result High byte */ +__sfr __at (0xdc) ADCON0; /* ADC Control 0 */ +__sfr __at (0xdd) ADCON1; /* ADC Control 1 */ +__sfr __at (0xde) ADCON2; /* ADC Control 2 */ +__sfr __at (0xdf) ADCON3; /* ADC Control 3 */ +__sfr __at (0xe0) ACC; /* Accumulator */ +__sfr __at (0xe1) SSCON; /* Summation and Shift Control */ +__sfr __at (0xe2) SUMR0; /* Summation Register 0 (LSB) */ +__sfr __at (0xe3) SUMR1; /* Summation Register 1 */ +__sfr __at (0xe4) SUMR2; /* Summation Register 2 */ +__sfr __at (0xe5) SUMR3; /* Summation Register 3 (MSB) */ +__sfr __at (0xe6) ODAC; /* (ADC) Offset DAC Register */ +__sfr __at (0xe7) LVDCON; /* Low Voltage Detection Control */ +__sfr __at (0xe8) EIE; /* Extended Interrupt Enable */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* | | | |EWDI|EX5|EX4|EX3|EX2| */ + __sbit __at (0xe8) EX2; /* Enable External Interrupt 2 */ + __sbit __at (0xe9) EX3; /* Enable External Interrupt 3 */ + __sbit __at (0xea) EX4; /* Enable External Interrupt 4 */ + __sbit __at (0xeb) EX5; /* Enable External Interrupt 5 */ + __sbit __at (0xec) EWDI; /* Enable Watchdog Interrupt */ +__sfr __at (0xe9) HWPC0; /* Hardware Product Code 0 */ +__sfr __at (0xea) HWPC1; /* Hardware Product Code 1 */ +__sfr __at (0xeb) HWVER; /* Hardware Version number */ +__sfr __at (0xee) FMCON; /* Flash Memory Control */ +__sfr __at (0xef) FTCON; /* Flash Memory Timing Control */ +__sfr __at (0xf0) B; /* B Register */ +__sfr __at (0xf1) PDCON; /* Power Down Control */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* | | | |PDPWM|PDAD|PDWDT|PDST|PDSPI| */ + __sbit __at (0xf1) PDSPI; /* SPI System Control */ + __sbit __at (0xf2) PDST; /* System Timer Control */ + __sbit __at (0xf3) PDWDT; /* Watchdog Timer Control */ + __sbit __at (0xf4) PDAD; /* A/D Control */ + __sbit __at (0xf5) PDPWM; /* PWM Control */ +__sfr __at (0xf2) PASEL; /* /PSEN|ALE Select */ +__sfr __at (0xf6) ACLK; /* Analog Clock */ +__sfr __at (0xf7) SRST; /* System Reset Register */ +__sfr __at (0xf8) EIP; /* Extended Interrupt Priority */ + /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */ + /* | | | |PWDI|PX5|PX4|PX3|PX2| */ + __sbit __at (0xf8) PX2; /* External Interrupt 2 Priority */ + __sbit __at (0xf9) PX3; /* External Interrupt 3 Priority */ + __sbit __at (0xfa) PX4; /* External Interrupt 4 Priority */ + __sbit __at (0xfb) PX5; /* External Interrupt 5 Priority */ + __sbit __at (0xfc) PWDI; /* Watchdog Interrupt Priority */ +__sfr __at (0xf9) SECINT; /* Seconds Timer Interrupt */ +__sfr __at (0xfa) MSINT; /* Milliseconds Interrupt */ +__sfr __at (0xfb) USEC; /* Microsecond Register */ +__sfr __at (0xfc) MSECL; /* Millisecond Low byte */ +__sfr __at (0xfd) MSECH; /* Millisecond High byte */ +__sfr __at (0xfe) HMSEC; /* Hundred Millisecond Clock */ +__sfr __at (0xff) WDTCON; /* Watchdog Control */ + +/* Word Registers */ +__sfr16 __at (0x8c8a) TMR0; +__sfr16 __at (0x8d8b) TMR1; +__sfr16 __at (0xa3a2) PWM; +__sfr16 __at (0xa3a2) TONE; +__sfr16 __at (0xabaa) BP; +__sfr16 __at (0xabaa) BREAKPT; +__sfr16 __at (0xadac) P0DDR; +__sfr16 __at (0xafae) P1DDR; +__sfr16 __at (0xb2b1) P2DDR; +__sfr16 __at (0xb4b3) P3DDR; +__sfr16 __at (0xcbca) RCAP2; +__sfr16 __at (0xcdcc) TMR2; +__sfr16 __at (0xdfde) DECIMATION; +__sfr16 __at (0xfdfc) ONEMS; +__sfr16 __at (0xfdfc) MSEC; + +/* Double Word Registers */ +__sfr32 __at (0xe5e4e3e2) SUMR; + +#endif diff --git a/device/include/mcs51/serial_IO.h b/device/include/mcs51/serial_IO.h index 0922f952..d6d536a1 100644 --- a/device/include/mcs51/serial_IO.h +++ b/device/include/mcs51/serial_IO.h @@ -1,76 +1,76 @@ -/* Default putchar() and getchar() to the serial port - - Written By - Jesus Calvino-Fraga (October/2006) - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#ifndef SERIAL_IO_H -#define SERIAL_IO_H - -__sfr __at (0x87) SIO_PCON; -__sfr __at (0x89) SIO_TMOD; -__sfr __at (0x8D) SIO_TH1; -__sfr __at (0x8B) SIO_TL1; -__sfr __at (0x98) SIO_SCON; -__sfr __at (0x99) SIO_SBUF; -__sbit __at (0x8E) SIO_TR1; - -/*SCON bits*/ -__sbit __at (0x98) SIO_RI; -__sbit __at (0x99) SIO_TI; -__sbit __at (0x9A) SIO_RB8; -__sbit __at (0x9B) SIO_TB8; -__sbit __at (0x9C) SIO_REN; -__sbit __at (0x9D) SIO_SM2; -__sbit __at (0x9E) SIO_SM1; -__sbit __at (0x9F) SIO_SM0; - -void inituart (unsigned char t1_reload) -{ - SIO_TR1=0; - SIO_TMOD=(SIO_TMOD&0x0f)|0x20; - SIO_PCON|=0x80; - SIO_TH1=SIO_TL1=t1_reload; - SIO_TR1=1; - SIO_SCON=0x52; -} - -void putchar (char c) -{ - if((!SIO_SM0)&&(!SIO_SM1)) inituart(0xff); - if (c=='\n') - { - while (!SIO_TI); - SIO_TI=0; - SIO_SBUF='\r'; - } - while (!SIO_TI); - SIO_TI=0; - SIO_SBUF=c; -} - -char getchar (void) -{ - char c; - - if((!SIO_SM0)&&(!SIO_SM1)) inituart(0xff); - - while (!SIO_RI); - SIO_RI=0; - c=SIO_SBUF; - return c; -} -#endif +/* Default putchar() and getchar() to the serial port + + Written By - Jesus Calvino-Fraga (October/2006) + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#ifndef SERIAL_IO_H +#define SERIAL_IO_H + +__sfr __at (0x87) SIO_PCON; +__sfr __at (0x89) SIO_TMOD; +__sfr __at (0x8D) SIO_TH1; +__sfr __at (0x8B) SIO_TL1; +__sfr __at (0x98) SIO_SCON; +__sfr __at (0x99) SIO_SBUF; +__sbit __at (0x8E) SIO_TR1; + +/*SCON bits*/ +__sbit __at (0x98) SIO_RI; +__sbit __at (0x99) SIO_TI; +__sbit __at (0x9A) SIO_RB8; +__sbit __at (0x9B) SIO_TB8; +__sbit __at (0x9C) SIO_REN; +__sbit __at (0x9D) SIO_SM2; +__sbit __at (0x9E) SIO_SM1; +__sbit __at (0x9F) SIO_SM0; + +void inituart (unsigned char t1_reload) +{ + SIO_TR1=0; + SIO_TMOD=(SIO_TMOD&0x0f)|0x20; + SIO_PCON|=0x80; + SIO_TH1=SIO_TL1=t1_reload; + SIO_TR1=1; + SIO_SCON=0x52; +} + +void putchar (char c) +{ + if((!SIO_SM0)&&(!SIO_SM1)) inituart(0xff); + if (c=='\n') + { + while (!SIO_TI); + SIO_TI=0; + SIO_SBUF='\r'; + } + while (!SIO_TI); + SIO_TI=0; + SIO_SBUF=c; +} + +char getchar (void) +{ + char c; + + if((!SIO_SM0)&&(!SIO_SM1)) inituart(0xff); + + while (!SIO_RI); + SIO_RI=0; + c=SIO_SBUF; + return c; +} +#endif diff --git a/device/include/pic/errno.h b/device/include/pic/errno.h index 93e72d62..3336ea64 100644 --- a/device/include/pic/errno.h +++ b/device/include/pic/errno.h @@ -21,7 +21,7 @@ -------------------------------------------------------------------------*/ /* -** $Id: errno.h 3912 2005-10-26 11:08:11Z tecodev $ +** $Id$ */ #ifndef _PIC14_ERRNO_H diff --git a/device/include/pic/math.h b/device/include/pic/math.h index b93d4123..0cf95079 100644 --- a/device/include/pic/math.h +++ b/device/include/pic/math.h @@ -22,7 +22,7 @@ -------------------------------------------------------------------------*/ /* -** $Id: math.h 3648 2005-01-22 18:02:16Z vrokas $ +** $Id$ */ diff --git a/device/include/pic/sdcc-lib.h b/device/include/pic/sdcc-lib.h index df9f8ed7..8a3b5e5c 100644 --- a/device/include/pic/sdcc-lib.h +++ b/device/include/pic/sdcc-lib.h @@ -11,7 +11,7 @@ * The GNU PIC Library is maintained by, * Vangelis Rokas * - * $Id: sdcc-lib.h 3512 2004-10-01 14:32:06Z vrokas $ + * $Id$ * */ diff --git a/device/include/pic16/pic18f2620.h b/device/include/pic16/pic18f2620.h index d5f06577..d1ea81a2 100644 --- a/device/include/pic16/pic18f2620.h +++ b/device/include/pic16/pic18f2620.h @@ -19,7 +19,7 @@ * Vangelis Rokas * * - * $Id: $ + * $Id$ * */ diff --git a/device/include/pic16/pic18f4620.h b/device/include/pic16/pic18f4620.h index 950fea26..a2727dbd 100644 --- a/device/include/pic16/pic18f4620.h +++ b/device/include/pic16/pic18f4620.h @@ -14,7 +14,7 @@ * Added based on existing PICs * Gary Plumbridge * - * $Id: $ + * $Id$ * */ diff --git a/device/lib/ds390/putchar.c b/device/lib/ds390/putchar.c index b2df1d61..8a90f60b 100644 --- a/device/lib/ds390/putchar.c +++ b/device/lib/ds390/putchar.c @@ -1,36 +1,36 @@ -/*------------------------------------------------------------------------- - putchar.c - putchar implementation for DS80C390 - - Written By - Maarten Brock, sourceforge.brock@dse.nl - - This program is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by the - Free Software Foundation; either version 2, or (at your option) any - later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - - In other words, you are welcome to use, share and improve this program. - You are forbidden to forbid anyone else to use, share and improve - what you give them. Help stamp out software-hoarding! --------------------------------------------------------------------------*/ - -#include -#include - -void putchar (char c) -{ - Serial0PutChar(c); -} - -extern char getchar(void) -{ - return Serial0GetChar(); -} +/*------------------------------------------------------------------------- + putchar.c - putchar implementation for DS80C390 + + Written By - Maarten Brock, sourceforge.brock@dse.nl + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + In other words, you are welcome to use, share and improve this program. + You are forbidden to forbid anyone else to use, share and improve + what you give them. Help stamp out software-hoarding! +-------------------------------------------------------------------------*/ + +#include +#include + +void putchar (char c) +{ + Serial0PutChar(c); +} + +extern char getchar(void) +{ + return Serial0GetChar(); +} diff --git a/device/lib/ds390/rtc390.c b/device/lib/ds390/rtc390.c old mode 100755 new mode 100644 diff --git a/device/lib/incl.mk b/device/lib/incl.mk index 3128d979..5e7888ac 100644 --- a/device/lib/incl.mk +++ b/device/lib/incl.mk @@ -1 +1 @@ -MODELS = small medium large \ No newline at end of file +MODELS = small medium large diff --git a/device/lib/make51lib.bat b/device/lib/make51lib.bat index ee58c083..ec1773fa 100644 --- a/device/lib/make51lib.bat +++ b/device/lib/make51lib.bat @@ -1,37 +1,37 @@ -del small\*.lib -set SDCCLIB_CC=sdcc --use-stdout --model-small -c -sdcclib -l small\libfloat.lib libfloat.lib -sdcclib -l small\libint.lib libint.lib -sdcclib -l small\liblong.lib liblong.lib -sdcclib -l small\libsdcc.lib libsdcc.lib -cd mcs51 -@for %%I in (*.asm) do asx8051 -plosgff %%I -@for %%I in (*.rel) do sdcclib ..\small\mcs51.lib %%I -cd.. -del *.rel *.sym *.asm *.lst *.adb - -del medium\*.lib -set SDCCLIB_CC=sdcc --use-stdout --model-medium -c -sdcclib -l medium\libfloat.lib libfloat.lib -sdcclib -l medium\libint.lib libint.lib -sdcclib -l medium\liblong.lib liblong.lib -sdcclib -l medium\libsdcc.lib libsdcc.lib -cd mcs51 -@for %%I in (*.asm) do asx8051 -plosgff %%I -@for %%I in (*.rel) do sdcclib ..\medium\mcs51.lib %%I -cd.. -del *.rel *.sym *.asm *.lst *.adb - -del large\*.lib -set SDCCLIB_CC=sdcc --use-stdout --model-large -DUSE_FLOATS -c -sdcclib -l large\libfloat.lib libfloat.lib -sdcclib -l large\libint.lib libint.lib -sdcclib -l large\liblong.lib liblong.lib -sdcclib -l large\libsdcc.lib libsdcc.lib -cd mcs51 -@for %%I in (*.asm) do asx8051 -plosgff %%I -@for %%I in (*.rel) do sdcclib ..\large\mcs51.lib %%I -cd.. -del *.rel *.sym *.asm *.lst *.adb - +del small\*.lib +set SDCCLIB_CC=sdcc --use-stdout --model-small -c +sdcclib -l small\libfloat.lib libfloat.lib +sdcclib -l small\libint.lib libint.lib +sdcclib -l small\liblong.lib liblong.lib +sdcclib -l small\libsdcc.lib libsdcc.lib +cd mcs51 +@for %%I in (*.asm) do asx8051 -plosgff %%I +@for %%I in (*.rel) do sdcclib ..\small\mcs51.lib %%I +cd.. +del *.rel *.sym *.asm *.lst *.adb + +del medium\*.lib +set SDCCLIB_CC=sdcc --use-stdout --model-medium -c +sdcclib -l medium\libfloat.lib libfloat.lib +sdcclib -l medium\libint.lib libint.lib +sdcclib -l medium\liblong.lib liblong.lib +sdcclib -l medium\libsdcc.lib libsdcc.lib +cd mcs51 +@for %%I in (*.asm) do asx8051 -plosgff %%I +@for %%I in (*.rel) do sdcclib ..\medium\mcs51.lib %%I +cd.. +del *.rel *.sym *.asm *.lst *.adb + +del large\*.lib +set SDCCLIB_CC=sdcc --use-stdout --model-large -DUSE_FLOATS -c +sdcclib -l large\libfloat.lib libfloat.lib +sdcclib -l large\libint.lib libint.lib +sdcclib -l large\liblong.lib liblong.lib +sdcclib -l large\libsdcc.lib libsdcc.lib +cd mcs51 +@for %%I in (*.asm) do asx8051 -plosgff %%I +@for %%I in (*.rel) do sdcclib ..\large\mcs51.lib %%I +cd.. +del *.rel *.sym *.asm *.lst *.adb + set SDCCLIB_CC= \ No newline at end of file diff --git a/device/lib/pic/libm/acosf.c b/device/lib/pic/libm/acosf.c index c6993805..134c5fa3 100644 --- a/device/lib/pic/libm/acosf.c +++ b/device/lib/pic/libm/acosf.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: acosf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/asincosf.c b/device/lib/pic/libm/asincosf.c index cad72b75..1c845eaa 100644 --- a/device/lib/pic/libm/asincosf.c +++ b/device/lib/pic/libm/asincosf.c @@ -22,7 +22,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: asincosf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ diff --git a/device/lib/pic/libm/asinf.c b/device/lib/pic/libm/asinf.c index 869e0f50..c2928221 100644 --- a/device/lib/pic/libm/asinf.c +++ b/device/lib/pic/libm/asinf.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: asinf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/atan2f.c b/device/lib/pic/libm/atan2f.c index 2e0a4fbb..f5a87483 100644 --- a/device/lib/pic/libm/atan2f.c +++ b/device/lib/pic/libm/atan2f.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: atan2f.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/atanf.c b/device/lib/pic/libm/atanf.c index 5192e2a6..7680e5b3 100644 --- a/device/lib/pic/libm/atanf.c +++ b/device/lib/pic/libm/atanf.c @@ -22,7 +22,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: atanf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/ceilf.c b/device/lib/pic/libm/ceilf.c index 598630e6..a6343385 100644 --- a/device/lib/pic/libm/ceilf.c +++ b/device/lib/pic/libm/ceilf.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: ceilf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/cosf.c b/device/lib/pic/libm/cosf.c index 8d31b93c..4355be12 100644 --- a/device/lib/pic/libm/cosf.c +++ b/device/lib/pic/libm/cosf.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: cosf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/coshf.c b/device/lib/pic/libm/coshf.c index 1acdf2e1..4d1d9738 100644 --- a/device/lib/pic/libm/coshf.c +++ b/device/lib/pic/libm/coshf.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: coshf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/cotf.c b/device/lib/pic/libm/cotf.c index ae3090b1..cd52c68e 100644 --- a/device/lib/pic/libm/cotf.c +++ b/device/lib/pic/libm/cotf.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: cotf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/errno.c b/device/lib/pic/libm/errno.c index 2a33a842..031d2bef 100644 --- a/device/lib/pic/libm/errno.c +++ b/device/lib/pic/libm/errno.c @@ -19,7 +19,7 @@ -------------------------------------------------------------------------*/ /* -** $Id: errno.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ int errno; diff --git a/device/lib/pic/libm/expf.c b/device/lib/pic/libm/expf.c index 6f74e935..0a59823b 100644 --- a/device/lib/pic/libm/expf.c +++ b/device/lib/pic/libm/expf.c @@ -22,7 +22,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: expf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/fabsf.c b/device/lib/pic/libm/fabsf.c index 2d4fe796..f1bf04ad 100644 --- a/device/lib/pic/libm/fabsf.c +++ b/device/lib/pic/libm/fabsf.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: fabsf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/floorf.c b/device/lib/pic/libm/floorf.c index 6eeb708b..a9eea702 100644 --- a/device/lib/pic/libm/floorf.c +++ b/device/lib/pic/libm/floorf.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: floorf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/frexpf.c b/device/lib/pic/libm/frexpf.c index 36fe3503..b76201dd 100644 --- a/device/lib/pic/libm/frexpf.c +++ b/device/lib/pic/libm/frexpf.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: frexpf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/ldexpf.c b/device/lib/pic/libm/ldexpf.c index 014dec54..f6f6e68c 100644 --- a/device/lib/pic/libm/ldexpf.c +++ b/device/lib/pic/libm/ldexpf.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: ldexpf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/log10f.c b/device/lib/pic/libm/log10f.c index 03d50443..7c18d7b6 100644 --- a/device/lib/pic/libm/log10f.c +++ b/device/lib/pic/libm/log10f.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: log10f.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/logf.c b/device/lib/pic/libm/logf.c index 0ba3f8b3..3c3e6f8f 100644 --- a/device/lib/pic/libm/logf.c +++ b/device/lib/pic/libm/logf.c @@ -22,7 +22,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: logf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/modff.c b/device/lib/pic/libm/modff.c index 3aae5fd1..544062d1 100644 --- a/device/lib/pic/libm/modff.c +++ b/device/lib/pic/libm/modff.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: modff.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/powf.c b/device/lib/pic/libm/powf.c index b6b941eb..77f768f5 100644 --- a/device/lib/pic/libm/powf.c +++ b/device/lib/pic/libm/powf.c @@ -20,7 +20,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: powf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/sincosf.c b/device/lib/pic/libm/sincosf.c index 5a741567..9ddee4ec 100644 --- a/device/lib/pic/libm/sincosf.c +++ b/device/lib/pic/libm/sincosf.c @@ -22,7 +22,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: sincosf.c 3714 2005-04-02 13:13:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/sincoshf.c b/device/lib/pic/libm/sincoshf.c index 1043bdc2..87de5d13 100644 --- a/device/lib/pic/libm/sincoshf.c +++ b/device/lib/pic/libm/sincoshf.c @@ -22,7 +22,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: sincoshf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/sinf.c b/device/lib/pic/libm/sinf.c index 3d0ed8a2..0d546b14 100644 --- a/device/lib/pic/libm/sinf.c +++ b/device/lib/pic/libm/sinf.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: sinf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/sinhf.c b/device/lib/pic/libm/sinhf.c index 5d81c5fa..d3386a5c 100644 --- a/device/lib/pic/libm/sinhf.c +++ b/device/lib/pic/libm/sinhf.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: sinhf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/sqrtf.c b/device/lib/pic/libm/sqrtf.c index a35e6009..bc04b613 100644 --- a/device/lib/pic/libm/sqrtf.c +++ b/device/lib/pic/libm/sqrtf.c @@ -22,7 +22,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: sqrtf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/tancotf.c b/device/lib/pic/libm/tancotf.c index 60e3ada7..cf529099 100644 --- a/device/lib/pic/libm/tancotf.c +++ b/device/lib/pic/libm/tancotf.c @@ -22,7 +22,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: tancotf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/tanf.c b/device/lib/pic/libm/tanf.c index 4e1bcfa2..bd247ef4 100644 --- a/device/lib/pic/libm/tanf.c +++ b/device/lib/pic/libm/tanf.c @@ -19,7 +19,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: tanf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libm/tanhf.c b/device/lib/pic/libm/tanhf.c index d46a8b01..27488d94 100644 --- a/device/lib/pic/libm/tanhf.c +++ b/device/lib/pic/libm/tanhf.c @@ -22,7 +22,7 @@ /* Version 1.0 - Initial release */ /* -** $Id: tanhf.c 3654 2005-01-24 10:38:53Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libsdcc/fs2schar.c b/device/lib/pic/libsdcc/fs2schar.c index 387b0c46..a482b2d8 100644 --- a/device/lib/pic/libsdcc/fs2schar.c +++ b/device/lib/pic/libsdcc/fs2schar.c @@ -26,7 +26,7 @@ -------------------------------------------------------------------------*/ /* -** $Id: fs2schar.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ diff --git a/device/lib/pic/libsdcc/fs2sint.c b/device/lib/pic/libsdcc/fs2sint.c index e6fe0e95..82265249 100644 --- a/device/lib/pic/libsdcc/fs2sint.c +++ b/device/lib/pic/libsdcc/fs2sint.c @@ -27,7 +27,7 @@ /* -** $Id: fs2sint.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ diff --git a/device/lib/pic/libsdcc/fs2slong.c b/device/lib/pic/libsdcc/fs2slong.c index ef46b6c3..6f9d61da 100644 --- a/device/lib/pic/libsdcc/fs2slong.c +++ b/device/lib/pic/libsdcc/fs2slong.c @@ -26,7 +26,7 @@ -------------------------------------------------------------------------*/ /* -** $Id: fs2slong.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libsdcc/fs2uchar.c b/device/lib/pic/libsdcc/fs2uchar.c index cf963716..6d8d431e 100644 --- a/device/lib/pic/libsdcc/fs2uchar.c +++ b/device/lib/pic/libsdcc/fs2uchar.c @@ -26,7 +26,7 @@ -------------------------------------------------------------------------*/ /* -** $Id: fs2uchar.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libsdcc/fs2uint.c b/device/lib/pic/libsdcc/fs2uint.c index 16084456..0313c68d 100644 --- a/device/lib/pic/libsdcc/fs2uint.c +++ b/device/lib/pic/libsdcc/fs2uint.c @@ -26,7 +26,7 @@ -------------------------------------------------------------------------*/ /* -** $Id: fs2uint.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libsdcc/fs2ulong.c b/device/lib/pic/libsdcc/fs2ulong.c index fd34c445..cf47d4b7 100644 --- a/device/lib/pic/libsdcc/fs2ulong.c +++ b/device/lib/pic/libsdcc/fs2ulong.c @@ -15,7 +15,7 @@ */ /* -** $Id: fs2ulong.c 3711 2005-03-31 16:25:17Z vrokas $ +** $Id$ */ /* (c)2000/2001: hacked a little by johan.knol@iduna.nl for sdcc */ diff --git a/device/lib/pic/libsdcc/fsadd.c b/device/lib/pic/libsdcc/fsadd.c index bda18264..56fd5fa9 100644 --- a/device/lib/pic/libsdcc/fsadd.c +++ b/device/lib/pic/libsdcc/fsadd.c @@ -15,7 +15,7 @@ */ /* -** $Id: fsadd.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libsdcc/fsdiv.c b/device/lib/pic/libsdcc/fsdiv.c index beb6607d..f4a44e6b 100644 --- a/device/lib/pic/libsdcc/fsdiv.c +++ b/device/lib/pic/libsdcc/fsdiv.c @@ -1,106 +1,106 @@ -/* -** libgcc support for software floating point. -** Copyright (C) 1991 by Pipeline Associates, Inc. All rights reserved. -** Permission is granted to do *anything* you want with this file, -** commercial or otherwise, provided this message remains intact. So there! -** I would appreciate receiving any updates/patches/changes that anyone -** makes, and am willing to be the repository for said changes (am I -** making a big mistake?). -** -** Pat Wood -** Pipeline Associates, Inc. -** pipeline!phw@motown.com or -** sun!pipeline!phw or -** uunet!motown!pipeline!phw -*/ - -/* -** $Id: fsdiv.c 3513 2004-10-01 14:49:51Z vrokas $ -*/ - -/* (c)2000/2001: hacked a little by johan.knol@iduna.nl for sdcc */ - -#include - -union float_long - { - float f; - long l; - }; - -/* divide two floats */ -float __fsdiv (float a1, float a2) _FS_REENTRANT -{ - FS_STATIC volatile union float_long fl1, fl2; - long result; - unsigned long mask; - long mant1, mant2; - int exp ; - char sign; - - fl1.f = a1; - fl2.f = a2; - - /* subtract exponents */ - exp = EXP (fl1.l) ; - exp -= EXP (fl2.l); - exp += EXCESS; - - /* compute sign */ - sign = SIGN (fl1.l) ^ SIGN (fl2.l); - - /* divide by zero??? */ - if (!fl2.l) - {/* return NaN or -NaN */ - fl2.l = 0x7FC00000; - return (fl2.f); - } - - /* numerator zero??? */ - if (!fl1.l) - return (0); - - /* now get mantissas */ - mant1 = MANT (fl1.l); - mant2 = MANT (fl2.l); - - /* this assures we have 25 bits of precision in the end */ - if (mant1 < mant2) - { - mant1 <<= 1; - exp--; - } - - /* now we perform repeated subtraction of fl2.l from fl1.l */ - mask = 0x1000000; - result = 0; - while (mask) - { - if (mant1 >= mant2) - { - result |= mask; - mant1 -= mant2; - } - mant1 <<= 1; - mask >>= 1; - } - - /* round */ - result += 1; - - /* normalize down */ - exp++; - result >>= 1; - - result &= ~HIDDEN; - - /* pack up and go home */ - if (exp >= 0x100) - fl1.l = (sign ? SIGNBIT : 0) | 0x7F800000; - else if (exp < 0) - fl1.l = 0; - else - fl1.l = PACK (sign ? SIGNBIT : 0 , exp, result); - return (fl1.f); -} - +/* +** libgcc support for software floating point. +** Copyright (C) 1991 by Pipeline Associates, Inc. All rights reserved. +** Permission is granted to do *anything* you want with this file, +** commercial or otherwise, provided this message remains intact. So there! +** I would appreciate receiving any updates/patches/changes that anyone +** makes, and am willing to be the repository for said changes (am I +** making a big mistake?). +** +** Pat Wood +** Pipeline Associates, Inc. +** pipeline!phw@motown.com or +** sun!pipeline!phw or +** uunet!motown!pipeline!phw +*/ + +/* +** $Id$ +*/ + +/* (c)2000/2001: hacked a little by johan.knol@iduna.nl for sdcc */ + +#include + +union float_long + { + float f; + long l; + }; + +/* divide two floats */ +float __fsdiv (float a1, float a2) _FS_REENTRANT +{ + FS_STATIC volatile union float_long fl1, fl2; + long result; + unsigned long mask; + long mant1, mant2; + int exp ; + char sign; + + fl1.f = a1; + fl2.f = a2; + + /* subtract exponents */ + exp = EXP (fl1.l) ; + exp -= EXP (fl2.l); + exp += EXCESS; + + /* compute sign */ + sign = SIGN (fl1.l) ^ SIGN (fl2.l); + + /* divide by zero??? */ + if (!fl2.l) + {/* return NaN or -NaN */ + fl2.l = 0x7FC00000; + return (fl2.f); + } + + /* numerator zero??? */ + if (!fl1.l) + return (0); + + /* now get mantissas */ + mant1 = MANT (fl1.l); + mant2 = MANT (fl2.l); + + /* this assures we have 25 bits of precision in the end */ + if (mant1 < mant2) + { + mant1 <<= 1; + exp--; + } + + /* now we perform repeated subtraction of fl2.l from fl1.l */ + mask = 0x1000000; + result = 0; + while (mask) + { + if (mant1 >= mant2) + { + result |= mask; + mant1 -= mant2; + } + mant1 <<= 1; + mask >>= 1; + } + + /* round */ + result += 1; + + /* normalize down */ + exp++; + result >>= 1; + + result &= ~HIDDEN; + + /* pack up and go home */ + if (exp >= 0x100) + fl1.l = (sign ? SIGNBIT : 0) | 0x7F800000; + else if (exp < 0) + fl1.l = 0; + else + fl1.l = PACK (sign ? SIGNBIT : 0 , exp, result); + return (fl1.f); +} + diff --git a/device/lib/pic/libsdcc/fseq.c b/device/lib/pic/libsdcc/fseq.c index 4bea7bbb..cdb2ccbd 100644 --- a/device/lib/pic/libsdcc/fseq.c +++ b/device/lib/pic/libsdcc/fseq.c @@ -15,7 +15,7 @@ */ /* -** $Id: fseq.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ /* (c)2000/2001: hacked a little by johan.knol@iduna.nl for sdcc */ diff --git a/device/lib/pic/libsdcc/fsgt.c b/device/lib/pic/libsdcc/fsgt.c index 634619b6..8306d5bf 100644 --- a/device/lib/pic/libsdcc/fsgt.c +++ b/device/lib/pic/libsdcc/fsgt.c @@ -15,7 +15,7 @@ */ /* -** $Id: fsgt.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ /* (c)2000/2001: hacked a little by johan.knol@iduna.nl for sdcc */ diff --git a/device/lib/pic/libsdcc/fslt.c b/device/lib/pic/libsdcc/fslt.c index 9956717b..1bc71016 100644 --- a/device/lib/pic/libsdcc/fslt.c +++ b/device/lib/pic/libsdcc/fslt.c @@ -15,7 +15,7 @@ */ /* -** $Id: fslt.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ /* (c)2000/2001: hacked a little by johan.knol@iduna.nl for sdcc */ diff --git a/device/lib/pic/libsdcc/fsmul.c b/device/lib/pic/libsdcc/fsmul.c index 9752800c..34279826 100644 --- a/device/lib/pic/libsdcc/fsmul.c +++ b/device/lib/pic/libsdcc/fsmul.c @@ -1,86 +1,86 @@ -/* -** libgcc support for software floating point. -** Copyright (C) 1991 by Pipeline Associates, Inc. All rights reserved. -** Permission is granted to do *anything* you want with this file, -** commercial or otherwise, provided this message remains intact. So there! -** I would appreciate receiving any updates/patches/changes that anyone -** makes, and am willing to be the repository for said changes (am I -** making a big mistake?). -** -** Pat Wood -** Pipeline Associates, Inc. -** pipeline!phw@motown.com or -** sun!pipeline!phw or -** uunet!motown!pipeline!phw -*/ - -/* -** $Id: fsmul.c 3513 2004-10-01 14:49:51Z vrokas $ -*/ - -/* (c)2000/2001: hacked a little by johan.knol@iduna.nl for sdcc */ - -#include - -union float_long - { - float f; - unsigned long l; - }; - -/* multiply two floats */ -float __fsmul (float a1, float a2) _FS_REENTRANT -{ - FS_STATIC volatile union float_long fl1, fl2; - unsigned long result; - int exp; - char sign; - - fl1.f = a1; - fl2.f = a2; - - if (!fl1.l || !fl2.l) - return (0); - - /* compute sign and exponent */ - sign = SIGN (fl1.l) ^ SIGN (fl2.l); - exp = EXP (fl1.l) - EXCESS; - exp += EXP (fl2.l); - - fl1.l = MANT (fl1.l); - fl2.l = MANT (fl2.l); - - /* the multiply is done as one 16x16 multiply and two 16x8 multiples */ - result = (fl1.l >> 8) * (fl2.l >> 8); - result += ((fl1.l & (unsigned long) 0xFF) * (fl2.l >> 8)) >> 8; - result += ((fl2.l & (unsigned long) 0xFF) * (fl1.l >> 8)) >> 8; - - if (0 != (result & SIGNBIT)) - { - /* round */ - result += 0x80; - result >>= 8; - } - else - { - /* round */ - result += 0x40; - result >>= 7; - exp--; - } - - result &= ~HIDDEN; - - /* pack up and go home */ - if (exp >= 0x100) - fl1.l = (sign ? SIGNBIT : 0) | 0x7F800000; - else if (exp < 0) - fl1.l = 0; - else - fl1.l = PACK (sign ? SIGNBIT : 0 , exp, result); - return (fl1.f); -} - - - - +/* +** libgcc support for software floating point. +** Copyright (C) 1991 by Pipeline Associates, Inc. All rights reserved. +** Permission is granted to do *anything* you want with this file, +** commercial or otherwise, provided this message remains intact. So there! +** I would appreciate receiving any updates/patches/changes that anyone +** makes, and am willing to be the repository for said changes (am I +** making a big mistake?). +** +** Pat Wood +** Pipeline Associates, Inc. +** pipeline!phw@motown.com or +** sun!pipeline!phw or +** uunet!motown!pipeline!phw +*/ + +/* +** $Id$ +*/ + +/* (c)2000/2001: hacked a little by johan.knol@iduna.nl for sdcc */ + +#include + +union float_long + { + float f; + unsigned long l; + }; + +/* multiply two floats */ +float __fsmul (float a1, float a2) _FS_REENTRANT +{ + FS_STATIC volatile union float_long fl1, fl2; + unsigned long result; + int exp; + char sign; + + fl1.f = a1; + fl2.f = a2; + + if (!fl1.l || !fl2.l) + return (0); + + /* compute sign and exponent */ + sign = SIGN (fl1.l) ^ SIGN (fl2.l); + exp = EXP (fl1.l) - EXCESS; + exp += EXP (fl2.l); + + fl1.l = MANT (fl1.l); + fl2.l = MANT (fl2.l); + + /* the multiply is done as one 16x16 multiply and two 16x8 multiples */ + result = (fl1.l >> 8) * (fl2.l >> 8); + result += ((fl1.l & (unsigned long) 0xFF) * (fl2.l >> 8)) >> 8; + result += ((fl2.l & (unsigned long) 0xFF) * (fl1.l >> 8)) >> 8; + + if (0 != (result & SIGNBIT)) + { + /* round */ + result += 0x80; + result >>= 8; + } + else + { + /* round */ + result += 0x40; + result >>= 7; + exp--; + } + + result &= ~HIDDEN; + + /* pack up and go home */ + if (exp >= 0x100) + fl1.l = (sign ? SIGNBIT : 0) | 0x7F800000; + else if (exp < 0) + fl1.l = 0; + else + fl1.l = PACK (sign ? SIGNBIT : 0 , exp, result); + return (fl1.f); +} + + + + diff --git a/device/lib/pic/libsdcc/fsneq.c b/device/lib/pic/libsdcc/fsneq.c index 8178cee2..48eabe8d 100644 --- a/device/lib/pic/libsdcc/fsneq.c +++ b/device/lib/pic/libsdcc/fsneq.c @@ -15,7 +15,7 @@ */ /* -** $Id: fsneq.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ /* (c)2000/2001: hacked a little by johan.knol@iduna.nl for sdcc */ diff --git a/device/lib/pic/libsdcc/fssub.c b/device/lib/pic/libsdcc/fssub.c index 0265e98e..e3c2172b 100644 --- a/device/lib/pic/libsdcc/fssub.c +++ b/device/lib/pic/libsdcc/fssub.c @@ -15,7 +15,7 @@ */ /* -** $Id: fssub.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ /* (c)2000/2001: hacked a little by johan.knol@iduna.nl for sdcc */ diff --git a/device/lib/pic/libsdcc/schar2fs.c b/device/lib/pic/libsdcc/schar2fs.c index 8153b367..9fc7bdf6 100644 --- a/device/lib/pic/libsdcc/schar2fs.c +++ b/device/lib/pic/libsdcc/schar2fs.c @@ -26,7 +26,7 @@ -------------------------------------------------------------------------*/ /* -** $Id: schar2fs.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libsdcc/sint2fs.c b/device/lib/pic/libsdcc/sint2fs.c index b0d714a0..ce53b355 100644 --- a/device/lib/pic/libsdcc/sint2fs.c +++ b/device/lib/pic/libsdcc/sint2fs.c @@ -26,7 +26,7 @@ -------------------------------------------------------------------------*/ /* -** $Id: sint2fs.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libsdcc/slong2fs.c b/device/lib/pic/libsdcc/slong2fs.c index 255d4d3e..fb9a8ab6 100644 --- a/device/lib/pic/libsdcc/slong2fs.c +++ b/device/lib/pic/libsdcc/slong2fs.c @@ -26,7 +26,7 @@ -------------------------------------------------------------------------*/ /* -** $Id: slong2fs.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libsdcc/uchar2fs.c b/device/lib/pic/libsdcc/uchar2fs.c index 4b42a5cd..d68eb866 100644 --- a/device/lib/pic/libsdcc/uchar2fs.c +++ b/device/lib/pic/libsdcc/uchar2fs.c @@ -26,7 +26,7 @@ -------------------------------------------------------------------------*/ /* -** $Id: uchar2fs.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libsdcc/uint2fs.c b/device/lib/pic/libsdcc/uint2fs.c index a1b8de43..6930296c 100644 --- a/device/lib/pic/libsdcc/uint2fs.c +++ b/device/lib/pic/libsdcc/uint2fs.c @@ -26,7 +26,7 @@ -------------------------------------------------------------------------*/ /* -** $Id: uint2fs.c 3513 2004-10-01 14:49:51Z vrokas $ +** $Id$ */ #include diff --git a/device/lib/pic/libsdcc/ulong2fs.c b/device/lib/pic/libsdcc/ulong2fs.c index a2dc3613..1f3841c5 100644 --- a/device/lib/pic/libsdcc/ulong2fs.c +++ b/device/lib/pic/libsdcc/ulong2fs.c @@ -15,7 +15,7 @@ */ /* -** $Id: ulong2fs.c 3607 2004-12-20 21:48:32Z vrokas $ +** $Id$ */ /* (c)2000/2001: hacked a little by johan.knol@iduna.nl for sdcc */ diff --git a/device/lib/rand.c b/device/lib/rand.c index 1a267194..a6c118f3 100644 --- a/device/lib/rand.c +++ b/device/lib/rand.c @@ -1,38 +1,38 @@ -/*------------------------------------------------------------------------- - rand.c - random number generator - - Written By - Maarten Brock, sourceforge.brock@dse.nl (2006) - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - In other words, you are welcome to use, share and improve this program. - You are forbidden to forbid anyone else to use, share and improve - what you give them. Help stamp out software-hoarding! --------------------------------------------------------------------------*/ - -#include - -static unsigned long int next = 1; - -int rand(void) -{ - next = next * 1103515245UL + 12345; - return (unsigned int)(next/65536) % (RAND_MAX + 1U); -} - -void srand(unsigned int seed) -{ - next = seed; -} +/*------------------------------------------------------------------------- + rand.c - random number generator + + Written By - Maarten Brock, sourceforge.brock@dse.nl (2006) + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + In other words, you are welcome to use, share and improve this program. + You are forbidden to forbid anyone else to use, share and improve + what you give them. Help stamp out software-hoarding! +-------------------------------------------------------------------------*/ + +#include + +static unsigned long int next = 1; + +int rand(void) +{ + next = next * 1103515245UL + 12345; + return (unsigned int)(next/65536) % (RAND_MAX + 1U); +} + +void srand(unsigned int seed) +{ + next = seed; +} diff --git a/doc/knownbugs.html b/doc/knownbugs.html index 995ac5ea..0b990f37 100644 --- a/doc/knownbugs.html +++ b/doc/knownbugs.html @@ -1,1819 +1,1819 @@ - - - - - - SourceForge.net: Known Bugs - - - - - - -
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Small Device C Compiler - Release 2.6.0 Known Bug List

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Request IDSummaryOpen DatePriorityAssigned ToSubmitted By
- 1527564 - - - Klydgy fixes in CSE - - -   - 2006-07-24 07:33 - - 5 - nobodynobody
- 1526968 - - - Bit inversion in pic16F74 - - -   - 2006-07-22 17:15 - - 5 - nobodynobody
- 1525093 - - - printf_fast_f, problem with large float - - -   - 2006-07-19 11:00 - - 5 - nobodyfrief
- 1524291 - - - __gptrget not overload register B - - -   - 2006-07-18 08:29 - - 5 - nobodynobody
- 1520949 - - - missing includes in pic18f4550.h - - -   - 2006-07-11 21:51 - - 5 - nobodymarkrages
- 1519100 - - - regression test bp.c fails on ppc64 host, z80 target - - -   - 2006-07-07 23:09 - - 5 - nobodyborutr
- 1518279 - - - bad code is accepted - - -   - 2006-07-06 10:25 - - 5 - nobodystsp
- 1518273 - - - good code rejected with strange error - - -   - 2006-07-06 10:22 - - 5 - nobodystsp
- 1515231 - - - pic14 SIGSEGV without --no-peep on 4251 Jun 29 - - -   - 2006-06-30 09:32 - - 5 - nobodychisight
- 1512044 - - - pic16: bad code for unitialized variable - - -   - 2006-06-25 01:50 - - 5 - nobodyborutr
- 1511838 - - - pic16: bad code for xor and or - - -   - 2006-06-24 09:41 - - 5 - nobodyborutr
- 1511794 - - - pic16: regression test bug-895992.c fails - - -   - 2006-06-24 07:09 - - 5 - nobodyborutr
- 1510137 - - - Makefile.in missing in lib/src/pic - - -   - 2006-06-21 11:09 - - 5 - nobodynobody
- 1509084 - - - Error in register optimisation - - -   - 2006-06-19 23:53 - - 5 - nobodypv32768
- 1505998 - - - Cannot operate with floats - - -   - 2006-06-14 05:30 - - 5 - tecodevnobody
- 1505956 - - - sjmp and conditional jump out of range - - -   - 2006-06-14 04:04 - - 5 - nobodyfrief
- 1505811 - - - Bad 'for' loop optimization - - -   - 2006-06-14 00:07 - - 5 - nobodygaufillet
- 1503239 - - - Internal error: validateLink failed - - -   - 2006-06-08 17:33 - - 5 - nobodysjborley
- 1503067 - - - Variable names are not case sensitive! - - -   - 2006-06-08 11:02 - - 5 - nobodyspth
- 1500467 - - - Missing banksel for function parameter - - -   - 2006-06-04 06:13 - - 5 - tecodevkein0r
- 1499904 - - - _naked is not supported - - -   - 2006-06-02 19:56 - - 5 - nobodyamep
- 1498479 - - - sdcc Z80port math library update - - -   - 2006-05-31 13:10 - - 5 - nobodyhbingal
- 1494169 - - - unmatched apostrophe in outcommented code - - -   - 2006-05-24 03:15 - - 1 - nobodyfrief
- 1485812 - - - pic16: regression test bug1426356.c fails - - -   - 2006-05-10 10:48 - - 5 - nobodyborutr
- 1478649 - - - keyword inline should not cause an error - - -   - 2006-04-28 13:59 - - 5 - epetrichfrief
- 1477149 - - - local variable globally visible - - -   - 2006-04-26 11:45 - - 5 - nobodyfrief
- 1474589 - - - nonexisting struct initialization - - -   - 2006-04-22 04:01 - - 5 - nobodyspth
- 1471713 - - - global char array not initialized - - -   - 2006-04-17 06:09 - - 5 - nobodynobody
- 1470790 - - - extern decl is not properly accounted - - -   - 2006-04-15 04:39 - - 5 - nobodystsp
- 1469393 - - - Compiler does not initialize static data - - -   - 2006-04-12 09:50 - - 5 - nobodynobody
- 1469031 - - - pointer cast problem - - -   - 2006-04-11 23:38 - - 5 - nobodyspth
- 1466761 - - - SIGSEGV on wrong code - - -   - 2006-04-08 00:52 - - 5 - nobodystsp
- 1465671 - - - Printf not calling puchar function - - -   - 2006-04-06 04:52 - - 5 - nobodynobody
- 1458678 - - - unsigned long *const w, xtea stream cypher - - -   - 2006-03-26 01:30 - - 5 - nobodyfrief
- 1447412 - - - Cannot debug files that contain spaces in the path name - - -   - 2006-03-10 10:13 - - 5 - nobodymcu_software
- 1444425 - - - onebyte.c regression tes fails on pic16 - - -   - 2006-03-06 13:07 - - 5 - tecodevborutr
- 1433917 - - - Bank switch missing in pic14 - - -   - 2006-02-17 15:49 - - 5 - nobodyrickbronson
- 1430967 - - - bad pic14 code for address of parameter - - -   - 2006-02-13 12:44 - - 5 - nobodyborutr
- 1427820 - - - bad code with varargs - - -   - 2006-02-08 11:45 - - 5 - nobodyborutr
- 1427663 - - - SIGSEGV on static array of function pointers - - -   - 2006-02-08 08:15 - - 5 - nobodyborutr
- 1425572 - - - failing pic14 regression tests - - -   - 2006-02-06 12:25 - - 5 - nobodyborutr
- 1406219 - - - Improper branch generation when using macros - - -   - 2006-01-14 16:43 - - 5 - nobodyjbrooksh
- 1399290 - - - Bad Code Generated in Z80 port - - -   - 2006-01-07 09:10 - - 5 - nobodyrgbradford
- 1385430 - - - dual dptr control for 89C51R - - -   - 2005-12-19 11:29 - - 5 - nobodyjanvrot
- 1384257 - - - Bank selection bug (new) - - -   - 2005-12-17 20:30 - - 5 - nobodysmcauliffe
- 1383846 - - - Variable initializers ignored - - -   - 2005-12-17 11:47 - - 5 - nobodysmcauliffe
- 1378648 - - - Insufficient bank selection during global initialization - - -   - 2005-12-12 02:59 - - 5 - nobodysmcauliffe
- 1376285 - - - syntax error - - -   - 2005-12-08 05:45 - - 5 - nobodymaartenbrock
- 1358533 - - - Global variables do not work as loop operands - - -   - 2005-11-16 15:02 - - 5 - nobodyatarimax
- 1351710 - - - string constant problem when many empty lines between - - -   - 2005-11-08 13:53 - - 5 - nobodyjetset
- 1309013 - - - Pointer types ignored - - -   - 2005-09-29 15:53 - - 5 - nobodyspth
- 1302048 - - - const doesn't work - - -   - 2005-09-23 13:34 - - 5 - nobodyspth
- 1299007 - - - No floating point functions in Z80 port - - -   - 2005-09-22 11:39 - - 5 - nobodyspth
- 1294691 - - - nested ifs make compiler crash - - -   - 2005-09-18 11:08 - - 5 - nobodyspth
- 1292721 - - - variable load wrongly optimized away - - -   - 2005-09-16 02:30 - - 5 - nobodyttensi
- 1291133 - - - duplicate members accross enum(s) - - -   - 2005-09-14 09:15 - - 5 - nobodyfrief
- 1281583 - - - code pointer array referencing - - -   - 2005-09-04 05:08 - - 5 - nobodybortel
- 1273984 - - - wrong assemblercode for functioncall - - -   - 2005-08-26 05:23 - - 5 - nobodyjehle
- 1255403 - - - printf_fast_f SIGN and leading spaces problem - - -   - 2005-08-09 18:24 - - 5 - nobodyshalomj
- 1224197 - - - SDCDB (from package of SDCC 2.5 and all CSV) works badly. - - -   - 2005-06-20 07:35 - - 5 - nobodynobody
- 1204921 - - - sdcdb hangs if child s51 process turns zombie - - -   - 2005-05-19 05:21 - - 5 - nobodymleopold
- 1203664 - - - sdcdb fails to open files w. two "." periods - - -   - 2005-05-17 08:13 - - 5 - nobodymleopold
- 1196096 - - - aslink abortes with signal 6 - - -   - 2005-05-05 11:19 - - 5 - nobodyajbathe
- 1196045 - - - HC08:wrong 16 bytes loading asm result - - -   - 2005-05-05 09:54 - - 5 - nobodynobody
- 1185014 - - - sdcdb crushes when trying to set a breakpoint - - -   - 2005-04-17 23:27 - - 5 - nobodynobody
- 1159134 - - - invalid duplicate declarations with same scope - - -   - 2005-03-08 07:55 - - 5 - epetrichriedel_teco
- 1115321 - - - pic16_allocRegByName results in bad code - - -   - 2005-02-03 03:03 - - 5 - vrokasschmidtw
- 1104624 - - - label minus label is not constant - - -   - 2005-01-18 09:09 - - 5 - nobodyjetset
- 1068030 - - - Assembler error with files that has "-" in the filename - - -   - 2004-11-17 06:11 - - 5 - nobodyhsanchez
- 1057171 - - - z80 linker problem on multiple global variable declare - - -   - 2004-10-29 21:27 - - 5 - nobodyakiya-i
- 1049137 - - - Possible Register Allocation Problem - - -   - 2004-10-18 04:03 - - 5 - nobodyttensi
- 1048323 - - - sdcdb command line simulator options do not pass to s51 - - -   - 2004-10-16 07:20 - - 5 - nobodyexcon26
- 1015185 - - - long type multiplication on DS80C400 - - -   - 2004-08-24 05:04 - - 5 - bernhardheldbernardtelling
- 1012147 - - - incorrect pointer address - - -   - 2004-08-19 05:33 - - 5 - nobodynobody
- 983491 - - - Merge duplicate strings function is ineffective - - -   - 2004-07-01 08:40 - - 5 - nobodybortel
- 976553 - - - Problem in debugging - - -   - 2004-06-21 00:24 - - 5 - nobodykirti10
- 947179 - - - Case Sensitive cpuSpeed - - -   - 2004-05-03 12:50 - - 5 - nobodynobody
- 894745 - - - Problem witch cdbFile - - -   - 2004-02-10 14:48 - - 5 - nobodynobody
- 880197 - - - (code *) cast to (xdata *) mishandled - - -   - 2004-01-19 14:50 - - 5 - epetrichmbroxton
- 855165 - - - Code generator selects incorrect registers - - -   - 2003-12-05 19:05 - - 5 - epetrichjcwren
- 830513 - - - inline assembler ACALL for ds80c390 is translated incorrect - - -   - 2003-10-26 06:48 - - 5 - nobodynobody
- 817589 - - - Can't create enough cdb file. - - -   - 2003-10-03 23:52 - - 5 - nobodynobody
- 681254 - - - Lib functions ignore --use-accelerator - - -   - 2003-02-05 13:16 - - 1 - bernhardheldbernhardheld
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Small Device C Compiler - Release 2.6.0 Known Bug List

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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Request IDSummaryOpen DatePriorityAssigned ToSubmitted By
+ 1527564 + + + Klydgy fixes in CSE + + +   + 2006-07-24 07:33 + + 5 + nobodynobody
+ 1526968 + + + Bit inversion in pic16F74 + + +   + 2006-07-22 17:15 + + 5 + nobodynobody
+ 1525093 + + + printf_fast_f, problem with large float + + +   + 2006-07-19 11:00 + + 5 + nobodyfrief
+ 1524291 + + + __gptrget not overload register B + + +   + 2006-07-18 08:29 + + 5 + nobodynobody
+ 1520949 + + + missing includes in pic18f4550.h + + +   + 2006-07-11 21:51 + + 5 + nobodymarkrages
+ 1519100 + + + regression test bp.c fails on ppc64 host, z80 target + + +   + 2006-07-07 23:09 + + 5 + nobodyborutr
+ 1518279 + + + bad code is accepted + + +   + 2006-07-06 10:25 + + 5 + nobodystsp
+ 1518273 + + + good code rejected with strange error + + +   + 2006-07-06 10:22 + + 5 + nobodystsp
+ 1515231 + + + pic14 SIGSEGV without --no-peep on 4251 Jun 29 + + +   + 2006-06-30 09:32 + + 5 + nobodychisight
+ 1512044 + + + pic16: bad code for unitialized variable + + +   + 2006-06-25 01:50 + + 5 + nobodyborutr
+ 1511838 + + + pic16: bad code for xor and or + + +   + 2006-06-24 09:41 + + 5 + nobodyborutr
+ 1511794 + + + pic16: regression test bug-895992.c fails + + +   + 2006-06-24 07:09 + + 5 + nobodyborutr
+ 1510137 + + + Makefile.in missing in lib/src/pic + + +   + 2006-06-21 11:09 + + 5 + nobodynobody
+ 1509084 + + + Error in register optimisation + + +   + 2006-06-19 23:53 + + 5 + nobodypv32768
+ 1505998 + + + Cannot operate with floats + + +   + 2006-06-14 05:30 + + 5 + tecodevnobody
+ 1505956 + + + sjmp and conditional jump out of range + + +   + 2006-06-14 04:04 + + 5 + nobodyfrief
+ 1505811 + + + Bad 'for' loop optimization + + +   + 2006-06-14 00:07 + + 5 + nobodygaufillet
+ 1503239 + + + Internal error: validateLink failed + + +   + 2006-06-08 17:33 + + 5 + nobodysjborley
+ 1503067 + + + Variable names are not case sensitive! + + +   + 2006-06-08 11:02 + + 5 + nobodyspth
+ 1500467 + + + Missing banksel for function parameter + + +   + 2006-06-04 06:13 + + 5 + tecodevkein0r
+ 1499904 + + + _naked is not supported + + +   + 2006-06-02 19:56 + + 5 + nobodyamep
+ 1498479 + + + sdcc Z80port math library update + + +   + 2006-05-31 13:10 + + 5 + nobodyhbingal
+ 1494169 + + + unmatched apostrophe in outcommented code + + +   + 2006-05-24 03:15 + + 1 + nobodyfrief
+ 1485812 + + + pic16: regression test bug1426356.c fails + + +   + 2006-05-10 10:48 + + 5 + nobodyborutr
+ 1478649 + + + keyword inline should not cause an error + + +   + 2006-04-28 13:59 + + 5 + epetrichfrief
+ 1477149 + + + local variable globally visible + + +   + 2006-04-26 11:45 + + 5 + nobodyfrief
+ 1474589 + + + nonexisting struct initialization + + +   + 2006-04-22 04:01 + + 5 + nobodyspth
+ 1471713 + + + global char array not initialized + + +   + 2006-04-17 06:09 + + 5 + nobodynobody
+ 1470790 + + + extern decl is not properly accounted + + +   + 2006-04-15 04:39 + + 5 + nobodystsp
+ 1469393 + + + Compiler does not initialize static data + + +   + 2006-04-12 09:50 + + 5 + nobodynobody
+ 1469031 + + + pointer cast problem + + +   + 2006-04-11 23:38 + + 5 + nobodyspth
+ 1466761 + + + SIGSEGV on wrong code + + +   + 2006-04-08 00:52 + + 5 + nobodystsp
+ 1465671 + + + Printf not calling puchar function + + +   + 2006-04-06 04:52 + + 5 + nobodynobody
+ 1458678 + + + unsigned long *const w, xtea stream cypher + + +   + 2006-03-26 01:30 + + 5 + nobodyfrief
+ 1447412 + + + Cannot debug files that contain spaces in the path name + + +   + 2006-03-10 10:13 + + 5 + nobodymcu_software
+ 1444425 + + + onebyte.c regression tes fails on pic16 + + +   + 2006-03-06 13:07 + + 5 + tecodevborutr
+ 1433917 + + + Bank switch missing in pic14 + + +   + 2006-02-17 15:49 + + 5 + nobodyrickbronson
+ 1430967 + + + bad pic14 code for address of parameter + + +   + 2006-02-13 12:44 + + 5 + nobodyborutr
+ 1427820 + + + bad code with varargs + + +   + 2006-02-08 11:45 + + 5 + nobodyborutr
+ 1427663 + + + SIGSEGV on static array of function pointers + + +   + 2006-02-08 08:15 + + 5 + nobodyborutr
+ 1425572 + + + failing pic14 regression tests + + +   + 2006-02-06 12:25 + + 5 + nobodyborutr
+ 1406219 + + + Improper branch generation when using macros + + +   + 2006-01-14 16:43 + + 5 + nobodyjbrooksh
+ 1399290 + + + Bad Code Generated in Z80 port + + +   + 2006-01-07 09:10 + + 5 + nobodyrgbradford
+ 1385430 + + + dual dptr control for 89C51R + + +   + 2005-12-19 11:29 + + 5 + nobodyjanvrot
+ 1384257 + + + Bank selection bug (new) + + +   + 2005-12-17 20:30 + + 5 + nobodysmcauliffe
+ 1383846 + + + Variable initializers ignored + + +   + 2005-12-17 11:47 + + 5 + nobodysmcauliffe
+ 1378648 + + + Insufficient bank selection during global initialization + + +   + 2005-12-12 02:59 + + 5 + nobodysmcauliffe
+ 1376285 + + + syntax error + + +   + 2005-12-08 05:45 + + 5 + nobodymaartenbrock
+ 1358533 + + + Global variables do not work as loop operands + + +   + 2005-11-16 15:02 + + 5 + nobodyatarimax
+ 1351710 + + + string constant problem when many empty lines between + + +   + 2005-11-08 13:53 + + 5 + nobodyjetset
+ 1309013 + + + Pointer types ignored + + +   + 2005-09-29 15:53 + + 5 + nobodyspth
+ 1302048 + + + const doesn't work + + +   + 2005-09-23 13:34 + + 5 + nobodyspth
+ 1299007 + + + No floating point functions in Z80 port + + +   + 2005-09-22 11:39 + + 5 + nobodyspth
+ 1294691 + + + nested ifs make compiler crash + + +   + 2005-09-18 11:08 + + 5 + nobodyspth
+ 1292721 + + + variable load wrongly optimized away + + +   + 2005-09-16 02:30 + + 5 + nobodyttensi
+ 1291133 + + + duplicate members accross enum(s) + + +   + 2005-09-14 09:15 + + 5 + nobodyfrief
+ 1281583 + + + code pointer array referencing + + +   + 2005-09-04 05:08 + + 5 + nobodybortel
+ 1273984 + + + wrong assemblercode for functioncall + + +   + 2005-08-26 05:23 + + 5 + nobodyjehle
+ 1255403 + + + printf_fast_f SIGN and leading spaces problem + + +   + 2005-08-09 18:24 + + 5 + nobodyshalomj
+ 1224197 + + + SDCDB (from package of SDCC 2.5 and all CSV) works badly. + + +   + 2005-06-20 07:35 + + 5 + nobodynobody
+ 1204921 + + + sdcdb hangs if child s51 process turns zombie + + +   + 2005-05-19 05:21 + + 5 + nobodymleopold
+ 1203664 + + + sdcdb fails to open files w. two "." periods + + +   + 2005-05-17 08:13 + + 5 + nobodymleopold
+ 1196096 + + + aslink abortes with signal 6 + + +   + 2005-05-05 11:19 + + 5 + nobodyajbathe
+ 1196045 + + + HC08:wrong 16 bytes loading asm result + + +   + 2005-05-05 09:54 + + 5 + nobodynobody
+ 1185014 + + + sdcdb crushes when trying to set a breakpoint + + +   + 2005-04-17 23:27 + + 5 + nobodynobody
+ 1159134 + + + invalid duplicate declarations with same scope + + +   + 2005-03-08 07:55 + + 5 + epetrichriedel_teco
+ 1115321 + + + pic16_allocRegByName results in bad code + + +   + 2005-02-03 03:03 + + 5 + vrokasschmidtw
+ 1104624 + + + label minus label is not constant + + +   + 2005-01-18 09:09 + + 5 + nobodyjetset
+ 1068030 + + + Assembler error with files that has "-" in the filename + + +   + 2004-11-17 06:11 + + 5 + nobodyhsanchez
+ 1057171 + + + z80 linker problem on multiple global variable declare + + +   + 2004-10-29 21:27 + + 5 + nobodyakiya-i
+ 1049137 + + + Possible Register Allocation Problem + + +   + 2004-10-18 04:03 + + 5 + nobodyttensi
+ 1048323 + + + sdcdb command line simulator options do not pass to s51 + + +   + 2004-10-16 07:20 + + 5 + nobodyexcon26
+ 1015185 + + + long type multiplication on DS80C400 + + +   + 2004-08-24 05:04 + + 5 + bernhardheldbernardtelling
+ 1012147 + + + incorrect pointer address + + +   + 2004-08-19 05:33 + + 5 + nobodynobody
+ 983491 + + + Merge duplicate strings function is ineffective + + +   + 2004-07-01 08:40 + + 5 + nobodybortel
+ 976553 + + + Problem in debugging + + +   + 2004-06-21 00:24 + + 5 + nobodykirti10
+ 947179 + + + Case Sensitive cpuSpeed + + +   + 2004-05-03 12:50 + + 5 + nobodynobody
+ 894745 + + + Problem witch cdbFile + + +   + 2004-02-10 14:48 + + 5 + nobodynobody
+ 880197 + + + (code *) cast to (xdata *) mishandled + + +   + 2004-01-19 14:50 + + 5 + epetrichmbroxton
+ 855165 + + + Code generator selects incorrect registers + + +   + 2003-12-05 19:05 + + 5 + epetrichjcwren
+ 830513 + + + inline assembler ACALL for ds80c390 is translated incorrect + + +   + 2003-10-26 06:48 + + 5 + nobodynobody
+ 817589 + + + Can't create enough cdb file. + + +   + 2003-10-03 23:52 + + 5 + nobodynobody
+ 681254 + + + Lib functions ignore --use-accelerator + + +   + 2003-02-05 13:16 + + 1 + bernhardheldbernhardheld
+ + + +

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+ \ No newline at end of file diff --git a/sim/ucsim/cmd.src/FlexLexer.h b/sim/ucsim/cmd.src/FlexLexer.h deleted file mode 100644 index e69de29b..00000000