* sim/ucsim/hc08.src/inst.cc (inst_condbranch): fixed simulation of

* sim/ucsim/hc08.src/inst.cc (inst_condbranch): fixed simulation of
  BGT, BLE, BHI, and BLS instructions
* src/hc08/gen.c (outAcc, outBitC, outBitNV, genCmpLt, genCmpGt,
  genCmpEq): removed
* src/hc08/gen.c (genCmpEQorNE, genCmp, branchopCmp, nameCmp,
  negatedCmp, exchangedCmp, genhc08Code): rewrite of comparison handling,
  fixes bug #1216342
* src/hc08/peeph.def: added rules 2g - 2l for new conditional branches

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@3782 4a8a32a2-be11-0410-ad9d-d568d2c75423