* sim/ucsim/cmd.src/info.cc, sim/ucsim/cmd.src/bp.cc,

[fw/sdcc] / sim / ucsim / hc08.src / hc08.cc

diff --git a/sim/ucsim/hc08.src/hc08.cc b/sim/ucsim/hc08.src/hc08.cc
index ed318ea16e997e227d30861b7baa3a53a16a9286..2028ee13fc5f50f7289d27ebeba448d8caf75a60 100644 (file)
--- a/sim/ucsim/hc08.src/hc08.cc
+++ b/sim/ucsim/hc08.src/hc08.cc
@@ -2,9 +2,9 @@
  * Simulator of microcontrollers (hc08.cc)
  *
  * some hc08 code base from Karl Bongers karl@turbobit.com
- * 
+ *
  * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
- * 
+ *
  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
  *
  */
@@ -262,7 +262,7 @@ cl_hc08::get_disasm_info(t_addr addr,
 }
 
 const char *
-cl_hc08::disass(t_addr addr, char *sep)
+cl_hc08::disass(t_addr addr, const char *sep)
 {
   char work[256], temp[20];
   const char *b;
@@ -273,7 +273,7 @@ cl_hc08::disass(t_addr addr, char *sep)
   p= work;
 
   b = get_disasm_info(addr, &len, NULL, &immed_offset);
-  
+
   if (b == NULL) {
     buf= (char*)malloc(30);
     strcpy(buf, "UNKNOWN/INVALID");
@@ -390,7 +390,7 @@ cl_hc08::print_regs(class cl_console_base *con)
   con->dd_printf("SP= 0x%04x [SP+1]= %02x %3d %c\n",
                  regs.SP, ram->get(regs.SP+1), ram->get(regs.SP+1),
                  isprint(ram->get(regs.SP+1))?ram->get(regs.SP+1):'.');
-  
+
   print_disass(PC, con);
 }
 
@@ -539,7 +539,7 @@ cl_hc08::exec_inst(void)
               }
             default: return(resHALT);
           }
-              
+
       }
     case 0xa:
     case 0xb: