From 5ffc745ea39393d2fc2772bf11e996e237463004 Mon Sep 17 00:00:00 2001
From: Adrien Grassein <agrassein@nanoxplore.com>
Date: Wed, 22 Jun 2022 11:23:31 +0200
Subject: [PATCH] tcl: ngultra: add target config file

ngultra is a Quad-R52 SoC + an FPGA.

Signed-off-by: Adrien Grassein <agrassein@nanoxplore.com>
Change-Id: I6a04eab3d9a7610e9dfa3d9f647868e579b6bd8a
Reviewed-on: https://review.openocd.org/c/openocd/+/7046
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---
 tcl/target/ngultra.cfg | 51 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 tcl/target/ngultra.cfg

diff --git a/tcl/target/ngultra.cfg b/tcl/target/ngultra.cfg
new file mode 100644
index 000000000..956fdbb5c
--- /dev/null
+++ b/tcl/target/ngultra.cfg
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2022 by NanoXplore, France - all rights reserved
+#
+# configuration file for NG-Ultra SoC from NanoXplore.
+# NG-Ultra is a quad-core Cortex-R52 SoC + an FPGA.
+#
+transport select jtag
+adapter speed 10000
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME NGULTRA
+}
+
+if { [info exists CHIPCORES] } {
+    set _cores $CHIPCORES
+} else {
+    set _cores 4
+}
+
+set DBGBASE {0x88210000 0x88310000 0x88410000 0x88510000}
+set CTIBASE {0x88220000 0x88320000 0x88420000 0x88520000}
+
+# Coresight access to the SoC
+jtag newtap $_CHIPNAME.coresight cpu      -irlen 4 -expected-id 0x6BA00477
+
+# Misc TAP devices
+jtag newtap $_CHIPNAME.soc       cpu      -irlen 7 -expected-id 0xFAAA0555
+jtag newtap $_CHIPNAME.pmb       unknown1 -irlen 5 -expected-id 0xBA20A005
+jtag newtap $_CHIPNAME.fpga      fpga     -irlen 4 -ignore-version -ignore-bypass
+
+# Create the Coresight DAP
+dap create $_CHIPNAME.coresight.dap -chain-position $_CHIPNAME.coresight.cpu
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+    cti create cti.$_core -dap $_CHIPNAME.coresight.dap -ap-num 0 \
+        -baseaddr [lindex $CTIBASE $_core]
+# Cores are armv8-r but works with aarch64 (since armv8-r not directly supported by openocd yet).
+    if { $_core == 0} {
+        target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \
+            -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core
+    } else {
+        target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \
+            -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core -defer-examine
+    }
+}
+
+# Create direct APB and AXI interfaces
+target create APB mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 0
+target create AXI mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 1
-- 
2.30.2