From: Ian Thompson Date: Thu, 15 Sep 2022 21:14:15 +0000 (-0700) Subject: target/xtensa: invalidate register cache on reset X-Git-Url: https://git.gag.com/?p=fw%2Fopenocd;a=commitdiff_plain;h=61d0757acf222fdd5669b471cc251e03101db273 target/xtensa: invalidate register cache on reset Resolves issues where registers are accessed when poll() logic is inactive or has not yet been triggered. Signed-off-by: Ian Thompson Change-Id: If7a4d00938fb188b008325249627f7773c3484c5 Reviewed-on: https://review.openocd.org/c/openocd/+/7197 Tested-by: jenkins Reviewed-by: Erhan Kurubas Reviewed-by: Antonio Borneo --- diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c index 50658e9d5..d3be8b441 100644 --- a/src/target/xtensa/xtensa.c +++ b/src/target/xtensa/xtensa.c @@ -959,7 +959,6 @@ int xtensa_assert_reset(struct target *target) struct xtensa *xtensa = target_to_xtensa(target); LOG_TARGET_DEBUG(target, "target_number=%i, begin", target->target_number); - target->state = TARGET_RESET; xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, PWRCTL_JTAGDEBUGUSE(xtensa) | PWRCTL_DEBUGWAKEUP(xtensa) | PWRCTL_MEMWAKEUP(xtensa) | @@ -968,8 +967,12 @@ int xtensa_assert_reset(struct target *target) int res = xtensa_dm_queue_execute(&xtensa->dbg_mod); if (res != ERROR_OK) return res; + + /* registers are now invalid */ xtensa->reset_asserted = true; - return res; + register_cache_invalidate(xtensa->core_cache); + target->state = TARGET_RESET; + return ERROR_OK; } int xtensa_deassert_reset(struct target *target)