target/riscv: fix 'reset run' after 'reset halt'

target/riscv: fix 'reset run' after 'reset halt'

'reset halt' does not clear DM_DMCONTROL_HALTREQ at deassert_reset().
If hw reset line is configured e.g. 'reset_config srst_only'
the folowing 'reset run' halts:

 > gd32v.cpu curstate
 running

 > reset halt
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 halted

 > reset
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 halted <<<<---- wrong!!!

 > reset
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 running

Clear DM_DMCONTROL_HALTREQ when acking reset.

Change-Id: Iae0454b425e81e64774b9785bb5ba1d4564d940b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6961
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>