Upstream a whole host of RISC-V changes.
authorTim Newsome <tim@sifive.com>
Wed, 1 Sep 2021 22:00:46 +0000 (15:00 -0700)
committerAntonio Borneo <borneo.antonio@gmail.com>
Mon, 25 Oct 2021 16:12:05 +0000 (16:12 +0000)
commit615709d14049027e6172fbb7f6cf6c898eefaea9
tree32e59476ea216ac5bc107e92777508a422e5629a
parentf4612e06c61f6c46cff936d2c6b48d6f2627ff61
Upstream a whole host of RISC-V changes.

Made no attempt to separate this out into reviewable chunks, since this
is all RISC-V-specific code developed at
https://github.com/riscv/riscv-openocd

Memory sample and repeat read functionality was left out of this change
since it requires some target-independent changes that I'll upstream
some other time.

Change-Id: I92917c86d549c232cbf36ffbfefc93331c05accd
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6529
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
src/target/riscv/batch.c
src/target/riscv/debug_defines.h
src/target/riscv/opcodes.h
src/target/riscv/program.h
src/target/riscv/riscv-011.c
src/target/riscv/riscv-013.c
src/target/riscv/riscv.c
src/target/riscv/riscv.h
src/target/riscv/riscv_semihosting.c