-<html>\r
-<head>\r
-<title>Test cases</title>\r
-</head>\r
-\r
-<body>\r
-<H1>Test cases</H1>\r
-<H2>Test case results</H2>\r
-The test results are stored in seperate documents. One document for\r
-each subversion number.\r
-<table border="1">\r
- <tr><td>Test results</td><td>comment</td></tr>\r
- <tr><td><a href="examples/SAM7S256Test/results/607.html">607</a></td><td></td></tr>\r
- <tr><td><a href="results/template.html">template</a></td><td>Test results template</td></tr>\r
-</table>\r
-\r
-<H2>Vocabulary</H2>\r
-<table border="1">\r
- <tr>\r
- <td width="100">Passed version</td>\r
-\r
- <td>The latest branch and version on which the test is known to pass</td>\r
- </tr>\r
- <tr>\r
- <td width="100">Broken version</td>\r
- <td>The latest branch and version on which the test is known to fail. n/a when older than passed version.</td>\r
- </tr>\r
- <tr>\r
- <td width="100">ID</td>\r
- <td>A unqiue ID to refer to a test. The unique numbers are maintained in this file. Note that the same test can be run on different hardware/interface. Each combination yields a unique id. </td>\r
- </tr>\r
- <tr>\r
- <td width="100">Test case</td>\r
- <td>An atomic entity that describes the operations needed to test a feature or only a part of it. The test case should:\r
- <ul>\r
- <li>be uniquely identifiable</li>\r
- <li>define the complete prerequisites of the test (eg: the target, the interface, the initial state of the system)</li>\r
- <li>define the input to be applied to the system in order to execute the test</li>\r
- <li>define the expected output</li>\r
- <li>contain the output resulted by running the test case</li>\r
- <li>contain the result of the test (pass/fail)</li>\r
- </ul>\r
- </td>\r
- </tr>\r
- <tr>\r
- <td width="100">Test suite</td>\r
- <td>A (completable) collection of test cases</td>\r
- </tr>\r
- <tr>\r
- <td width="100">Testing</td>\r
- <td>Testing refers to running the test suite for a specific revision of the software,\r
- for one or many targets, using one or many JTAG interfaces. Testing should be be stored\r
- along with all the other records for that specific revision. For releases, the results\r
- can be stored along with the binaries</td>\r
- </tr>\r
- <tr>\r
- <td width="100">Target = ANY</td>\r
- <td>Any target can be used for this test</td>\r
- </tr>\r
- <tr>\r
- <td width="100">Interface = ANY</td>\r
- <td>Any interface can be used for this test</td>\r
- </tr>\r
- <tr>\r
- <td width="100">Target = "reset_config srst_and_trst"</td>\r
- <td>Any target which supports the reset_config above</td>\r
- </tr>\r
-</table>\r
-\r
-<H1>Test cases</H1>\r
-\r
-<H2>Connectivity</H2>\r
-<table border=1>\r
- <tr>\r
- <td>ID</td>\r
- <td>Target</td>\r
- <td>Interface</td>\r
- <td>Description</td>\r
- <td>Initial state</td>\r
- <td>Input</td>\r
- <td>Expected output</td>\r
- <td>Pass/Fail</td>\r
- </tr>\r
- <tr>\r
- <td><a name="CON001"/>CON001</td>\r
- <td>ALL</td>\r
- <td>ALL</td>\r
- <td>Telnet connection</td>\r
- <td>Power on, jtag target attached</td>\r
- <td>On console, type<br><code>telnet ip port</code></td>\r
- <td><code>Open On-Chip Debugger<br>></code></td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="CON002"/>CON002</td>\r
- <td>ALL</td>\r
- <td>ALL</td>\r
- <td>GDB server connection</td>\r
- <td>Power on, jtag target attached</td>\r
- <td>On GDB console, type<br><code>target remote ip:port</code></td>\r
- <td><code>Remote debugging using 10.0.0.73:3333</code></td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
-</table>\r
-\r
-<H2>Reset</H2>\r
-<table border=1>\r
- <tr>\r
- <td>ID</td>\r
- <td>Target</td>\r
- <td>Interface</td>\r
- <td>Description</td>\r
- <td>Initial state</td>\r
- <td>Input</td>\r
- <td>Expected output</td>\r
- <td>Pass/Fail</td>\r
- </tr>\r
- <tr>\r
- <td><a name="RES001"/>RES001</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>Reset halt on a blank target</td>\r
- <td>Erase all the content of the flash</td>\r
- <td>Connect via the telnet interface and type <br><code>reset halt</code></td>\r
- <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="RES002"/>RES002</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>Reset init on a blank target</td>\r
- <td>Erase all the content of the flash</td>\r
- <td>Connect via the telnet interface and type <br><code>reset init</code></td>\r
- <td>Reset should return without error and the output should contain <br><code>executing reset script 'name_of_the_script'</code></td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="RES003"/>RES003</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>Reset after a power cycle of the target</td>\r
- <td>Reset the target then power cycle the target</td>\r
- <td>Connect via the telnet interface and type <br><code>reset halt</code> after the power was detected</td>\r
- <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="RES004"/>RES004</td>\r
- <td>ARM7/9,reset_config srst_and_trst</td>\r
- <td>ANY</td>\r
- <td>Reset halt on a blank target where reset halt is supported</td>\r
- <td>Erase all the content of the flash</td>\r
- <td>Connect via the telnet interface and type <br><code>reset halt</code></td>\r
- <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="RES005"/>RES005</td>\r
- <td>arm926ejs,reset_config srst_and_trst</td>\r
- <td>ANY</td>\r
- <td>Reset halt on a blank target where reset halt is supported. This target has problems with the reset vector catch being disabled by TRST</td>\r
- <td>Erase all the content of the flash</td>\r
- <td>Connect via the telnet interface and type <br><code>reset halt</code></td>\r
- <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
-</table>\r
-\r
-<H2>JTAG Speed</H2>\r
-<table border=1>\r
- <tr>\r
- <td>ID</td>\r
- <td>Target</td>\r
- <td>Interface</td>\r
- <td>Description</td>\r
- <td>Initial state</td>\r
- <td>Input</td>\r
- <td>Expected output</td>\r
- <td>Pass/Fail</td>\r
- </tr>\r
- <tr>\r
- <td><a name="SPD001"/>RES001</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>16MHz on normal operation</td>\r
- <td>Reset init the target according to RES002 </td>\r
- <td>Exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>\r
- <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
-</table>\r
-\r
-<H2>Debugging</H2>\r
-<table border=1>\r
- <tr>\r
- <td>ID</td>\r
- <td>Target</td>\r
- <td>Interface</td>\r
- <td>Description</td>\r
- <td>Initial state</td>\r
- <td>Input</td>\r
- <td>Expected output</td>\r
- <td>Pass/Fail</td>\r
- </tr>\r
- <tr>\r
- <td><a name="DBG001"/>DBG001</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>Load is working</td>\r
- <td>Reset init is working, RAM is accesible, GDB server is started</td>\r
- <td>On the console of the OS: <br>\r
- <code>arm-elf-gdb test_ram.elf</code><br>\r
- <code>(gdb) target remote ip:port</code><br>\r
- <code>(gdb) load</load>\r
- </td>\r
- <td>Load should return without error, typical output looks like:<br>\r
- <code>\r
- Loading section .text, size 0x14c lma 0x0<br>\r
- Start address 0x40, load size 332<br>\r
- Transfer rate: 180 bytes/sec, 332 bytes/write.<br>\r
- </code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="DBG002"/>DBG002</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>Software breakpoint</td>\r
- <td>Load the test_ram.elf application, use instructions from GDB001</td>\r
- <td>In the GDB console:<br>\r
- <code>\r
- (gdb) monitor arm7_9 sw_bkpts enable<br>\r
- software breakpoints enabled<br>\r
- (gdb) break main<br>\r
- Breakpoint 1 at 0xec: file src/main.c, line 71.<br>\r
- (gdb) continue<br>\r
- Continuing.\r
- </code>\r
- </td>\r
- <td>The software breakpoint should be reached, a typical output looks like:<br>\r
- <code>\r
- target state: halted<br>\r
- target halted in ARM state due to breakpoint, current mode: Supervisor<br>\r
- cpsr: 0x000000d3 pc: 0x000000ec<br>\r
- <br>\r
- Breakpoint 1, main () at src/main.c:71<br>\r
- 71 DWORD a = 1;\r
- </code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="DBG003"/>DBG003</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>Single step in a RAM application</td>\r
- <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>\r
- <td>In GDB, type <br><code>(gdb) step</code></td>\r
- <td>The next instruction should be reached, typical output:<br>\r
- <code>\r
- (gdb) step<br>\r
- target state: halted<br>\r
- target halted in ARM state due to single step, current mode: Abort<br>\r
- cpsr: 0x20000097 pc: 0x000000f0<br>\r
- target state: halted<br>\r
- target halted in ARM state due to single step, current mode: Abort<br>\r
- cpsr: 0x20000097 pc: 0x000000f4<br>\r
- 72 DWORD b = 2;\r
- </code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="DBG004"/>DBG004</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>Software break points are working after a reset</td>\r
- <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>\r
- <td>In GDB, type <br><code>\r
- (gdb) monitor reset<br>\r
- (gdb) load<br>\r
- (gdb) continue<br>\r
- </code></td>\r
- <td>The breakpoint should be reached, typical output:<br>\r
- <code>\r
- target state: halted<br>\r
- target halted in ARM state due to breakpoint, current mode: Supervisor<br>\r
- cpsr: 0x000000d3 pc: 0x000000ec<br>\r
- <br>\r
- Breakpoint 1, main () at src/main.c:71<br>\r
- 71 DWORD a = 1;\r
- </code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="DBG005"/>DBG005</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>Hardware breakpoint</td>\r
- <td>Flash the test_rom.elf application. Make this test after FLA004 has passed</td>\r
- <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>\r
- <code>\r
- (gdb) monitor reset<br>\r
- (gdb) load<br>\r
- Loading section .text, size 0x194 lma 0x100000<br>\r
- Start address 0x100040, load size 404<br>\r
- Transfer rate: 179 bytes/sec, 404 bytes/write.<br>\r
- (gdb) monitor arm7_9 force_hw_bkpts enable<br>\r
- force hardware breakpoints enabled<br>\r
- (gdb) break main<br>\r
- Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>\r
- (gdb) continue<br>\r
- </code>\r
- </td>\r
- <td>The breakpoint should be reached, typical output:<br>\r
- <code>\r
- Continuing.<br>\r
- <br>\r
- Breakpoint 1, main () at src/main.c:69<br>\r
- 69 DWORD a = 1;<br>\r
- </code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="DBG006"/>DBG006</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>Hardware breakpoint is set after a reset</td>\r
- <td>Follow the instructions to flash and insert a hardware breakpoint from DBG005</td>\r
- <td>In GDB, type <br>\r
- <code>\r
- (gdb) monitor reset<br>\r
- (gdb) monitor reg pc 0x100000<br>\r
- pc (/32): 0x00100000<br>\r
- (gdb) continue\r
- </code>\r
- </td>\r
- <td>The breakpoint should be reached, typical output:<br>\r
- <code>\r
- Continuing.<br>\r
- <br>\r
- Breakpoint 1, main () at src/main.c:69<br>\r
- 69 DWORD a = 1;<br>\r
- </code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="DBG007"/>DBG007</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>Single step in ROM</td>\r
- <td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed</td>\r
- <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>\r
- <code>\r
- (gdb) monitor reset<br>\r
- (gdb) load<br>\r
- Loading section .text, size 0x194 lma 0x100000<br>\r
- Start address 0x100040, load size 404<br>\r
- Transfer rate: 179 bytes/sec, 404 bytes/write.<br>\r
- (gdb) monitor arm7_9 force_hw_bkpts enable<br>\r
- force hardware breakpoints enabled<br>\r
- (gdb) break main<br>\r
- Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>\r
- (gdb) continue<br>\r
- Continuing.<br>\r
- <br>\r
- Breakpoint 1, main () at src/main.c:69<br>\r
- 69 DWORD a = 1;<br>\r
- (gdb) step\r
- </code>\r
- </td>\r
- <td>The breakpoint should be reached, typical output:<br>\r
- <code>\r
- target state: halted<br>\r
- target halted in ARM state due to single step, current mode: Supervisor<br>\r
- cpsr: 0x60000013 pc: 0x0010013c<br>\r
- 70 DWORD b = 2;<br>\r
- </code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
-</table>\r
-\r
-<H2>RAM access</H2>\r
-Note: these tests are not designed to test/debug the target, but to test functionalities!\r
-<table border=1>\r
- <tr>\r
- <td>ID</td>\r
- <td>Target</td>\r
- <td>Interface</td>\r
- <td>Description</td>\r
- <td>Initial state</td>\r
- <td>Input</td>\r
- <td>Expected output</td>\r
- <td>Pass/Fail</td>\r
- </tr>\r
- <tr>\r
- <td><a name="RAM001"/>RAM001</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>32 bit Write/read RAM</td>\r
- <td>Reset init is working</td>\r
- <td>On the telnet interface<br>\r
- <code> > mww ram_address 0xdeadbeef 16<br>\r
- > mdw ram_address 32\r
- </code>\r
- </td>\r
- <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.<br>\r
- <code>\r
- > mww 0x0 0xdeadbeef 16<br>\r
- > mdw 0x0 32<br>\r
- 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>\r
- 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>\r
- 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388<br>\r
- 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388<br>\r
- </code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="RAM001"/>RAM001</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>16 bit Write/read RAM</td>\r
- <td>Reset init is working</td>\r
- <td>On the telnet interface<br>\r
- <code> > mwh ram_address 0xbeef 16<br>\r
- > mdh ram_address 32\r
- </code>\r
- </td>\r
- <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.<br>\r
- <code>\r
- > mwh 0x0 0xbeef 16<br>\r
- > mdh 0x0 32<br>\r
- 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>\r
- 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000<br>\r
- >\r
- </code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="RAM003"/>RAM003</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>8 bit Write/read RAM</td>\r
- <td>Reset init is working</td>\r
- <td>On the telnet interface<br>\r
- <code> > mwb ram_address 0xab 16<br>\r
- > mdb ram_address 32\r
- </code>\r
- </td>\r
- <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.<br>\r
- <code>\r
- > mwh 0x0 0x0 16<br>\r
- > mwb ram_address 0xab 16<br>\r
- > mdb ram_address 32<br>\r
- 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>\r
- >\r
- </code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
-</table>\r
-\r
-\r
-\r
-<H2>Flash access</H2>\r
-<table border=1>\r
- <tr>\r
- <td>ID</td>\r
- <td>Target</td>\r
- <td>Interface</td>\r
- <td>Description</td>\r
- <td>Initial state</td>\r
- <td>Input</td>\r
- <td>Expected output</td>\r
- <td>Pass/Fail</td>\r
- </tr>\r
- <tr>\r
- <td><a name="FLA001"/>FLA001</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>Flash probe</td>\r
- <td>Reset init is working</td>\r
- <td>On the telnet interface:<br>\r
- <code> > flash probe 0</code>\r
- </td>\r
- <td>The command should execute without error. The output should state the name of the flash and the starting address. An example of output:<br>\r
- <code>flash 'ecosflash' found at 0x01000000</code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="FLA002"/>FLA002</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>flash fillw</td>\r
- <td>Reset init is working, flash is probed</td>\r
- <td>On the telnet interface<br>\r
- <code> > flash fillw 0x1000000 0xdeadbeef 16\r
- </code>\r
- </td>\r
- <td>The commands should execute without error. The output looks like:<br>\r
- <code>\r
- wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)\r
- </code><br>\r
- To verify the contents of the flash:<br>\r
- <code>\r
- > mdw 0x1000000 32<br>\r
- 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>\r
- 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>\r
- 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>\r
- 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff\r
- </code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="FLA003"/>FLA003</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>Flash erase</td>\r
- <td>Reset init is working, flash is probed</td>\r
- <td>On the telnet interface<br>\r
- <code> > flash erase_address 0x1000000 0x2000\r
- </code>\r
- </td>\r
- <td>The commands should execute without error.<br>\r
- <code>\r
- erased address 0x01000000 length 8192 in 4.970000s\r
- </code>\r
- To check that the flash has been erased, read at different addresses. The result should always be 0xff.\r
- <code>\r
- > mdw 0x1000000 32<br>\r
- 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>\r
- 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>\r
- 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>\r
- 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff\r
- </code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
- <tr>\r
- <td><a name="FLA004"/>FLA004</td>\r
- <td>Fill in!</td>\r
- <td>Fill in!</td>\r
- <td>Loading to flash from GDB</td>\r
- <td>Reset init is working, flash is probed, connectivity to GDB server is working</td>\r
- <td>Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf. <br>\r
- <code>\r
- (gdb) target remote ip:port<br>\r
- (gdb) monitor reset<br>\r
- (gdb) load<br>\r
- Loading section .text, size 0x194 lma 0x100000<br>\r
- Start address 0x100040, load size 404<br>\r
- Transfer rate: 179 bytes/sec, 404 bytes/write.\r
- (gdb) monitor verify_image path_to_elf_file\r
- </code>\r
- </td>\r
- <td>The output should look like:<br>\r
- <code>\r
- verified 404 bytes in 5.060000s\r
- </code><br>\r
- The failure message is something like:<br>\r
- <code>Verify operation failed address 0x00200000. Was 0x00 instead of 0x18</code>\r
- </td>\r
- <td>PASS/FAIL</td>\r
- </tr>\r
-</table>\r
-\r
-</body>\r
+<html>
+<head>
+<title>Test cases</title>
+</head>
+
+<body>
+<H1>Test cases</H1>
+<H2>Test case results</H2>
+The test results are stored in seperate documents. One document for
+each subversion number.
+<table border="1">
+ <tr><td>Test results</td><td>comment</td></tr>
+ <tr><td><a href="examples/SAM7S256Test/results/607.html">607</a></td><td></td></tr>
+ <tr><td><a href="results/template.html">template</a></td><td>Test results template</td></tr>
+</table>
+
+<H2>Vocabulary</H2>
+<table border="1">
+ <tr>
+ <td width="100">Passed version</td>
+
+ <td>The latest branch and version on which the test is known to pass</td>
+ </tr>
+ <tr>
+ <td width="100">Broken version</td>
+ <td>The latest branch and version on which the test is known to fail. n/a when older than passed version.</td>
+ </tr>
+ <tr>
+ <td width="100">ID</td>
+ <td>A unqiue ID to refer to a test. The unique numbers are maintained in this file. Note that the same test can be run on different hardware/interface. Each combination yields a unique id. </td>
+ </tr>
+ <tr>
+ <td width="100">Test case</td>
+ <td>An atomic entity that describes the operations needed to test a feature or only a part of it. The test case should:
+ <ul>
+ <li>be uniquely identifiable</li>
+ <li>define the complete prerequisites of the test (eg: the target, the interface, the initial state of the system)</li>
+ <li>define the input to be applied to the system in order to execute the test</li>
+ <li>define the expected output</li>
+ <li>contain the output resulted by running the test case</li>
+ <li>contain the result of the test (pass/fail)</li>
+ </ul>
+ </td>
+ </tr>
+ <tr>
+ <td width="100">Test suite</td>
+ <td>A (completable) collection of test cases</td>
+ </tr>
+ <tr>
+ <td width="100">Testing</td>
+ <td>Testing refers to running the test suite for a specific revision of the software,
+ for one or many targets, using one or many JTAG interfaces. Testing should be be stored
+ along with all the other records for that specific revision. For releases, the results
+ can be stored along with the binaries</td>
+ </tr>
+ <tr>
+ <td width="100">Target = ANY</td>
+ <td>Any target can be used for this test</td>
+ </tr>
+ <tr>
+ <td width="100">Interface = ANY</td>
+ <td>Any interface can be used for this test</td>
+ </tr>
+ <tr>
+ <td width="100">Target = "reset_config srst_and_trst"</td>
+ <td>Any target which supports the reset_config above</td>
+ </tr>
+</table>
+
+<H1>Test cases</H1>
+
+<H2>Connectivity</H2>
+<table border=1>
+ <tr>
+ <td>ID</td>
+ <td>Target</td>
+ <td>Interface</td>
+ <td>Description</td>
+ <td>Initial state</td>
+ <td>Input</td>
+ <td>Expected output</td>
+ <td>Pass/Fail</td>
+ </tr>
+ <tr>
+ <td><a name="CON001"/>CON001</td>
+ <td>ALL</td>
+ <td>ALL</td>
+ <td>Telnet connection</td>
+ <td>Power on, jtag target attached</td>
+ <td>On console, type<br><code>telnet ip port</code></td>
+ <td><code>Open On-Chip Debugger<br>></code></td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="CON002"/>CON002</td>
+ <td>ALL</td>
+ <td>ALL</td>
+ <td>GDB server connection</td>
+ <td>Power on, jtag target attached</td>
+ <td>On GDB console, type<br><code>target remote ip:port</code></td>
+ <td><code>Remote debugging using 10.0.0.73:3333</code></td>
+ <td>PASS/FAIL</td>
+ </tr>
+</table>
+
+<H2>Reset</H2>
+<table border=1>
+ <tr>
+ <td>ID</td>
+ <td>Target</td>
+ <td>Interface</td>
+ <td>Description</td>
+ <td>Initial state</td>
+ <td>Input</td>
+ <td>Expected output</td>
+ <td>Pass/Fail</td>
+ </tr>
+ <tr>
+ <td><a name="RES001"/>RES001</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>Reset halt on a blank target</td>
+ <td>Erase all the content of the flash</td>
+ <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
+ <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="RES002"/>RES002</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>Reset init on a blank target</td>
+ <td>Erase all the content of the flash</td>
+ <td>Connect via the telnet interface and type <br><code>reset init</code></td>
+ <td>Reset should return without error and the output should contain <br><code>executing reset script 'name_of_the_script'</code></td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="RES003"/>RES003</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>Reset after a power cycle of the target</td>
+ <td>Reset the target then power cycle the target</td>
+ <td>Connect via the telnet interface and type <br><code>reset halt</code> after the power was detected</td>
+ <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="RES004"/>RES004</td>
+ <td>ARM7/9,reset_config srst_and_trst</td>
+ <td>ANY</td>
+ <td>Reset halt on a blank target where reset halt is supported</td>
+ <td>Erase all the content of the flash</td>
+ <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
+ <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="RES005"/>RES005</td>
+ <td>arm926ejs,reset_config srst_and_trst</td>
+ <td>ANY</td>
+ <td>Reset halt on a blank target where reset halt is supported. This target has problems with the reset vector catch being disabled by TRST</td>
+ <td>Erase all the content of the flash</td>
+ <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
+ <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
+ <td>PASS/FAIL</td>
+ </tr>
+</table>
+
+<H2>JTAG Speed</H2>
+<table border=1>
+ <tr>
+ <td>ID</td>
+ <td>Target</td>
+ <td>Interface</td>
+ <td>Description</td>
+ <td>Initial state</td>
+ <td>Input</td>
+ <td>Expected output</td>
+ <td>Pass/Fail</td>
+ </tr>
+ <tr>
+ <td><a name="SPD001"/>RES001</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>16MHz on normal operation</td>
+ <td>Reset init the target according to RES002 </td>
+ <td>Exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+ <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+ <td>PASS/FAIL</td>
+ </tr>
+</table>
+
+<H2>Debugging</H2>
+<table border=1>
+ <tr>
+ <td>ID</td>
+ <td>Target</td>
+ <td>Interface</td>
+ <td>Description</td>
+ <td>Initial state</td>
+ <td>Input</td>
+ <td>Expected output</td>
+ <td>Pass/Fail</td>
+ </tr>
+ <tr>
+ <td><a name="DBG001"/>DBG001</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>Load is working</td>
+ <td>Reset init is working, RAM is accesible, GDB server is started</td>
+ <td>On the console of the OS: <br>
+ <code>arm-elf-gdb test_ram.elf</code><br>
+ <code>(gdb) target remote ip:port</code><br>
+ <code>(gdb) load</load>
+ </td>
+ <td>Load should return without error, typical output looks like:<br>
+ <code>
+ Loading section .text, size 0x14c lma 0x0<br>
+ Start address 0x40, load size 332<br>
+ Transfer rate: 180 bytes/sec, 332 bytes/write.<br>
+ </code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="DBG002"/>DBG002</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>Software breakpoint</td>
+ <td>Load the test_ram.elf application, use instructions from GDB001</td>
+ <td>In the GDB console:<br>
+ <code>
+ (gdb) monitor arm7_9 sw_bkpts enable<br>
+ software breakpoints enabled<br>
+ (gdb) break main<br>
+ Breakpoint 1 at 0xec: file src/main.c, line 71.<br>
+ (gdb) continue<br>
+ Continuing.
+ </code>
+ </td>
+ <td>The software breakpoint should be reached, a typical output looks like:<br>
+ <code>
+ target state: halted<br>
+ target halted in ARM state due to breakpoint, current mode: Supervisor<br>
+ cpsr: 0x000000d3 pc: 0x000000ec<br>
+ <br>
+ Breakpoint 1, main () at src/main.c:71<br>
+ 71 DWORD a = 1;
+ </code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="DBG003"/>DBG003</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>Single step in a RAM application</td>
+ <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
+ <td>In GDB, type <br><code>(gdb) step</code></td>
+ <td>The next instruction should be reached, typical output:<br>
+ <code>
+ (gdb) step<br>
+ target state: halted<br>
+ target halted in ARM state due to single step, current mode: Abort<br>
+ cpsr: 0x20000097 pc: 0x000000f0<br>
+ target state: halted<br>
+ target halted in ARM state due to single step, current mode: Abort<br>
+ cpsr: 0x20000097 pc: 0x000000f4<br>
+ 72 DWORD b = 2;
+ </code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="DBG004"/>DBG004</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>Software break points are working after a reset</td>
+ <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
+ <td>In GDB, type <br><code>
+ (gdb) monitor reset<br>
+ (gdb) load<br>
+ (gdb) continue<br>
+ </code></td>
+ <td>The breakpoint should be reached, typical output:<br>
+ <code>
+ target state: halted<br>
+ target halted in ARM state due to breakpoint, current mode: Supervisor<br>
+ cpsr: 0x000000d3 pc: 0x000000ec<br>
+ <br>
+ Breakpoint 1, main () at src/main.c:71<br>
+ 71 DWORD a = 1;
+ </code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="DBG005"/>DBG005</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>Hardware breakpoint</td>
+ <td>Flash the test_rom.elf application. Make this test after FLA004 has passed</td>
+ <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
+ <code>
+ (gdb) monitor reset<br>
+ (gdb) load<br>
+ Loading section .text, size 0x194 lma 0x100000<br>
+ Start address 0x100040, load size 404<br>
+ Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
+ (gdb) monitor arm7_9 force_hw_bkpts enable<br>
+ force hardware breakpoints enabled<br>
+ (gdb) break main<br>
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
+ (gdb) continue<br>
+ </code>
+ </td>
+ <td>The breakpoint should be reached, typical output:<br>
+ <code>
+ Continuing.<br>
+ <br>
+ Breakpoint 1, main () at src/main.c:69<br>
+ 69 DWORD a = 1;<br>
+ </code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="DBG006"/>DBG006</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>Hardware breakpoint is set after a reset</td>
+ <td>Follow the instructions to flash and insert a hardware breakpoint from DBG005</td>
+ <td>In GDB, type <br>
+ <code>
+ (gdb) monitor reset<br>
+ (gdb) monitor reg pc 0x100000<br>
+ pc (/32): 0x00100000<br>
+ (gdb) continue
+ </code>
+ </td>
+ <td>The breakpoint should be reached, typical output:<br>
+ <code>
+ Continuing.<br>
+ <br>
+ Breakpoint 1, main () at src/main.c:69<br>
+ 69 DWORD a = 1;<br>
+ </code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="DBG007"/>DBG007</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>Single step in ROM</td>
+ <td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed</td>
+ <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
+ <code>
+ (gdb) monitor reset<br>
+ (gdb) load<br>
+ Loading section .text, size 0x194 lma 0x100000<br>
+ Start address 0x100040, load size 404<br>
+ Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
+ (gdb) monitor arm7_9 force_hw_bkpts enable<br>
+ force hardware breakpoints enabled<br>
+ (gdb) break main<br>
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
+ (gdb) continue<br>
+ Continuing.<br>
+ <br>
+ Breakpoint 1, main () at src/main.c:69<br>
+ 69 DWORD a = 1;<br>
+ (gdb) step
+ </code>
+ </td>
+ <td>The breakpoint should be reached, typical output:<br>
+ <code>
+ target state: halted<br>
+ target halted in ARM state due to single step, current mode: Supervisor<br>
+ cpsr: 0x60000013 pc: 0x0010013c<br>
+ 70 DWORD b = 2;<br>
+ </code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+</table>
+
+<H2>RAM access</H2>
+Note: these tests are not designed to test/debug the target, but to test functionalities!
+<table border=1>
+ <tr>
+ <td>ID</td>
+ <td>Target</td>
+ <td>Interface</td>
+ <td>Description</td>
+ <td>Initial state</td>
+ <td>Input</td>
+ <td>Expected output</td>
+ <td>Pass/Fail</td>
+ </tr>
+ <tr>
+ <td><a name="RAM001"/>RAM001</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>32 bit Write/read RAM</td>
+ <td>Reset init is working</td>
+ <td>On the telnet interface<br>
+ <code> > mww ram_address 0xdeadbeef 16<br>
+ > mdw ram_address 32
+ </code>
+ </td>
+ <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.<br>
+ <code>
+ > mww 0x0 0xdeadbeef 16<br>
+ > mdw 0x0 32<br>
+ 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+ 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+ 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388<br>
+ 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388<br>
+ </code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="RAM001"/>RAM001</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>16 bit Write/read RAM</td>
+ <td>Reset init is working</td>
+ <td>On the telnet interface<br>
+ <code> > mwh ram_address 0xbeef 16<br>
+ > mdh ram_address 32
+ </code>
+ </td>
+ <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.<br>
+ <code>
+ > mwh 0x0 0xbeef 16<br>
+ > mdh 0x0 32<br>
+ 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
+ 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000<br>
+ >
+ </code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="RAM003"/>RAM003</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>8 bit Write/read RAM</td>
+ <td>Reset init is working</td>
+ <td>On the telnet interface<br>
+ <code> > mwb ram_address 0xab 16<br>
+ > mdb ram_address 32
+ </code>
+ </td>
+ <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.<br>
+ <code>
+ > mwh 0x0 0x0 16<br>
+ > mwb ram_address 0xab 16<br>
+ > mdb ram_address 32<br>
+ 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
+ >
+ </code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+</table>
+
+
+
+<H2>Flash access</H2>
+<table border=1>
+ <tr>
+ <td>ID</td>
+ <td>Target</td>
+ <td>Interface</td>
+ <td>Description</td>
+ <td>Initial state</td>
+ <td>Input</td>
+ <td>Expected output</td>
+ <td>Pass/Fail</td>
+ </tr>
+ <tr>
+ <td><a name="FLA001"/>FLA001</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>Flash probe</td>
+ <td>Reset init is working</td>
+ <td>On the telnet interface:<br>
+ <code> > flash probe 0</code>
+ </td>
+ <td>The command should execute without error. The output should state the name of the flash and the starting address. An example of output:<br>
+ <code>flash 'ecosflash' found at 0x01000000</code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="FLA002"/>FLA002</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>flash fillw</td>
+ <td>Reset init is working, flash is probed</td>
+ <td>On the telnet interface<br>
+ <code> > flash fillw 0x1000000 0xdeadbeef 16
+ </code>
+ </td>
+ <td>The commands should execute without error. The output looks like:<br>
+ <code>
+ wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)
+ </code><br>
+ To verify the contents of the flash:<br>
+ <code>
+ > mdw 0x1000000 32<br>
+ 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+ 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ </code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="FLA003"/>FLA003</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>Flash erase</td>
+ <td>Reset init is working, flash is probed</td>
+ <td>On the telnet interface<br>
+ <code> > flash erase_address 0x1000000 0x2000
+ </code>
+ </td>
+ <td>The commands should execute without error.<br>
+ <code>
+ erased address 0x01000000 length 8192 in 4.970000s
+ </code>
+ To check that the flash has been erased, read at different addresses. The result should always be 0xff.
+ <code>
+ > mdw 0x1000000 32<br>
+ 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+ 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ </code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+ <tr>
+ <td><a name="FLA004"/>FLA004</td>
+ <td>Fill in!</td>
+ <td>Fill in!</td>
+ <td>Loading to flash from GDB</td>
+ <td>Reset init is working, flash is probed, connectivity to GDB server is working</td>
+ <td>Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf. <br>
+ <code>
+ (gdb) target remote ip:port<br>
+ (gdb) monitor reset<br>
+ (gdb) load<br>
+ Loading section .text, size 0x194 lma 0x100000<br>
+ Start address 0x100040, load size 404<br>
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor verify_image path_to_elf_file
+ </code>
+ </td>
+ <td>The output should look like:<br>
+ <code>
+ verified 404 bytes in 5.060000s
+ </code><br>
+ The failure message is something like:<br>
+ <code>Verify operation failed address 0x00200000. Was 0x00 instead of 0x18</code>
+ </td>
+ <td>PASS/FAIL</td>
+ </tr>
+</table>
+
+</body>
</html>
\ No newline at end of file
projects / fw / openocd / blobdiff