tcl/target/ti_k3: Rename R5 targets to be more descriptive

[fw/openocd] / tcl / target / ti_k3.cfg

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index e397d2255cae037cfdc5a1d708d29dfbcbd7cb00..6c2c2e1dadafe553f60041c13941eac1423aa555 100644 (file)
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -42,6 +42,7 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
 #              (0)MCU 0   (1)MCU 1   (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
+set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
 
 # Finally an General Purpose(GP) MCU
 set CM4_CTIBASE                {0x20001000}
@@ -64,11 +65,9 @@ switch $_soc {
                # AM654 has 1 cluster of 2 R5s cores.
                set _r5_cores 2
                set _mcu_r5_cores 2
-               set _mcu_base_core_id 0
                set _main0_r5_cores 0
-               set _main0_base_core_id 0
                set _main1_r5_cores 0
-               set _main1_base_core_id 0
+               set R5_NAMES {mcu_r5.0 mcu_r5.1}
 
                # Sysctrl power-ap unlock offsets
                set _sysctrl_ap_unlock_offsets {0xf0 0x50}
@@ -86,11 +85,9 @@ switch $_soc {
                # AM642 has 2 cluster of 2 R5s cores.
                set _r5_cores 4
                set _mcu_r5_cores 0
-               set _mcu_base_core_id 0
                set _main0_r5_cores 2
-               set _main0_base_core_id 0
                set _main1_r5_cores 2
-               set _main1_base_core_id 2
+               set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
                set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
                set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
 
@@ -107,11 +104,8 @@ switch $_soc {
                # J721E has 3 clusters of 2 R5 cores each.
                set _r5_cores 6
                set _mcu_r5_cores 2
-               set _mcu_base_core_id 0
                set _main0_r5_cores 2
-               set _main0_base_core_id 2
                set _main1_r5_cores 2
-               set _main1_base_core_id 4
        }
        j7200 {
                set _CHIPNAME j7200
@@ -124,11 +118,8 @@ switch $_soc {
                # J7200 has 2 clusters of 2 R5 cores each.
                set _r5_cores 4
                set _mcu_r5_cores 2
-               set _mcu_base_core_id 0
                set _main0_r5_cores 2
-               set _main0_base_core_id 2
                set _main1_r5_cores 0
-               set _main1_base_core_id 0
                set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
                set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
 
@@ -208,20 +199,20 @@ if { $_v8_smp_debug == 0 } {
 }
 
 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
-       cti create $_CTINAME.r5.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+       set _r5_name [lindex $R5_NAMES $_core]
+       cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
                -baseaddr [lindex $R5_CTIBASE $_core]
 
        # inactive core examination will fail - wait till startup of additional core
-       target create $_TARGETNAME.r5.$_core cortex_r4 -dap $_CHIPNAME.dap \
+       target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
                -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
 }
 
 if { $_mcu_r5_cores != 0 } {
        proc mcu_r5_up { args } {
                foreach { _core } [set args] {
-                       set _core [expr {$_core + $::_mcu_base_core_id}]
-                       $::_TARGETNAME.r5.$_core arp_examine
-                       $::_TARGETNAME.r5.$_core cortex_r4 dbginit
+                       $::_TARGETNAME.mcu_r5.$_core arp_examine
+                       $::_TARGETNAME.mcu_r5.$_core cortex_r4 dbginit
                }
        }
 }
@@ -229,9 +220,8 @@ if { $_mcu_r5_cores != 0 } {
 if { $_main0_r5_cores != 0 } {
        proc main0_r5_up { args } {
                foreach { _core } [set args] {
-                       set _core [expr {$_core + $::_main0_base_core_id}]
-                       $::_TARGETNAME.r5.$_core arp_examine
-                       $::_TARGETNAME.r5.$_core cortex_r4 dbginit
+                       $::_TARGETNAME.main0_r5.$_core arp_examine
+                       $::_TARGETNAME.main0_r5.$_core cortex_r4 dbginit
                }
        }
 }
@@ -239,9 +229,8 @@ if { $_main0_r5_cores != 0 } {
 if { $_main1_r5_cores != 0 } {
        proc main1_r5_up { args } {
                foreach { _core } [set args] {
-                       set _core [expr {$_core + $::_main1_base_core_id}]
-                       $::_TARGETNAME.r5.$_core arp_examine
-                       $::_TARGETNAME.r5.$_core cortex_r4 dbginit
+                       $::_TARGETNAME.main1_r5.$_core arp_examine
+                       $::_TARGETNAME.main1_r5.$_core cortex_r4 dbginit
                }
        }
 }