tcl/target/ti_k3: Add J721S2 SoC

[fw/openocd] / tcl / target / ti_k3.cfg

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 883197b14b28f906087b04553fa243159621ec4e..604083758c1c852e158cd1412590157e09894468 100644 (file)
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -114,6 +114,26 @@ switch $_soc {
                # M3 CTI base
                set CM3_CTIBASE {0x20001000}
        }
+       j721s2 {
+               set _CHIPNAME j721s2
+               set _K3_DAP_TAPID 0x0bb7502f
+
+               # J721s2 has 1 cluster of 2 A72 cores.
+               set _armv8_cpu_name a72
+               set _armv8_cores 2
+
+               # J721s2 has 3 clusters of 2 R5 cores each.
+               set _r5_cores 6
+
+               # sysctrl CTI base
+               set CM3_CTIBASE {0x20001000}
+               # Sysctrl power-ap unlock offsets
+               set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+               # M4 processor
+               set _gp_mcu_cores 1
+               set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+       }
        default {
                echo "'$_soc' is invalid!"
        }
@@ -154,6 +174,16 @@ proc _cpu_no_smp_up {} {
        $_current_target $_current_type dbginit
 }
 
+proc _armv8_smp_up {} {
+       for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
+               $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
+               $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+               $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
+       }
+       # Set Default target as core 0
+       targets $::_TARGETNAME.$::_armv8_cpu_name.0
+}
+
 set _v8_smp_targets ""
 
 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
@@ -165,6 +195,20 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
                -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
 
        set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
+
+       if { $_v8_smp_debug == 0 } {
+               $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+                       _cpu_no_smp_up
+                       # gdb-attach default rule
+                       halt 1000
+               }
+       } else {
+               $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+                       _armv8_smp_up
+                       # gdb-attach default rule
+                       halt 1000
+               }
+       }
 }
 
 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
@@ -174,22 +218,15 @@ set _armv8_smp_cmd "$_armv8_cpu_name"_smp
 
 if { $_v8_smp_debug == 0 } {
        proc $_armv8_up_cmd { args } {
-               foreach { _core } [set args] {
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+               foreach _core $args {
+                       targets $_core
+                       _cpu_no_smp_up
                }
        }
 } else {
        proc $_armv8_smp_cmd { args } {
-               for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
-                       $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
-               }
-               # Set Default target are core 0
-               targets $::_TARGETNAME.$::_armv8_cpu_name.0
+               _armv8_smp_up
        }
-
        # Declare SMP
        target smp $:::_v8_smp_targets
 }