target/espressif: add semihosting support

[fw/openocd] / tcl / target / esp32s3.cfg

diff --git a/tcl/target/esp32s3.cfg b/tcl/target/esp32s3.cfg
index a25dc145c5f37cdb1b1063bea9a9bdcb33649dbb..42b2199633b54a7f8460a42fc62f701db3c174de 100644 (file)
--- a/tcl/target/esp32s3.cfg
+++ b/tcl/target/esp32s3.cfg
@@ -7,6 +7,9 @@ set CPU_MAX_ADDRESS 0xFFFFFFFF
 source [find bitsbytes.tcl]
 source [find memory.tcl]
 source [find mmr_helpers.tcl]
+# Source the ESP common configuration file
+source [find target/esp_common.cfg]
+
 
 if { [info exists CHIPNAME] } {
        set _CHIPNAME $CHIPNAME
@@ -96,6 +99,29 @@ if { $_ONLYCPU != 1 } {
 
 $_TARGETNAME_0 xtensa maskisr on
 $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
+$_TARGETNAME_0 configure -event examine-end {
+       # Need to enable to set 'semihosting_basedir'
+       arm semihosting enable
+       arm semihosting_resexit enable
+       if { [info exists _SEMIHOST_BASEDIR] } {
+               if { $_SEMIHOST_BASEDIR != "" } {
+                       arm semihosting_basedir $_SEMIHOST_BASEDIR
+               }
+       }
+}
+
+if { $_ONLYCPU != 1 } {
+       $_TARGETNAME_1 configure -event examine-end {
+               # Need to enable to set 'semihosting_basedir'
+               arm semihosting enable
+               arm semihosting_resexit enable
+               if { [info exists _SEMIHOST_BASEDIR] } {
+                       if { $_SEMIHOST_BASEDIR != "" } {
+                               arm semihosting_basedir $_SEMIHOST_BASEDIR
+                       }
+               }
+       }
+}
 
 $_TARGETNAME_0 configure -event gdb-attach {
        $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut