/***************************************************************************
* STELLARIS flash is tested on LM3S811, LM3S6965, LM3s3748, more.
***************************************************************************/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
+#include "jtag/interface.h"
#include "imp.h"
#include <target/algorithm.h>
#include <target/armv7m.h>
-
#define DID0_VER(did0) ((did0 >> 28)&0x07)
/* STELLARIS control registers */
#define FLASH_FMA_PRE(x) (2 * (x)) /* for FMPPREx */
#define FLASH_FMA_PPE(x) (2 * (x) + 1) /* for FMPPPEx */
-
static void stellaris_read_clock_info(struct flash_bank *bank);
static int stellaris_mass_erase(struct flash_bank *bank);
-struct stellaris_flash_bank
-{
+struct stellaris_flash_bank {
/* chip id register */
uint32_t did0;
uint32_t did1;
uint32_t dc0;
uint32_t dc1;
- const char * target_name;
+ const char *target_name;
+ uint8_t target_class;
uint32_t sramsiz;
uint32_t flshsz;
const char *mck_desc;
};
-// Autogenerated by contrib/gen-stellaris-part-header.pl
-// From Stellaris Firmware Development Package revision 8049
+/* Autogenerated by contrib/gen-stellaris-part-header.pl */
+/* From Stellaris Firmware Development Package revision 9453 */
static struct {
uint8_t class;
uint8_t partno;
{0x04, 0xC9, "LM3S1R26"},
{0x04, 0x30, "LM3S1W16"},
{0x04, 0x2F, "LM3S1Z16"},
- {0x01, 0xD4, "LM3S2016"},
{0x01, 0x51, "LM3S2110"},
{0x01, 0x84, "LM3S2139"},
{0x03, 0x39, "LM3S2276"},
{0x01, 0x8B, "LM3S6637"},
{0x01, 0xA3, "LM3S6730"},
{0x01, 0x77, "LM3S6753"},
- {0x01, 0xD1, "LM3S6816"},
{0x01, 0xE9, "LM3S6911"},
- {0x01, 0xD3, "LM3S6916"},
{0x01, 0xE8, "LM3S6918"},
{0x01, 0x89, "LM3S6938"},
{0x01, 0x72, "LM3S6950"},
{0x04, 0x1E, "LM3S9BN5"},
{0x04, 0x1F, "LM3S9BN6"},
{0x06, 0x70, "LM3S9C97"},
- {0x06, 0x7A, "LM3S9CN5"},
{0x06, 0xA9, "LM3S9D81"},
{0x06, 0x7E, "LM3S9D90"},
{0x06, 0x92, "LM3S9D92"},
- {0x06, 0xC8, "LM3S9D95"},
{0x06, 0x9D, "LM3S9D96"},
{0x06, 0x7B, "LM3S9DN5"},
{0x06, 0x7C, "LM3S9DN6"},
{0x06, 0xA8, "LM3S9U81"},
{0x06, 0x7D, "LM3S9U90"},
{0x06, 0x90, "LM3S9U92"},
- {0x06, 0xB7, "LM3S9U95"},
{0x06, 0x9B, "LM3S9U96"},
{0x05, 0x18, "LM4F110B2QR"},
{0x05, 0x19, "LM4F110C4QR"},
{0x05, 0x60, "LM4F132E5QC"},
{0x05, 0x61, "LM4F132H5QC"},
{0x05, 0x65, "LM4F132H5QD"},
+ {0x05, 0x70, "LM4F210E5QR"},
+ {0x05, 0x73, "LM4F210H5QR"},
+ {0x05, 0x80, "LM4F211E5QR"},
+ {0x05, 0x83, "LM4F211H5QR"},
+ {0x05, 0xE9, "LM4F212H5BB"},
+ {0x05, 0xC4, "LM4F212H5QC"},
+ {0x05, 0xC6, "LM4F212H5QD"},
{0x05, 0xA0, "LM4F230E5QR"},
{0x05, 0xA1, "LM4F230H5QR"},
{0x05, 0xB0, "LM4F231E5QR"},
{0x05, 0xC1, "LM4F232H5QC"},
{0x05, 0xC5, "LM4F232H5QD"},
{0x05, 0xE5, "LM4FS1AH5BB"},
+ {0x05, 0xEA, "LM4FS1GH5BB"},
{0x05, 0xE4, "LM4FS99H5BB"},
- {0x05, 0xE0, "LM4FSXAH5BB"},
+ {0x05, 0xE1, "LM4FSXLH5BB"},
{0xFF, 0x00, "Unknown Part"}
};
-static char * StellarisClassname[7] =
-{
+static char *StellarisClassname[7] = {
"Sandstorm",
"Fury",
"Unknown",
struct stellaris_flash_bank *stellaris_info;
if (CMD_ARGC < 6)
- {
return ERROR_COMMAND_SYNTAX_ERROR;
- }
stellaris_info = calloc(sizeof(struct stellaris_flash_bank), 1);
bank->base = 0x0;
static int get_stellaris_info(struct flash_bank *bank, char *buf, int buf_size)
{
- int printed, device_class;
+ int printed;
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
if (stellaris_info->did1 == 0)
/* Read main and master clock freqency register */
stellaris_read_clock_info(bank);
- if (DID0_VER(stellaris_info->did0) > 0)
- {
- device_class = (stellaris_info->did0 >> 16) & 0xFF;
- }
- else
- {
- device_class = 0;
- }
printed = snprintf(buf,
buf_size,
"\nTI/LMI Stellaris information: Chip is "
"class %i (%s) %s rev %c%i\n",
- device_class,
- StellarisClassname[device_class],
+ stellaris_info->target_class,
+ StellarisClassname[stellaris_info->target_class],
stellaris_info->target_name,
(int)('A' + ((stellaris_info->did0 >> 8) & 0xFF)),
(int)((stellaris_info->did0) & 0xFF));
buf += printed;
buf_size -= printed;
- if (stellaris_info->num_lockbits > 0)
- {
+ if (stellaris_info->num_lockbits > 0) {
snprintf(buf,
buf_size,
"pagesize: %" PRIi32 ", pages: %d, "
struct target *target = bank->target;
uint32_t usecrl = (stellaris_info->mck_freq/1000000ul-1);
- LOG_DEBUG("usecrl = %i",(int)(usecrl));
+ /* only valid for Sandstorm and Fury class devices */
+ if (stellaris_info->target_class > 1)
+ return;
+
+ LOG_DEBUG("usecrl = %i", (int)(usecrl));
target_write_u32(target, SCB_BASE | USECRL, usecrl);
}
stellaris_info->mck_desc = "";
- switch (oscsrc)
- {
+ switch (oscsrc) {
case 0: /* MOSC */
mainfreq = rcc_xtal[xtal];
break;
did0, did1, stellaris_info->dc0, stellaris_info->dc1);
ver = did0 >> 28;
- if ((ver != 0) && (ver != 1))
- {
+ if ((ver != 0) && (ver != 1)) {
LOG_WARNING("Unknown did0 version, cannot identify target");
return ERROR_FLASH_OPERATION_FAILED;
}
- if (did1 == 0)
- {
+ if (did1 == 0) {
LOG_WARNING("Cannot identify target as a Stellaris");
return ERROR_FLASH_OPERATION_FAILED;
}
ver = did1 >> 28;
fam = (did1 >> 24) & 0xF;
- if (((ver != 0) && (ver != 1)) || (fam != 0))
- {
+ if (((ver != 0) && (ver != 1)) || (fam != 0)) {
LOG_WARNING("Unknown did1 version/family.");
return ERROR_FLASH_OPERATION_FAILED;
}
* always approximate.
*
* For Tempest: IOSC is calibrated, 16 MHz
+ * For Blizzard: IOSC is calibrated, 16 MHz
+ * For Firestorm: IOSC is calibrated, 16 MHz
*/
stellaris_info->iosc_freq = 12000000;
stellaris_info->iosc_desc = " (±30%)";
stellaris_info->xtal_mask = 0x0f;
- switch ((did0 >> 28) & 0x7) {
- case 0: /* Sandstorm */
- /*
- * Current (2009-August) parts seem to be rev C2 and use 12 MHz.
- * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
- * (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
- */
- if (((did0 >> 8) & 0xff) < 2) {
- stellaris_info->iosc_freq = 15000000;
- stellaris_info->iosc_desc = " (±50%)";
- }
- break;
- case 1:
- switch ((did0 >> 16) & 0xff) {
+ /* get device class */
+ if (DID0_VER(did0) > 0) {
+ stellaris_info->target_class = (did0 >> 16) & 0xFF;
+ } else {
+ /* Sandstorm class */
+ stellaris_info->target_class = 0;
+ }
+
+ switch (stellaris_info->target_class) {
+ case 0: /* Sandstorm */
+ /*
+ * Current (2009-August) parts seem to be rev C2 and use 12 MHz.
+ * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
+ * (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
+ */
+ if (((did0 >> 8) & 0xff) < 2) {
+ stellaris_info->iosc_freq = 15000000;
+ stellaris_info->iosc_desc = " (±50%)";
+ }
+ break;
+
case 1: /* Fury */
break;
+
case 4: /* Tempest */
+ case 5: /* Blizzard */
+ case 6: /* Firestorm */
stellaris_info->iosc_freq = 16000000; /* +/- 1% */
stellaris_info->iosc_desc = " (±1%)";
/* FALL THROUGH */
+
case 3: /* DustDevil */
stellaris_info->xtal_mask = 0x1f;
break;
+
default:
LOG_WARNING("Unknown did0 class");
- }
- break;
- default:
- LOG_WARNING("Unknown did0 version");
- break;
}
- for (i = 0; StellarisParts[i].partno; i++)
- {
+ for (i = 0; StellarisParts[i].partno; i++) {
if ((StellarisParts[i].partno == ((did1 >> 16) & 0xFF)) &&
- (StellarisParts[i].class == ((did0 >> 16) & 0xFF)))
+ (StellarisParts[i].class == stellaris_info->target_class))
break;
}
stellaris_info->did1 = did1;
stellaris_info->num_lockbits = 1 + (stellaris_info->dc0 & 0xFFFF);
- stellaris_info->num_pages = 2 *(1 + (stellaris_info->dc0 & 0xFFFF));
+ stellaris_info->num_pages = 2 * (1 + (stellaris_info->dc0 & 0xFFFF));
stellaris_info->pagesize = 1024;
stellaris_info->pages_in_lockregion = 2;
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
struct target *target = bank->target;
- if (bank->target->state != TARGET_HALTED)
- {
+ if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
return ERROR_FLASH_BANK_NOT_PROBED;
if ((first < 0) || (last < first) || (last >= (int)stellaris_info->num_pages))
- {
return ERROR_FLASH_SECTOR_INVALID;
- }
if ((first == 0) && (last == ((int)stellaris_info->num_pages-1)))
- {
return stellaris_mass_erase(bank);
- }
/* Refresh flash controller timing */
stellaris_read_clock_info(bank);
* it might want to process those IRQs.
*/
- for (banknr = first; banknr <= last; banknr++)
- {
+ for (banknr = first; banknr <= last; banknr++) {
/* Address is first word in page */
target_write_u32(target, FLASH_FMA, banknr * stellaris_info->pagesize);
/* Write erase command */
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_ERASE);
/* Wait until erase complete */
- do
- {
+ do {
target_read_u32(target, FLASH_FMC, &flash_fmc);
- }
- while (flash_fmc & FMC_ERASE);
+ } while (flash_fmc & FMC_ERASE);
/* Check acess violations */
target_read_u32(target, FLASH_CRIS, &flash_cris);
- if (flash_cris & (AMASK))
- {
- LOG_WARNING("Error erasing flash page %i, flash_cris 0x%" PRIx32 "", banknr, flash_cris);
+ if (flash_cris & (AMASK)) {
+ LOG_WARNING("Error erasing flash page %i, flash_cris 0x%" PRIx32 "",
+ banknr, flash_cris);
target_write_u32(target, FLASH_CRIS, 0);
return ERROR_FLASH_OPERATION_FAILED;
}
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
struct target *target = bank->target;
- if (bank->target->state != TARGET_HALTED)
- {
+ if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- if (!set)
- {
+ if (!set) {
LOG_ERROR("Hardware doesn't support page-level unprotect. "
"Try the 'recover' command.");
return ERROR_COMMAND_SYNTAX_ERROR;
/* lockregions are 2 pages ... must protect [even..odd] */
if ((first < 0) || (first & 1)
|| (last < first) || !(last & 1)
- || (last >= 2 * stellaris_info->num_lockbits))
- {
+ || (last >= 2 * stellaris_info->num_lockbits)) {
LOG_ERROR("Can't protect unaligned or out-of-range pages.");
return ERROR_FLASH_SECTOR_INVALID;
}
* it might want to process those IRQs.
*/
- LOG_DEBUG("fmppe 0x%" PRIx32 "",fmppe);
+ LOG_DEBUG("fmppe 0x%" PRIx32 "", fmppe);
target_write_u32(target, SCB_BASE | FMPPE, fmppe);
/* Commit FMPPE */
/* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
/* Wait until erase complete */
- do
- {
+ do {
target_read_u32(target, FLASH_FMC, &flash_fmc);
- }
- while (flash_fmc & FMC_COMT);
+ } while (flash_fmc & FMC_COMT);
/* Check acess violations */
target_read_u32(target, FLASH_CRIS, &flash_cris);
- if (flash_cris & (AMASK))
- {
+ if (flash_cris & (AMASK)) {
LOG_WARNING("Error setting flash page protection, flash_cris 0x%" PRIx32 "", flash_cris);
target_write_u32(target, FLASH_CRIS, 0);
return ERROR_FLASH_OPERATION_FAILED;
/* see contib/loaders/flash/stellaris.s for src */
-static const uint8_t stellaris_write_code[] =
-{
-/*
- Call with :
- r0 = buffer address
- r1 = destination address
- r2 = bytecount (in) - endaddr (work)
-
- Used registers:
- r3 = pFLASH_CTRL_BASE
- r4 = FLASHWRITECMD
- r5 = #1
- r6 = bytes written
- r7 = temp reg
-*/
- 0x07,0x4B, /* ldr r3,pFLASH_CTRL_BASE */
- 0x08,0x4C, /* ldr r4,FLASHWRITECMD */
- 0x01,0x25, /* movs r5, 1 */
- 0x00,0x26, /* movs r6, #0 */
-/* mainloop: */
- 0x19,0x60, /* str r1, [r3, #0] */
- 0x87,0x59, /* ldr r7, [r0, r6] */
- 0x5F,0x60, /* str r7, [r3, #4] */
- 0x9C,0x60, /* str r4, [r3, #8] */
-/* waitloop: */
- 0x9F,0x68, /* ldr r7, [r3, #8] */
- 0x2F,0x42, /* tst r7, r5 */
- 0xFC,0xD1, /* bne waitloop */
- 0x04,0x31, /* adds r1, r1, #4 */
- 0x04,0x36, /* adds r6, r6, #4 */
- 0x96,0x42, /* cmp r6, r2 */
- 0xF4,0xD1, /* bne mainloop */
- 0x00,0xBE, /* bkpt #0 */
-/* pFLASH_CTRL_BASE: */
- 0x00,0xD0,0x0F,0x40, /* .word 0x400FD000 */
-/* FLASHWRITECMD: */
- 0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */
+static const uint8_t stellaris_write_code[] = {
+ /* write: */
+ 0xDF, 0xF8, 0x40, 0x40, /* ldr r4, pFLASH_CTRL_BASE */
+ 0xDF, 0xF8, 0x40, 0x50, /* ldr r5, FLASHWRITECMD */
+ /* wait_fifo: */
+ 0xD0, 0xF8, 0x00, 0x80, /* ldr r8, [r0, #0] */
+ 0xB8, 0xF1, 0x00, 0x0F, /* cmp r8, #0 */
+ 0x17, 0xD0, /* beq exit */
+ 0x47, 0x68, /* ldr r7, [r0, #4] */
+ 0x47, 0x45, /* cmp r7, r8 */
+ 0xF7, 0xD0, /* beq wait_fifo */
+ /* mainloop: */
+ 0x22, 0x60, /* str r2, [r4, #0] */
+ 0x02, 0xF1, 0x04, 0x02, /* add r2, r2, #4 */
+ 0x57, 0xF8, 0x04, 0x8B, /* ldr r8, [r7], #4 */
+ 0xC4, 0xF8, 0x04, 0x80, /* str r8, [r4, #4] */
+ 0xA5, 0x60, /* str r5, [r4, #8] */
+ /* busy: */
+ 0xD4, 0xF8, 0x08, 0x80, /* ldr r8, [r4, #8] */
+ 0x18, 0xF0, 0x01, 0x0F, /* tst r8, #1 */
+ 0xFA, 0xD1, /* bne busy */
+ 0x8F, 0x42, /* cmp r7, r1 */
+ 0x28, 0xBF, /* it cs */
+ 0x00, 0xF1, 0x08, 0x07, /* addcs r7, r0, #8 */
+ 0x47, 0x60, /* str r7, [r0, #4] */
+ 0x01, 0x3B, /* subs r3, r3, #1 */
+ 0x03, 0xB1, /* cbz r3, exit */
+ 0xE2, 0xE7, /* b wait_fifo */
+ /* exit: */
+ 0x00, 0xBE, /* bkpt #0 */
+
+ /* pFLASH_CTRL_BASE: */
+ 0x00, 0xD0, 0x0F, 0x40, /* .word 0x400FD000 */
+ /* FLASHWRITECMD: */
+ 0x01, 0x00, 0x42, 0xA4 /* .word 0xA4420001 */
};
-
static int stellaris_write_block(struct flash_bank *bank,
uint8_t *buffer, uint32_t offset, uint32_t wcount)
{
struct working_area *source;
struct working_area *write_algorithm;
uint32_t address = bank->base + offset;
- struct reg_param reg_params[3];
+ struct reg_param reg_params[4];
struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
bank, buffer, offset, wcount);
/* flash write code */
- if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK)
- {
+ if (target_alloc_working_area(target, sizeof(stellaris_write_code),
+ &write_algorithm) != ERROR_OK) {
LOG_DEBUG("no working area for block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
buffer_size = wcount * 4;
/* memory buffer */
- while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
- {
+ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
buffer_size /= 2;
- if (buffer_size <= buf_min)
- {
+ if (buffer_size <= buf_min) {
target_free_working_area(target, write_algorithm);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
target_name(target), (unsigned) buffer_size);
};
- retval = target_write_buffer(target, write_algorithm->address,
+ target_write_buffer(target, write_algorithm->address,
sizeof(stellaris_write_code),
(uint8_t *) stellaris_write_code);
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
+ init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
- while (wcount > 0)
- {
- uint32_t thisrun_count = (wcount > (buffer_size / 4)) ? (buffer_size / 4) : wcount;
-
- target_write_buffer(target, source->address, thisrun_count * 4, buffer);
-
- buf_set_u32(reg_params[0].value, 0, 32, source->address);
- buf_set_u32(reg_params[1].value, 0, 32, address);
- buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
- LOG_DEBUG("Algorithm flash write %u words to 0x%" PRIx32
- ", %u remaining",
- (unsigned) thisrun_count, address,
- (unsigned) (wcount - thisrun_count));
- retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
- write_algorithm->address,
- 0,
- 10000, &armv7m_info);
- if (retval != ERROR_OK)
- {
- LOG_ERROR("error %d executing stellaris "
- "flash write algorithm",
- retval);
- retval = ERROR_FLASH_OPERATION_FAILED;
- break;
- }
+ buf_set_u32(reg_params[0].value, 0, 32, source->address);
+ buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
+ buf_set_u32(reg_params[2].value, 0, 32, address);
+ buf_set_u32(reg_params[3].value, 0, 32, wcount);
- buffer += thisrun_count * 4;
- address += thisrun_count * 4;
- wcount -= thisrun_count;
- }
+ retval = target_run_flash_async_algorithm(target, buffer, wcount, 4,
+ 0, NULL,
+ 4, reg_params,
+ source->address, source->size,
+ write_algorithm->address, 0,
+ &armv7m_info);
- /* REVISIT we could speed up writing multi-section images by
- * not freeing the initialized write_algorithm this way.
- */
+ if (retval == ERROR_FLASH_OPERATION_FAILED)
+ LOG_ERROR("error %d executing stellaris flash write algorithm", retval);
target_free_working_area(target, write_algorithm);
target_free_working_area(target, source);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
return retval;
}
-static int stellaris_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+static int stellaris_write(struct flash_bank *bank, uint8_t *buffer,
+ uint32_t offset, uint32_t count)
{
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
struct target *target = bank->target;
uint32_t bytes_written = 0;
int retval;
- if (bank->target->state != TARGET_HALTED)
- {
+ if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (stellaris_info->did1 == 0)
return ERROR_FLASH_BANK_NOT_PROBED;
- if (offset & 0x3)
- {
+ if (offset & 0x3) {
LOG_WARNING("offset size must be word aligned");
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
*/
/* multiple words to be programmed? */
- if (words_remaining > 0)
- {
+ if (words_remaining > 0) {
/* try using a block write */
retval = stellaris_write_block(bank, buffer, offset,
words_remaining);
- if (retval != ERROR_OK)
- {
- if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
- {
+ if (retval != ERROR_OK) {
+ if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
LOG_DEBUG("writing flash word-at-a-time");
- }
- else if (retval == ERROR_FLASH_OPERATION_FAILED)
- {
+ } else if (retval == ERROR_FLASH_OPERATION_FAILED) {
/* if an error occured, we examine the reason, and quit */
target_read_u32(target, FLASH_CRIS, &flash_cris);
LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32 "", flash_cris);
return ERROR_FLASH_OPERATION_FAILED;
}
- }
- else
- {
+ } else {
buffer += words_remaining * 4;
address += words_remaining * 4;
words_remaining = 0;
}
}
- while (words_remaining > 0)
- {
+ while (words_remaining > 0) {
if (!(address & 0xff))
LOG_DEBUG("0x%" PRIx32 "", address);
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
/* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
/* Wait until write complete */
- do
- {
+ do {
target_read_u32(target, FLASH_FMC, &flash_fmc);
} while (flash_fmc & FMC_WRITE);
words_remaining--;
}
- if (bytes_remaining)
- {
+ if (bytes_remaining) {
uint8_t last_word[4] = {0xff, 0xff, 0xff, 0xff};
/* copy the last remaining bytes into the write buffer */
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
/* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
/* Wait until write complete */
- do
- {
+ do {
target_read_u32(target, FLASH_FMC, &flash_fmc);
} while (flash_fmc & FMC_WRITE);
}
/* Check access violations */
target_read_u32(target, FLASH_CRIS, &flash_cris);
- if (flash_cris & (AMASK))
- {
+ if (flash_cris & (AMASK)) {
LOG_DEBUG("flash_cris 0x%" PRIx32 "", flash_cris);
return ERROR_FLASH_OPERATION_FAILED;
}
if (retval != ERROR_OK)
return retval;
- if (bank->sectors)
- {
+ if (bank->sectors) {
free(bank->sectors);
bank->sectors = NULL;
}
bank->size = 1024 * stellaris_info->num_pages;
bank->num_sectors = stellaris_info->num_pages;
bank->sectors = calloc(bank->num_sectors, sizeof(struct flash_sector));
- for (int i = 0; i < bank->num_sectors; i++)
- {
+ for (int i = 0; i < bank->num_sectors; i++) {
bank->sectors[i].offset = i * stellaris_info->pagesize;
bank->sectors[i].size = stellaris_info->pagesize;
bank->sectors[i].is_erased = -1;
stellaris_info = bank->driver_priv;
target = bank->target;
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
target_write_u32(target, FLASH_FMA, 0);
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
/* Wait until erase complete */
- do
- {
+ do {
target_read_u32(target, FLASH_FMC, &flash_fmc);
- }
- while (flash_fmc & FMC_MERASE);
+ } while (flash_fmc & FMC_MERASE);
/* if device has > 128k, then second erase cycle is needed
* this is only valid for older devices, but will not hurt */
- if (stellaris_info->num_pages * stellaris_info->pagesize > 0x20000)
- {
+ if (stellaris_info->num_pages * stellaris_info->pagesize > 0x20000) {
target_write_u32(target, FLASH_FMA, 0x20000);
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
/* Wait until erase complete */
- do
- {
+ do {
target_read_u32(target, FLASH_FMC, &flash_fmc);
- }
- while (flash_fmc & FMC_MERASE);
+ } while (flash_fmc & FMC_MERASE);
}
return ERROR_OK;
int i;
if (CMD_ARGC < 1)
- {
return ERROR_COMMAND_SYNTAX_ERROR;
- }
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
if (ERROR_OK != retval)
return retval;
- if (stellaris_mass_erase(bank) == ERROR_OK)
- {
+ if (stellaris_mass_erase(bank) == ERROR_OK) {
/* set all sectors as erased */
for (i = 0; i < bank->num_sectors; i++)
- {
bank->sectors[i].is_erased = 1;
- }
command_print(CMD_CTX, "stellaris mass erase complete");
- }
- else
- {
+ } else
command_print(CMD_CTX, "stellaris mass erase failed");
- }
return ERROR_OK;
}
LOG_ERROR("Can't recover Stellaris flash without SRST");
return ERROR_FAIL;
}
- jtag_add_reset(0, 1);
+ adapter_assert_reset();
for (int i = 0; i < 5; i++) {
retval = dap_to_swd(bank->target);
}
/* de-assert SRST */
- jtag_add_reset(0, 0);
+ adapter_deassert_reset();
retval = jtag_execute_queue();
/* wait 400+ msec ... OK, "1+ second" is simpler */
.name = "stellaris",
.mode = COMMAND_EXEC,
.help = "Stellaris flash command group",
+ .usage = "",
.chain = stellaris_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
.read = default_flash_read,
.probe = stellaris_probe,
.auto_probe = stellaris_probe,
- .erase_check = default_flash_mem_blank_check,
+ .erase_check = default_flash_blank_check,
.protect_check = stellaris_protect_check,
.info = get_stellaris_info,
};
projects / fw / openocd / blobdiff