X-Git-Url: https://git.gag.com/?p=fw%2Fopenalt;a=blobdiff_plain;f=adc%2Fadc.c;h=a1a08d56d7618f76bd12536621eb7eee7f89d3d1;hp=cc7158eff2fa0e684b6c2a926f383ba3ea7dbcfd;hb=364c8190eed3a8339542303243370f1da8fee1dd;hpb=6fa7af38a539cb6605921c0b1f442416eaf678cf

diff --git a/adc/adc.c b/adc/adc.c
index cc7158e..a1a08d5 100644
--- a/adc/adc.c
+++ b/adc/adc.c
@@ -35,10 +35,28 @@ void adcInit (void)
 
 void adcStartXYZ (void)
 {
-//  AD1_CR = AD_CR_CLKS10 | AD_CR_PDN | ((11 - 1) << AD_CR_CLKDIVSHIFT) | AD_CR_SEL3 | AD_CR_SEL4 | AD_CR_SEL6 | AD_CR_BURST;
-//  AD1_CR = AD_CR_CLKS10 | AD_CR_PDN | ((11 - 1) << AD_CR_CLKDIVSHIFT) | AD_CR_SEL3 | AD_CR_BURST;
-  AD1_CR = AD_CR_CLKS10 | AD_CR_PDN | ((11 - 1) << AD_CR_CLKDIVSHIFT) | AD_CR_SEL6 | AD_CR_BURST;
-  AD1_CR |= AD_CR_START_NOW;
+  unsigned portLONG ulCompareMatch;
+
+  // configure MAT0.1 ... assumes TIMER0 already initialized and running
+
+  // Calculate the match value required for 1khz ADC trigger rate
+  ulCompareMatch = configCPU_CLOCK_HZ / 1000;
+
+  // Account for prescaler, protecting against divide by zero.
+  #if portPRESCALE_VALUE != 0
+  {
+	ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+  }
+  #endif
+  T0_MR1 = ulCompareMatch;
+  
+  // burst sample 3 channels of accelerometer triggering on MAT0.1
+  AD1_CR = AD_CR_CLKS10 | AD_CR_PDN | ((11 - 1) << AD_CR_CLKDIVSHIFT) | AD_CR_SEL3 | AD_CR_SEL4 | AD_CR_SEL6 | AD_CR_BURST;
+  AD1_CR |= AD_CR_START_MAT01;
+
+// following works for one channel repeated sampling
+//  AD1_CR = AD_CR_CLKS10 | AD_CR_PDN | ((11 - 1) << AD_CR_CLKDIVSHIFT) | AD_CR_SEL6 | AD_CR_BURST;
+//  AD1_CR |= AD_CR_START_NOW;
 
 // wait for conversion to complete
 //  while (!(AD1_DR3 & AD_DR_DONE))
@@ -51,7 +69,7 @@ void adcStartXYZ (void)
 //
 int adcReadX (void)
 {
-//  while (!(AD1_DR3 & AD_DR_DONE)) ;
+  while (!(AD1_DR3 & AD_DR_DONE)) ;
   return ((AD1_DR3 & AD_DR_RESULTMASK) >> AD_DR_RESULTSHIFT);
 }
 
@@ -60,7 +78,7 @@ int adcReadX (void)
 //
 int adcReadY (void)
 {
-//  while (!(AD1_DR4 & AD_DR_DONE)) ;
+  while (!(AD1_DR4 & AD_DR_DONE)) ;
   return ((AD1_DR4 & AD_DR_RESULTMASK) >> AD_DR_RESULTSHIFT);
 }