From 877d4643b45ca2099f602390b71e1c77d5e11ef1 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 16 Feb 2022 21:38:25 -0800 Subject: [PATCH] altos/stmf0: Add casts to reduce -Wconversion warnings. Use AO_TICK_TYPE No bugs identified. Serial timeout types updated to AO_TICK_TYPE. Signed-off-by: Keith Packard --- src/stmf0/ao_adc_fast.c | 10 ++-- src/stmf0/ao_adc_stm.c | 20 +++---- src/stmf0/ao_arch_funcs.h | 10 ++-- src/stmf0/ao_beep_stm.c | 4 +- src/stmf0/ao_boot_pin.c | 2 +- src/stmf0/ao_crc.h | 2 +- src/stmf0/ao_dma_stm.c | 6 +-- src/stmf0/ao_exti_stm.c | 2 +- src/stmf0/ao_flash_stm.c | 4 +- src/stmf0/ao_gpio.c | 8 +-- src/stmf0/ao_led_stmf0.c | 4 +- src/stmf0/ao_serial_stm.c | 16 +++--- src/stmf0/ao_timer.c | 10 ++-- src/stmf0/ao_usb_stm.c | 108 +++++++++++++++++++------------------- src/stmf0/stm32f0.h | 66 +++++++++++------------ 15 files changed, 136 insertions(+), 136 deletions(-) diff --git a/src/stmf0/ao_adc_fast.c b/src/stmf0/ao_adc_fast.c index fbf4ad2e..51860ced 100644 --- a/src/stmf0/ao_adc_fast.c +++ b/src/stmf0/ao_adc_fast.c @@ -89,7 +89,7 @@ ao_adc_init(void) /* Reset ADC */ stm_rcc.apb2rstr |= (1 << STM_RCC_APB2RSTR_ADCRST); - stm_rcc.apb2rstr &= ~(1 << STM_RCC_APB2RSTR_ADCRST); + stm_rcc.apb2rstr &= ~(1UL << STM_RCC_APB2RSTR_ADCRST); /* Turn on ADC pins */ stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR; @@ -160,11 +160,11 @@ ao_adc_init(void) stm_adc.smpr = STM_ADC_SMPR_SMP_1_5 << STM_ADC_SMPR_SMP; /* Turn off enable and start */ - stm_adc.cr &= ~((1 << STM_ADC_CR_ADEN) | (1 << STM_ADC_CR_ADSTART)); + stm_adc.cr &= ~((1UL << STM_ADC_CR_ADEN) | (1 << STM_ADC_CR_ADSTART)); /* Calibrate */ - stm_adc.cr |= (1 << STM_ADC_CR_ADCAL); - while ((stm_adc.cr & (1 << STM_ADC_CR_ADCAL)) != 0) + stm_adc.cr |= (1UL << STM_ADC_CR_ADCAL); + while ((stm_adc.cr & (1UL << STM_ADC_CR_ADCAL)) != 0) ; /* Enable */ @@ -197,7 +197,7 @@ ao_adc_init(void) stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN); /* Set ADC to use DMA channel 1 (option 1) */ - stm_syscfg.cfgr1 &= ~(1 << STM_SYSCFG_CFGR1_ADC_DMA_RMP); + stm_syscfg.cfgr1 &= ~(1UL << STM_SYSCFG_CFGR1_ADC_DMA_RMP); ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1)); } diff --git a/src/stmf0/ao_adc_stm.c b/src/stmf0/ao_adc_stm.c index d48726a1..e5471b12 100644 --- a/src/stmf0/ao_adc_stm.c +++ b/src/stmf0/ao_adc_stm.c @@ -178,7 +178,7 @@ ao_adc_init(void) /* Reset ADC */ stm_rcc.apb2rstr |= (1 << STM_RCC_APB2RSTR_ADCRST); - stm_rcc.apb2rstr &= ~(1 << STM_RCC_APB2RSTR_ADCRST); + stm_rcc.apb2rstr &= ~(1UL << STM_RCC_APB2RSTR_ADCRST); /* Turn on ADC pins */ stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR; @@ -251,8 +251,8 @@ ao_adc_init(void) #endif /* Wait for ADC to be idle */ - while (stm_adc.cr & ((1 << STM_ADC_CR_ADCAL) | - (1 << STM_ADC_CR_ADDIS))) + while (stm_adc.cr & ((1UL << STM_ADC_CR_ADCAL) | + (1UL << STM_ADC_CR_ADDIS))) ; /* Disable */ @@ -263,10 +263,10 @@ ao_adc_init(void) } /* Turn off everything */ - stm_adc.cr &= ~((1 << STM_ADC_CR_ADCAL) | - (1 << STM_ADC_CR_ADSTP) | - (1 << STM_ADC_CR_ADSTART) | - (1 << STM_ADC_CR_ADEN)); + stm_adc.cr &= ~((1UL << STM_ADC_CR_ADCAL) | + (1UL << STM_ADC_CR_ADSTP) | + (1UL << STM_ADC_CR_ADSTART) | + (1UL << STM_ADC_CR_ADEN)); /* Configure */ stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) | /* analog watchdog channel 0 */ @@ -297,8 +297,8 @@ ao_adc_init(void) (0 << STM_ADC_CCR_VREFEN)); /* Calibrate */ - stm_adc.cr |= (1 << STM_ADC_CR_ADCAL); - while ((stm_adc.cr & (1 << STM_ADC_CR_ADCAL)) != 0) + stm_adc.cr |= (1UL << STM_ADC_CR_ADCAL); + while ((stm_adc.cr & (1UL << STM_ADC_CR_ADCAL)) != 0) ; /* Enable */ @@ -313,7 +313,7 @@ ao_adc_init(void) stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN); /* Set ADC to use DMA channel 1 (option 1) */ - stm_syscfg.cfgr1 &= ~(1 << STM_SYSCFG_CFGR1_ADC_DMA_RMP); + stm_syscfg.cfgr1 &= ~(1UL << STM_SYSCFG_CFGR1_ADC_DMA_RMP); ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1)); diff --git a/src/stmf0/ao_arch_funcs.h b/src/stmf0/ao_arch_funcs.h index d46899d5..8a173b57 100644 --- a/src/stmf0/ao_arch_funcs.h +++ b/src/stmf0/ao_arch_funcs.h @@ -151,7 +151,7 @@ ao_spi_recv_byte(uint8_t spi_index) stm_spi->dr = 0xff; while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE))) ; - return stm_spi->dr; + return (uint8_t) stm_spi->dr; } void @@ -215,16 +215,16 @@ static inline void ao_enable_port(struct stm_gpio *port) static inline void ao_disable_port(struct stm_gpio *port) { if ((port) == &stm_gpioa) { - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPAEN); + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_IOPAEN); ao_power_unregister(&ao_power_gpioa); } else if ((port) == &stm_gpiob) { - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPBEN); + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_IOPBEN); ao_power_unregister(&ao_power_gpiob); } else if ((port) == &stm_gpioc) { - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPCEN); + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_IOPCEN); ao_power_unregister(&ao_power_gpioc); } else if ((port) == &stm_gpiof) { - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPFEN); + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_IOPFEN); ao_power_unregister(&ao_power_gpiof); } } diff --git a/src/stmf0/ao_beep_stm.c b/src/stmf0/ao_beep_stm.c index 39022da1..751e611a 100644 --- a/src/stmf0/ao_beep_stm.c +++ b/src/stmf0/ao_beep_stm.c @@ -58,7 +58,7 @@ disable(void) #if BEEPER_TIMER == 1 timer.bdtr = 0; #endif - stm_rcc_enr &= ~(1 << STM_RCC_TIMER); + stm_rcc_enr &= ~(1UL << STM_RCC_TIMER); /* Disconnect the timer from the pin */ stm_afr_set(BEEPER_PORT, BEEPER_PIN, STM_AFR_NONE); @@ -389,5 +389,5 @@ ao_beep_init(void) ao_enable_output(BEEPER_PORT, BEEPER_PIN, 0); /* Leave the timer off until requested */ - stm_rcc_enr &= ~(1 << STM_RCC_TIMER); + stm_rcc_enr &= ~(1UL << STM_RCC_TIMER); } diff --git a/src/stmf0/ao_boot_pin.c b/src/stmf0/ao_boot_pin.c index f21ce1b2..b289b804 100644 --- a/src/stmf0/ao_boot_pin.c +++ b/src/stmf0/ao_boot_pin.c @@ -41,6 +41,6 @@ ao_boot_check_pin(void) /* Reset the chip to turn off the port and the power interface clock */ ao_gpio_set_mode(&AO_BOOT_APPLICATION_GPIO, AO_BOOT_APPLICATION_PIN, 0); ao_disable_port(&AO_BOOT_APPLICATION_GPIO); - stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_PWREN); + stm_rcc.apb1enr &= ~(1UL << STM_RCC_APB1ENR_PWREN); return v == AO_BOOT_APPLICATION_VALUE; } diff --git a/src/stmf0/ao_crc.h b/src/stmf0/ao_crc.h index b6d91023..59e7e7a6 100644 --- a/src/stmf0/ao_crc.h +++ b/src/stmf0/ao_crc.h @@ -36,7 +36,7 @@ static inline uint16_t ao_crc_in_32_out_16(uint32_t v) { stm_crc.dr.u32 = v; v = stm_crc.dr.u32; - return v ^ (v >> 16); + return (uint16_t) (v ^ (v >> 16)); } static inline uint16_t diff --git a/src/stmf0/ao_dma_stm.c b/src/stmf0/ao_dma_stm.c index f3fa13b4..ef551786 100644 --- a/src/stmf0/ao_dma_stm.c +++ b/src/stmf0/ao_dma_stm.c @@ -111,10 +111,10 @@ ao_dma_start(uint8_t index) void ao_dma_done_transfer(uint8_t index) { - stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN); + stm_dma.channel[index].ccr &= ~(1UL << STM_DMA_CCR_EN); ao_arch_critical( if (--ao_dma_active == 0) - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_DMAEN); + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_DMAEN); ); if (ao_dma_allocated[index]) ao_dma_mutex[index] = 0; @@ -125,7 +125,7 @@ ao_dma_done_transfer(uint8_t index) void ao_dma_abort(uint8_t index) { - stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN); + stm_dma.channel[index].ccr &= ~(1UL << STM_DMA_CCR_EN); ao_wakeup(&ao_dma_done[index]); } diff --git a/src/stmf0/ao_exti_stm.c b/src/stmf0/ao_exti_stm.c index 77c59d05..bba2064d 100644 --- a/src/stmf0/ao_exti_stm.c +++ b/src/stmf0/ao_exti_stm.c @@ -24,7 +24,7 @@ static void (*ao_exti_callback[16])(void); uint32_t ao_last_exti; static void ao_exti_range_isr(uint8_t first, uint8_t last, uint16_t mask) { - uint16_t pending = (ao_last_exti = stm_exti.pr) & mask; + uint16_t pending = (uint16_t) ((ao_last_exti = stm_exti.pr) & mask); uint8_t pin; static uint16_t last_mask; static uint8_t last_pin; diff --git a/src/stmf0/ao_flash_stm.c b/src/stmf0/ao_flash_stm.c index 896d536b..a33099ab 100644 --- a/src/stmf0/ao_flash_stm.c +++ b/src/stmf0/ao_flash_stm.c @@ -63,7 +63,7 @@ _ao_flash_erase_page(uint32_t *page) ao_flash_wait_bsy(); - stm_flash.cr &= ~(1 << STM_FLASH_CR_PER); + stm_flash.cr &= ~(1UL << STM_FLASH_CR_PER); } static uint32_t @@ -115,7 +115,7 @@ _ao_flash_page(uint16_t *dst, uint16_t *src) ao_flash_wait_bsy(); } - stm_flash.cr &= ~(1 << STM_FLASH_CR_PG); + stm_flash.cr &= ~(1UL << STM_FLASH_CR_PG); } void diff --git a/src/stmf0/ao_gpio.c b/src/stmf0/ao_gpio.c index 024ff948..a21ce4fa 100644 --- a/src/stmf0/ao_gpio.c +++ b/src/stmf0/ao_gpio.c @@ -23,13 +23,13 @@ ao_gpio_suspend(void *arg) { struct stm_gpio *port = arg; if (port == &stm_gpioa) - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPAEN); + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_IOPAEN); else if ((port) == &stm_gpiob) - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPBEN); + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_IOPBEN); else if ((port) == &stm_gpioc) - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPCEN); + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_IOPCEN); else if ((port) == &stm_gpiof) - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPFEN); + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_IOPFEN); } static void diff --git a/src/stmf0/ao_led_stmf0.c b/src/stmf0/ao_led_stmf0.c index 63593aff..9448a15a 100644 --- a/src/stmf0/ao_led_stmf0.c +++ b/src/stmf0/ao_led_stmf0.c @@ -52,7 +52,7 @@ void ao_led_set(AO_LED_TYPE colors) { AO_LED_TYPE on = colors & LEDS_AVAILABLE; - AO_LED_TYPE off = ~colors & LEDS_AVAILABLE; + AO_LED_TYPE off = (AO_LED_TYPE) (~colors & LEDS_AVAILABLE); ao_led_off(off); ao_led_on(on); @@ -78,7 +78,7 @@ ao_led_init(void) #ifdef LED_PORT stm_rcc.ahbenr |= (1 << LED_PORT_ENABLE); - LED_PORT->odr &= ~LEDS_AVAILABLE; + LED_PORT->odr &= (uint32_t) ~LEDS_AVAILABLE; #else #ifdef LED_PORT_0 stm_rcc.ahbenr |= (1 << LED_PORT_0_ENABLE); diff --git a/src/stmf0/ao_serial_stm.c b/src/stmf0/ao_serial_stm.c index ef35394a..21ea8614 100644 --- a/src/stmf0/ao_serial_stm.c +++ b/src/stmf0/ao_serial_stm.c @@ -75,7 +75,7 @@ _ao_usart_rx(struct ao_stm_usart *usart, int is_stdin) } #endif } else { - usart->reg->cr1 &= ~(1 << STM_USART_CR1_RXNEIE); + usart->reg->cr1 &= ~(1UL << STM_USART_CR1_RXNEIE); } } } @@ -86,11 +86,11 @@ ao_usart_isr(struct ao_stm_usart *usart, int is_stdin) _ao_usart_rx(usart, is_stdin); if (!_ao_usart_tx_start(usart)) - usart->reg->cr1 &= ~(1<< STM_USART_CR1_TXEIE); + usart->reg->cr1 &= ~(1UL << STM_USART_CR1_TXEIE); if (usart->reg->isr & (1 << STM_USART_ISR_TC)) { usart->tx_running = 0; - usart->reg->cr1 &= ~(1 << STM_USART_CR1_TCIE); + usart->reg->cr1 &= ~(1UL << STM_USART_CR1_TCIE); if (usart->draining) { usart->draining = 0; ao_wakeup(&usart->tx_fifo); @@ -136,7 +136,7 @@ ao_usart_getchar(struct ao_stm_usart *usart) } static inline uint8_t -_ao_usart_sleep_for(struct ao_stm_usart *usart, uint16_t timeout) +_ao_usart_sleep_for(struct ao_stm_usart *usart, AO_TICK_TYPE timeout) { return ao_sleep_for(&usart->rx_fifo, timeout); } @@ -281,7 +281,7 @@ _ao_serial1_pollchar(void) } uint8_t -_ao_serial1_sleep_for(uint16_t timeout) +_ao_serial1_sleep_for(AO_TICK_TYPE timeout) { return _ao_usart_sleep_for(&ao_stm_usart1, timeout); } @@ -325,7 +325,7 @@ _ao_serial2_pollchar(void) } uint8_t -_ao_serial2_sleep_for(uint16_t timeout) +_ao_serial2_sleep_for(AO_TICK_TYPE timeout) { return _ao_usart_sleep_for(&ao_stm_usart2, timeout); } @@ -379,10 +379,10 @@ void ao_serial_shutdown(void) { #if HAS_SERIAL_1 - stm_rcc.apb2enr &= ~(1 << STM_RCC_APB2ENR_USART1EN); + stm_rcc.apb2enr &= ~(1UL << STM_RCC_APB2ENR_USART1EN); #endif #if HAS_SERIAL_2 - stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USART2EN); + stm_rcc.apb1enr &= ~(1UL << STM_RCC_APB1ENR_USART2EN); #endif } diff --git a/src/stmf0/ao_timer.c b/src/stmf0/ao_timer.c index 5b180074..b7047e10 100644 --- a/src/stmf0/ao_timer.c +++ b/src/stmf0/ao_timer.c @@ -183,7 +183,7 @@ ao_clock_normal_start(void) #if AO_HSE_BYPASS stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP); #else - stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP); + stm_rcc.cr &= ~(1UL << STM_RCC_CR_HSEBYP); #endif /* Enable HSE clock */ stm_rcc.cr |= (1 << STM_RCC_CR_HSEON); @@ -191,8 +191,8 @@ ao_clock_normal_start(void) asm("nop"); /* Disable the PLL */ - stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON); - while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)) + stm_rcc.cr &= ~(1UL << STM_RCC_CR_PLLON); + while (stm_rcc.cr & (1UL << STM_RCC_CR_PLLRDY)) asm("nop"); /* Set multiplier */ @@ -201,7 +201,7 @@ ao_clock_normal_start(void) cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL); /* PLL source */ - cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC); + cfgr &= ~(1UL << STM_RCC_CFGR_PLLSRC); cfgr |= (STM_RCC_CFGR_PLLSRC_TARGET_CLOCK << STM_RCC_CFGR_PLLSRC); stm_rcc.cfgr = cfgr; @@ -261,7 +261,7 @@ ao_clock_normal_switch(void) } #if !AO_HSI && !AO_NEED_HSI /* Turn off the HSI clock */ - stm_rcc.cr &= ~(1 << STM_RCC_CR_HSION); + stm_rcc.cr &= ~(1UL << STM_RCC_CR_HSION); #endif #ifdef STM_PLLSRC /* USB PLL source */ diff --git a/src/stmf0/ao_usb_stm.c b/src/stmf0/ao_usb_stm.c index b736d389..0525d11f 100644 --- a/src/stmf0/ao_usb_stm.c +++ b/src/stmf0/ao_usb_stm.c @@ -317,9 +317,9 @@ _ao_usb_set_stat_tx(int ep, uint32_t stat_tx) epr_old = epr_write = stm_usb.epr[ep].r; epr_write &= STM_USB_EPR_PRESERVE_MASK; epr_write |= STM_USB_EPR_INVARIANT; - epr_write |= set_toggle(epr_old, - STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX, - stat_tx << STM_USB_EPR_STAT_TX); + epr_write |= (uint16_t) set_toggle(epr_old, + STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX, + stat_tx << STM_USB_EPR_STAT_TX); stm_usb.epr[ep].r = epr_write; _tx_dbg1("set_stat_tx bottom", epr_write); } @@ -341,8 +341,8 @@ _ao_usb_toggle_dtog(int ep, uint32_t dtog_rx, uint32_t dtog_tx) epr_write = stm_usb.epr[ep].r; epr_write &= STM_USB_EPR_PRESERVE_MASK; epr_write |= STM_USB_EPR_INVARIANT; - epr_write |= ((dtog_rx << STM_USB_EPR_DTOG_RX) | - (dtog_tx << STM_USB_EPR_DTOG_TX)); + epr_write |= (uint16_t) ((dtog_rx << STM_USB_EPR_DTOG_RX) | + (dtog_tx << STM_USB_EPR_DTOG_TX)); stm_usb.epr[ep].r = epr_write; _tx_dbg1("toggle_dtog bottom", epr_write); } @@ -354,9 +354,9 @@ _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) { epr_write = epr_old = stm_usb.epr[ep].r; epr_write &= STM_USB_EPR_PRESERVE_MASK; epr_write |= STM_USB_EPR_INVARIANT; - epr_write |= set_toggle(epr_old, - STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX, - stat_rx << STM_USB_EPR_STAT_RX); + epr_write |= (uint16_t) set_toggle(epr_old, + STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX, + stat_rx << STM_USB_EPR_STAT_RX); stm_usb.epr[ep].r = epr_write; } @@ -381,22 +381,22 @@ ao_usb_init_ep(uint8_t ep, uint16_t addr, uint16_t type, ao_arch_block_interrupts(); epr = stm_usb.epr[ep].r; - epr = ((0 << STM_USB_EPR_CTR_RX) | - (type << STM_USB_EPR_EP_TYPE) | - (kind << STM_USB_EPR_EP_KIND) | - (0 << STM_USB_EPR_CTR_TX) | - (addr << STM_USB_EPR_EA) | - set_toggle(epr, - - (1 << STM_USB_EPR_DTOG_RX) | - (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | - (1 << STM_USB_EPR_DTOG_TX) | - (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX), - - (dtog_rx << STM_USB_EPR_DTOG_RX) | - (stat_rx << STM_USB_EPR_STAT_RX) | - (dtog_tx << STM_USB_EPR_DTOG_TX) | - (stat_tx << STM_USB_EPR_STAT_TX))); + epr = (uint16_t) ((0UL << STM_USB_EPR_CTR_RX) | + ((uint32_t) type << STM_USB_EPR_EP_TYPE) | + ((uint32_t) kind << STM_USB_EPR_EP_KIND) | + (0UL << STM_USB_EPR_CTR_TX) | + ((uint32_t) addr << STM_USB_EPR_EA) | + set_toggle(epr, + + (1UL << STM_USB_EPR_DTOG_RX) | + (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | + (1UL << STM_USB_EPR_DTOG_TX) | + (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX), + + ((uint32_t) dtog_rx << STM_USB_EPR_DTOG_RX) | + ((uint32_t) stat_rx << STM_USB_EPR_STAT_RX) | + ((uint32_t) dtog_tx << STM_USB_EPR_DTOG_TX) | + ((uint32_t) stat_tx << STM_USB_EPR_STAT_TX))); stm_usb.epr[ep].r = epr; ao_arch_release_interrupts(); debug ("writing epr[%d] 0x%04x wrote 0x%04x\n", @@ -418,30 +418,30 @@ ao_usb_alloc_buffers(void) sram_addr += AO_USB_CONTROL_SIZE; #if AO_USB_HAS_INT - sram_addr += (sram_addr & 1); + sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1)); ao_usb_int_tx_offset = sram_addr; sram_addr += AO_USB_INT_SIZE; #endif #if AO_USB_HAS_OUT - sram_addr += (sram_addr & 1); + sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1)); ao_usb_out_rx_offset = sram_addr; sram_addr += AO_USB_OUT_SIZE * 2; #endif #if AO_USB_HAS_IN - sram_addr += (sram_addr & 1); + sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1)); ao_usb_in_tx_offset = sram_addr; sram_addr += AO_USB_IN_SIZE * 2; #endif #if AO_USB_HAS_IN2 - sram_addr += (sram_addr & 1); + sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1)); ao_usb_in_tx2_offset = sram_addr; sram_addr += AO_USB_IN_SIZE * 2; #endif #if AO_USB_HAS_IN3 - sram_addr += (sram_addr & 1); + sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1)); ao_usb_in_tx3_offset = sram_addr; sram_addr += AO_USB_IN_SIZE * 2; #endif @@ -463,7 +463,7 @@ ao_usb_init_btable(void) static void ao_usb_set_ep0(void) { - int e; + uint8_t e; ao_usb_init_btable(); @@ -641,7 +641,7 @@ ao_usb_tx_byte(uint16_t offset, uint8_t byte) { if (offset & 1) ao_usb_packet_put(offset - 1, - ao_usb_packet_get(offset - 1) | ((uint16_t) byte) << 8); + (uint16_t) (ao_usb_packet_get(offset - 1) | ((uint16_t) byte) << 8)); else ao_usb_packet_put(offset, (uint16_t) byte); } @@ -709,7 +709,7 @@ ao_usb_ep0_fill(void) if (len > ao_usb_ep0_out_len) len = ao_usb_ep0_out_len; - ao_usb_ep0_out_len -= len; + ao_usb_ep0_out_len -= (uint8_t) len; /* Pull all of the data out of the packet */ debug_data ("Fill EP0 len %d:", len); @@ -754,7 +754,7 @@ ao_usb_ep0_in_start(uint16_t max) { /* Don't send more than asked for */ if (ao_usb_ep0_in_len > max) - ao_usb_ep0_in_len = max; + ao_usb_ep0_in_len = (uint8_t) max; ao_usb_ep0_flush(); } @@ -771,7 +771,7 @@ hex_to_ucs2(uint32_t in, uint8_t *out) for (i = 28; i >= 0; i -= 4) { uint8_t bits = (in >> i) & 0xf; - *out++ = ((bits < 10) ? '0' : ('a' - 10)) + bits; + *out++ = (uint8_t) (((bits < 10) ? '0' : ('a' - 10)) + bits); *out++ = 0; } } @@ -796,8 +796,8 @@ static void ao_usb_get_descriptor(uint16_t value, uint16_t length) { const uint8_t *descriptor; - uint8_t type = value >> 8; - uint8_t index = value; + uint8_t type = (uint8_t) (value >> 8); + uint8_t index = (uint8_t) value; descriptor = ao_usb_descriptors; while (descriptor[0] != 0) { @@ -815,7 +815,7 @@ ao_usb_get_descriptor(uint16_t value, uint16_t length) } #endif if (len > length) - len = length; + len = (uint8_t) length; ao_usb_ep0_in_set(descriptor, len); break; } @@ -855,7 +855,7 @@ ao_usb_ep0_setup(void) break; case AO_USB_REQ_SET_ADDRESS: debug ("set address %d\n", ao_usb_setup.value); - ao_usb_address = ao_usb_setup.value; + ao_usb_address = (uint8_t) ao_usb_setup.value; ao_usb_address_pending = 1; break; case AO_USB_REQ_GET_DESCRIPTOR: @@ -867,7 +867,7 @@ ao_usb_ep0_setup(void) ao_usb_ep0_in_queue_byte(ao_usb_configuration); break; case AO_USB_REQ_SET_CONFIGURATION: - ao_usb_configuration = ao_usb_setup.value; + ao_usb_configuration = (uint8_t) ao_usb_setup.value; debug ("set configuration %d\n", ao_usb_configuration); ao_usb_set_configuration(); break; @@ -970,7 +970,7 @@ static void ao_usb_wakeup(void) { ao_clock_resume(); - stm_usb.cntr &= ~(1 << STM_USB_CNTR_FSUSP); + stm_usb.cntr &= (uint16_t) ~(1 << STM_USB_CNTR_FSUSP); ao_power_resume(); } #endif @@ -980,7 +980,7 @@ stm_usb_isr(void) { uint32_t istr = stm_usb.istr; - stm_usb.istr = ~istr; + stm_usb.istr = (uint16_t) ~istr; if (istr & (1 << STM_USB_ISTR_CTR)) { uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK; uint16_t epr, epr_write; @@ -992,8 +992,8 @@ stm_usb_isr(void) epr_write = epr; epr_write &= STM_USB_EPR_PRESERVE_MASK; epr_write |= STM_USB_EPR_INVARIANT; - epr_write &= ~(1 << STM_USB_EPR_CTR_RX); - epr_write &= ~(1 << STM_USB_EPR_CTR_TX); + epr_write &= (uint16_t) ~(1 << STM_USB_EPR_CTR_RX); + epr_write &= (uint16_t) ~(1 << STM_USB_EPR_CTR_TX); stm_usb.epr[ep].r = epr_write; switch (ep) { @@ -1159,7 +1159,7 @@ ao_usb_putchar(char c) _ao_usb_in_wait(); ao_usb_in_flushed = 0; - ao_usb_tx_byte(ao_usb_in_tx_offset + AO_USB_IN_SIZE * ao_usb_in_tx_which + ao_usb_tx_count++, c); + ao_usb_tx_byte((uint16_t) (ao_usb_in_tx_offset + AO_USB_IN_SIZE * ao_usb_in_tx_which + ao_usb_tx_count++), c); /* Send the packet when full */ if (ao_usb_tx_count == AO_USB_IN_SIZE) { @@ -1247,7 +1247,7 @@ ao_usb_putchar2(char c) _ao_usb_in2_wait(); ao_usb_in2_flushed = 0; - ao_usb_tx_byte(ao_usb_in_tx2_offset + AO_USB_IN_SIZE * ao_usb_in_tx2_which + ao_usb_tx2_count++, c); + ao_usb_tx_byte((uint16_t) (ao_usb_in_tx2_offset + AO_USB_IN_SIZE * ao_usb_in_tx2_which + ao_usb_tx2_count++), c); /* Send the packet when full */ if (ao_usb_tx2_count == AO_USB_IN_SIZE) { @@ -1335,7 +1335,7 @@ ao_usb_putchar3(char c) _ao_usb_in3_wait(); ao_usb_in3_flushed = 0; - ao_usb_tx_byte(ao_usb_in_tx3_offset + AO_USB_IN_SIZE * ao_usb_in_tx3_which + ao_usb_tx3_count++, c); + ao_usb_tx_byte((uint16_t) (ao_usb_in_tx3_offset + AO_USB_IN_SIZE * ao_usb_in_tx3_which + ao_usb_tx3_count++), c); /* Send the packet when full */ if (ao_usb_tx3_count == AO_USB_IN_SIZE) { @@ -1359,7 +1359,7 @@ _ao_usb_out_recv(void) /* Switch to new buffer */ ao_usb_out_rx_which = 1 - ao_usb_out_rx_which; - ao_usb_rx_count = stm_usb_bdt[AO_USB_OUT_EPR].double_rx[ao_usb_out_rx_which].count & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK; + ao_usb_rx_count = (uint8_t) (stm_usb_bdt[AO_USB_OUT_EPR].double_rx[ao_usb_out_rx_which].count & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK); ao_usb_rx_pos = 0; /* Toggle the SW_BUF_RX bit */ @@ -1393,7 +1393,7 @@ _ao_usb_pollchar(void) } /* Pull a character out of the fifo */ - c = ao_usb_rx_byte(ao_usb_out_rx_offset + ao_usb_out_rx_which * AO_USB_OUT_SIZE + ao_usb_rx_pos++); + c = ao_usb_rx_byte((uint16_t) (ao_usb_out_rx_offset + ao_usb_out_rx_which * AO_USB_OUT_SIZE + ao_usb_rx_pos++)); _rx_dbg1("char", c); return c; } @@ -1407,7 +1407,7 @@ ao_usb_getchar(void) while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN) ao_sleep(AO_USB_OUT_SLEEP_ADDR); ao_arch_release_interrupts(); - return c; + return (char) c; } #endif @@ -1521,13 +1521,13 @@ ao_usb_disable(void) stm_usb.istr = 0; /* Disable USB pull-up */ - stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU); + stm_usb.bcdr &= (uint16_t) ~(1 << STM_USB_BCDR_DPPU); /* Switch off the device */ stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES); /* Disable the interface */ - stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN); + stm_rcc.apb1enr &= ~(1UL << STM_RCC_APB1ENR_USBEN); ao_arch_release_interrupts(); } @@ -1537,16 +1537,16 @@ ao_usb_enable(void) int t; /* Select HSI48 as USB clock source */ - stm_rcc.cfgr3 &= ~(1 << STM_RCC_CFGR3_USBSW); + stm_rcc.cfgr3 &= ~(1UL << STM_RCC_CFGR3_USBSW); /* Enable USB device */ stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN); /* Clear reset condition */ - stm_rcc.apb1rstr &= ~(1 << STM_RCC_APB1RSTR_USBRST); + stm_rcc.apb1rstr &= ~(1UL << STM_RCC_APB1RSTR_USBRST); /* Disable USB pull-up */ - stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU); + stm_usb.bcdr &= (uint16_t) ~(1 << STM_USB_BCDR_DPPU); /* Do not touch the GPIOA configuration; USB takes priority * over GPIO on pins A11 and A12, but if you select alternate diff --git a/src/stmf0/stm32f0.h b/src/stmf0/stm32f0.h index 075fd6a9..1735900c 100644 --- a/src/stmf0/stm32f0.h +++ b/src/stmf0/stm32f0.h @@ -43,7 +43,7 @@ struct stm_gpio { }; #define STM_MODER_SHIFT(pin) ((pin) << 1) -#define STM_MODER_MASK 3 +#define STM_MODER_MASK 3UL #define STM_MODER_INPUT 0 #define STM_MODER_OUTPUT 1 #define STM_MODER_ALTERNATE 2 @@ -62,7 +62,7 @@ stm_moder_get(struct stm_gpio *gpio, int pin) { } #define STM_OTYPER_SHIFT(pin) (pin) -#define STM_OTYPER_MASK 1 +#define STM_OTYPER_MASK 1UL #define STM_OTYPER_PUSH_PULL 0 #define STM_OTYPER_OPEN_DRAIN 1 @@ -79,7 +79,7 @@ stm_otyper_get(struct stm_gpio *gpio, int pin) { } #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1) -#define STM_OSPEEDR_MASK 3 +#define STM_OSPEEDR_MASK 3UL #define STM_OSPEEDR_LOW 0 /* 2MHz */ #define STM_OSPEEDR_MEDIUM 1 /* 10MHz */ #define STM_OSPEEDR_HIGH 3 /* 10-50MHz */ @@ -97,7 +97,7 @@ stm_ospeedr_get(struct stm_gpio *gpio, int pin) { } #define STM_PUPDR_SHIFT(pin) ((pin) << 1) -#define STM_PUPDR_MASK 3 +#define STM_PUPDR_MASK 3UL #define STM_PUPDR_NONE 0 #define STM_PUPDR_PULL_UP 1 #define STM_PUPDR_PULL_DOWN 2 @@ -116,7 +116,7 @@ stm_pupdr_get(struct stm_gpio *gpio, int pin) { } #define STM_AFR_SHIFT(pin) ((pin) << 2) -#define STM_AFR_MASK 0xf +#define STM_AFR_MASK 0xfUL #define STM_AFR_NONE 0 #define STM_AFR_AF0 0x0 #define STM_AFR_AF1 0x1 @@ -168,7 +168,7 @@ stm_gpio_get(struct stm_gpio *gpio, int pin) { static inline uint16_t stm_gpio_get_all(struct stm_gpio *gpio) { - return gpio->idr; + return (uint16_t) gpio->idr; } /* @@ -309,7 +309,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_MCOPRE_DIV_32 5 #define STM_RCC_CFGR_MCOPRE_DIV_64 6 #define STM_RCC_CFGR_MCOPRE_DIV_128 7 -#define STM_RCC_CFGR_MCOPRE_DIV_MASK 7 +#define STM_RCC_CFGR_MCOPRE_DIV_MASK 7UL #define STM_RCC_CFGR_MCO (24) # define STM_RCC_CFGR_MCO_DISABLE 0 @@ -321,7 +321,7 @@ extern struct stm_rcc stm_rcc; # define STM_RCC_CFGR_MCO_HSE 6 # define STM_RCC_CFGR_MCO_PLLCLK 7 # define STM_RCC_CFGR_MCO_HSI48 8 -# define STM_RCC_CFGR_MCO_MASK (0xf) +# define STM_RCC_CFGR_MCO_MASK (0xfUL) #define STM_RCC_CFGR_PLLMUL (18) #define STM_RCC_CFGR_PLLMUL_2 0 @@ -339,7 +339,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_PLLMUL_14 12 #define STM_RCC_CFGR_PLLMUL_15 13 #define STM_RCC_CFGR_PLLMUL_16 14 -#define STM_RCC_CFGR_PLLMUL_MASK 0xf +#define STM_RCC_CFGR_PLLMUL_MASK 0xfUL #define STM_RCC_CFGR_PLLXTPRE (17) @@ -357,7 +357,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_PPRE_DIV_4 5 #define STM_RCC_CFGR_PPRE_DIV_8 6 #define STM_RCC_CFGR_PPRE_DIV_16 7 -#define STM_RCC_CFGR_PPRE_MASK 7 +#define STM_RCC_CFGR_PPRE_MASK 7UL #define STM_RCC_CFGR_HPRE (4) #define STM_RCC_CFGR_HPRE_DIV_1 0 @@ -369,21 +369,21 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_HPRE_DIV_128 0xd #define STM_RCC_CFGR_HPRE_DIV_256 0xe #define STM_RCC_CFGR_HPRE_DIV_512 0xf -#define STM_RCC_CFGR_HPRE_MASK 0xf +#define STM_RCC_CFGR_HPRE_MASK 0xfUL #define STM_RCC_CFGR_SWS (2) #define STM_RCC_CFGR_SWS_HSI 0 #define STM_RCC_CFGR_SWS_HSE 1 #define STM_RCC_CFGR_SWS_PLL 2 #define STM_RCC_CFGR_SWS_HSI48 3 -#define STM_RCC_CFGR_SWS_MASK 3 +#define STM_RCC_CFGR_SWS_MASK 3UL #define STM_RCC_CFGR_SW (0) #define STM_RCC_CFGR_SW_HSI 0 #define STM_RCC_CFGR_SW_HSE 1 #define STM_RCC_CFGR_SW_PLL 2 #define STM_RCC_CFGR_SW_HSI48 3 -#define STM_RCC_CFGR_SW_MASK 3 +#define STM_RCC_CFGR_SW_MASK 3UL #define STM_RCC_APB2RSTR_DBGMCURST 22 #define STM_RCC_APB2RSTR_TIM17RST 18 @@ -707,7 +707,7 @@ stm_nvic_pending(int irq) { #define IRQ_PRIO_REG(irq) ((irq) >> 2) #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3) -#define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq)) +#define IRQ_PRIO_MASK(irq) (0xffUL << IRQ_PRIO_BIT(irq)) static inline void stm_nvic_set_priority(int irq, uint8_t prio) { @@ -836,7 +836,7 @@ extern struct stm_syscfg stm_syscfg; #define STM_SYSCFG_CFGR1_MEM_MODE_MAIN_FLASH 0 #define STM_SYSCFG_CFGR1_MEM_MODE_SYSTEM_FLASH 1 #define STM_SYSCFG_CFGR1_MEM_MODE_SRAM 3 -#define STM_SYSCFG_CFGR1_MEM_MODE_MASK 3 +#define STM_SYSCFG_CFGR1_MEM_MODE_MASK 3UL #define STM_SYSCFG_EXTICR_PA 0 #define STM_SYSCFG_EXTICR_PB 1 @@ -847,8 +847,8 @@ extern struct stm_syscfg stm_syscfg; static inline void stm_exticr_set(struct stm_gpio *gpio, int pin) { - uint8_t reg = pin >> 2; - uint8_t shift = (pin & 3) << 2; + uint8_t reg = (uint8_t) pin >> 2; + uint8_t shift = ((uint8_t) pin & 3) << 2; uint8_t val = 0; /* Enable SYSCFG */ @@ -863,7 +863,7 @@ stm_exticr_set(struct stm_gpio *gpio, int pin) { else if (gpio == &stm_gpiof) val = STM_SYSCFG_EXTICR_PF; - stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift; + stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xfUL << shift)) | val << shift; } struct stm_dma_channel { @@ -890,14 +890,14 @@ extern struct stm_dma stm_dma; #define STM_DMA_INDEX(channel) ((channel) - 1) #define STM_DMA_ISR(index) ((index) << 2) -#define STM_DMA_ISR_MASK 0xf +#define STM_DMA_ISR_MASK 0xfUL #define STM_DMA_ISR_TEIF 3 #define STM_DMA_ISR_HTIF 2 #define STM_DMA_ISR_TCIF 1 #define STM_DMA_ISR_GIF 0 #define STM_DMA_IFCR(index) ((index) << 2) -#define STM_DMA_IFCR_MASK 0xf +#define STM_DMA_IFCR_MASK 0xfUL #define STM_DMA_IFCR_CTEIF 3 #define STM_DMA_IFCR_CHTIF 2 #define STM_DMA_IFCR_CTCIF 1 @@ -910,19 +910,19 @@ extern struct stm_dma stm_dma; #define STM_DMA_CCR_PL_MEDIUM (1) #define STM_DMA_CCR_PL_HIGH (2) #define STM_DMA_CCR_PL_VERY_HIGH (3) -#define STM_DMA_CCR_PL_MASK (3) +#define STM_DMA_CCR_PL_MASK (3UL) #define STM_DMA_CCR_MSIZE (10) #define STM_DMA_CCR_MSIZE_8 (0) #define STM_DMA_CCR_MSIZE_16 (1) #define STM_DMA_CCR_MSIZE_32 (2) -#define STM_DMA_CCR_MSIZE_MASK (3) +#define STM_DMA_CCR_MSIZE_MASK (3UL) #define STM_DMA_CCR_PSIZE (8) #define STM_DMA_CCR_PSIZE_8 (0) #define STM_DMA_CCR_PSIZE_16 (1) #define STM_DMA_CCR_PSIZE_32 (2) -#define STM_DMA_CCR_PSIZE_MASK (3) +#define STM_DMA_CCR_PSIZE_MASK (3UL) #define STM_DMA_CCR_MINC (7) #define STM_DMA_CCR_PINC (6) @@ -1041,7 +1041,7 @@ extern struct stm_spi stm_spi1, stm_spi2, stm_spi3; #define STM_SPI_CR1_BR_PCLK_64 5 #define STM_SPI_CR1_BR_PCLK_128 6 #define STM_SPI_CR1_BR_PCLK_256 7 -#define STM_SPI_CR1_BR_MASK 7 +#define STM_SPI_CR1_BR_MASK 7UL #define STM_SPI_CR1_MSTR 2 #define STM_SPI_CR1_CPOL 1 @@ -1146,7 +1146,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CFGR1_EXTEN_RISING 1 #define STM_ADC_CFGR1_EXTEN_FALLING 2 #define STM_ADC_CFGR1_EXTEN_BOTH 3 -#define STM_ADC_CFGR1_EXTEN_MASK 3 +#define STM_ADC_CFGR1_EXTEN_MASK 3UL #define STM_ADC_CFGR1_EXTSEL 6 #define STM_ADC_CFGR1_ALIGN 5 @@ -1155,7 +1155,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CFGR1_RES_10 1 #define STM_ADC_CFGR1_RES_8 2 #define STM_ADC_CFGR1_RES_6 3 -#define STM_ADC_CFGR1_RES_MASK 3 +#define STM_ADC_CFGR1_RES_MASK 3UL #define STM_ADC_CFGR1_SCANDIR 2 #define STM_ADC_CFGR1_SCANDIR_UP 0 #define STM_ADC_CFGR1_SCANDIR_DOWN 1 @@ -1271,7 +1271,7 @@ extern struct stm_i2c stm_i2c1, stm_i2c2; #define STM_I2C_CR2_FREQ_8_MHZ 8 #define STM_I2C_CR2_FREQ_16_MHZ 16 #define STM_I2C_CR2_FREQ_32_MHZ 32 -#define STM_I2C_CR2_FREQ_MASK 0x3f +#define STM_I2C_CR2_FREQ_MASK 0x3fUL #define STM_I2C_SR1_SMBALERT 15 #define STM_I2C_SR1_TIMEOUT 14 @@ -1289,7 +1289,7 @@ extern struct stm_i2c stm_i2c1, stm_i2c2; #define STM_I2C_SR1_SB 0 #define STM_I2C_SR2_PEC 8 -#define STM_I2C_SR2_PEC_MASK 0xff00 +#define STM_I2C_SR2_PEC_MASK 0xff00UL #define STM_I2C_SR2_DUALF 7 #define STM_I2C_SR2_SMBHOST 6 #define STM_I2C_SR2_SMBDEFAULT 5 @@ -1301,7 +1301,7 @@ extern struct stm_i2c stm_i2c1, stm_i2c2; #define STM_I2C_CCR_FS 15 #define STM_I2C_CCR_DUTY 14 #define STM_I2C_CCR_CCR 0 -#define STM_I2C_CCR_MASK 0x7ff +#define STM_I2C_CCR_MASK 0x7ffUL struct stm_tim1 { vuint32_t cr1; @@ -1623,14 +1623,14 @@ extern struct stm_tim23 stm_tim2, stm_tim3; #define STM_TIM23_CR1_CKD_1 0 #define STM_TIM23_CR1_CKD_2 1 #define STM_TIM23_CR1_CKD_4 2 -#define STM_TIM23_CR1_CKD_MASK 3 +#define STM_TIM23_CR1_CKD_MASK 3UL #define STM_TIM23_CR1_ARPE 7 #define STM_TIM23_CR1_CMS 5 #define STM_TIM23_CR1_CMS_EDGE 0 #define STM_TIM23_CR1_CMS_CENTER_1 1 #define STM_TIM23_CR1_CMS_CENTER_2 2 #define STM_TIM23_CR1_CMS_CENTER_3 3 -#define STM_TIM23_CR1_CMS_MASK 3 +#define STM_TIM23_CR1_CMS_MASK 3UL #define STM_TIM23_CR1_DIR 4 #define STM_TIM23_CR1_DIR_UP 0 #define STM_TIM23_CR1_DIR_DOWN 1 @@ -1649,7 +1649,7 @@ extern struct stm_tim23 stm_tim2, stm_tim3; #define STM_TIM23_CR2_MMS_COMPARE_OC2REF 5 #define STM_TIM23_CR2_MMS_COMPARE_OC3REF 6 #define STM_TIM23_CR2_MMS_COMPARE_OC4REF 7 -#define STM_TIM23_CR2_MMS_MASK 7 +#define STM_TIM23_CR2_MMS_MASK 7UL #define STM_TIM23_CR2_CCDS 3 #define STM_TIM23_SMCR_ETP 15 @@ -1659,7 +1659,7 @@ extern struct stm_tim23 stm_tim2, stm_tim3; #define STM_TIM23_SMCR_ETPS_DIV_2 1 #define STM_TIM23_SMCR_ETPS_DIV_4 2 #define STM_TIM23_SMCR_ETPS_DIV_8 3 -#define STM_TIM23_SMCR_ETPS_MASK 3 +#define STM_TIM23_SMCR_ETPS_MASK 3UL #define STM_TIM23_SMCR_ETF 8 #define STM_TIM23_SMCR_ETF_NONE 0 #define STM_TIM23_SMCR_ETF_INT_N_2 1 -- 2.30.2