From 5b3a457f232e39977a437fc52256fc15c612b377 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 16 Feb 2022 21:32:07 -0800 Subject: [PATCH] altos/stm: Add casts to reduce -Wconversion warnings No bugs identified Signed-off-by: Keith Packard --- src/stm/ao_arch_funcs.h | 12 +-- src/stm/ao_beep_stm.c | 6 +- src/stm/ao_boot_pin.c | 2 +- src/stm/ao_dma_stm.c | 6 +- src/stm/ao_eeprom_stm.c | 8 +- src/stm/ao_exti_stm.c | 2 +- src/stm/ao_i2c_stm.c | 8 +- src/stm/ao_lcd_stm.c | 20 ++-- src/stm/ao_led_stm.c | 6 +- src/stm/ao_profile.h | 6 +- src/stm/ao_pwm_stm.c | 4 +- src/stm/ao_serial_stm.c | 20 ++-- src/stm/ao_timer.c | 12 +-- src/stm/ao_usb_stm.c | 42 ++++----- src/stm/stm32l.h | 202 ++++++++++++++++++++-------------------- 15 files changed, 178 insertions(+), 178 deletions(-) diff --git a/src/stm/ao_arch_funcs.h b/src/stm/ao_arch_funcs.h index d2cc1120..9f31a36f 100644 --- a/src/stm/ao_arch_funcs.h +++ b/src/stm/ao_arch_funcs.h @@ -148,7 +148,7 @@ ao_spi_recv_byte(uint8_t spi_index) stm_spi->dr = 0xff; while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE))) ; - return stm_spi->dr; + return (uint8_t) stm_spi->dr; } void @@ -200,15 +200,15 @@ ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t s #define ao_disable_port(port) do { \ if ((port) == &stm_gpioa) \ - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOAEN); \ + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOAEN); \ else if ((port) == &stm_gpiob) \ - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOBEN); \ + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOBEN); \ else if ((port) == &stm_gpioc) \ - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOCEN); \ + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOCEN); \ else if ((port) == &stm_gpiod) \ - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIODEN); \ + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIODEN); \ else if ((port) == &stm_gpioe) \ - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOEEN); \ + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOEEN); \ } while (0) diff --git a/src/stm/ao_beep_stm.c b/src/stm/ao_beep_stm.c index 12d2b0b6..4db03a5b 100644 --- a/src/stm/ao_beep_stm.c +++ b/src/stm/ao_beep_stm.c @@ -40,9 +40,9 @@ ao_beep(uint8_t beep) { if (beep == 0) { stm_beeper.cr1 = 0; - stm_rcc.apb1enr &= ~(1 << RCC_BEEPER); + stm_rcc.apb1enr &= ~(1UL << RCC_BEEPER); } else { - stm_rcc.apb1enr |= (1 << RCC_BEEPER); + stm_rcc.apb1enr |= (1UL << RCC_BEEPER); stm_beeper.cr2 = ((0 << STM_TIM234_CR2_TI1S) | (STM_TIM234_CR2_MMS_RESET << STM_TIM234_CR2_MMS) | @@ -162,5 +162,5 @@ ao_beep_init(void) stm_afr_set(BEEPER_PORT, BEEPER_PIN, BEEPER_AFR); /* Leave the timer off until requested */ - stm_rcc.apb1enr &= ~(1 << RCC_BEEPER); + stm_rcc.apb1enr &= ~(1UL << RCC_BEEPER); } diff --git a/src/stm/ao_boot_pin.c b/src/stm/ao_boot_pin.c index f21ce1b2..b289b804 100644 --- a/src/stm/ao_boot_pin.c +++ b/src/stm/ao_boot_pin.c @@ -41,6 +41,6 @@ ao_boot_check_pin(void) /* Reset the chip to turn off the port and the power interface clock */ ao_gpio_set_mode(&AO_BOOT_APPLICATION_GPIO, AO_BOOT_APPLICATION_PIN, 0); ao_disable_port(&AO_BOOT_APPLICATION_GPIO); - stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_PWREN); + stm_rcc.apb1enr &= ~(1UL << STM_RCC_APB1ENR_PWREN); return v == AO_BOOT_APPLICATION_VALUE; } diff --git a/src/stm/ao_dma_stm.c b/src/stm/ao_dma_stm.c index 962b3acc..d3162d5b 100644 --- a/src/stm/ao_dma_stm.c +++ b/src/stm/ao_dma_stm.c @@ -102,17 +102,17 @@ void ao_dma_start(uint8_t index) { ao_dma_done[index] = 0; - stm_dma.channel[index].ccr |= (1 << STM_DMA_CCR_EN); + stm_dma.channel[index].ccr |= (1UL << STM_DMA_CCR_EN); } void ao_dma_done_transfer(uint8_t index) { - stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN); + stm_dma.channel[index].ccr &= ~(1UL << STM_DMA_CCR_EN); #ifndef LEAVE_DMA_ON ao_arch_critical( if (--ao_dma_active == 0) - stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_DMA1EN); + stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_DMA1EN); ); #endif if (ao_dma_allocated[index]) diff --git a/src/stm/ao_eeprom_stm.c b/src/stm/ao_eeprom_stm.c index db4d6a49..ed2d2e41 100644 --- a/src/stm/ao_eeprom_stm.c +++ b/src/stm/ao_eeprom_stm.c @@ -103,7 +103,7 @@ ao_intflash_write8(uint16_t pos, uint8_t d) mask = 0xff << shift; w = (*addr & ~mask) | (d << shift); - ao_intflash_write32(pos & ~3, w); + ao_intflash_write32(pos & (uint16_t)~3, w); } static uint8_t @@ -119,7 +119,7 @@ ao_intflash_read(uint16_t pos) uint8_t ao_eeprom_write(ao_pos_t pos32, void *v, uint16_t len) { - uint16_t pos = pos32; + uint16_t pos = (uint16_t) pos32; uint8_t *d = v; if (pos >= ao_eeprom_total || pos + len > ao_eeprom_total) @@ -130,7 +130,7 @@ ao_eeprom_write(ao_pos_t pos32, void *v, uint16_t len) if ((pos & 3) == 0 && len >= 4) { uint32_t w; - w = d[0] | (d[1] << 8) | (d[2] << 16) | (d[3] << 24); + w = (uint32_t) d[0] | ((uint32_t) d[1] << 8) | ((uint32_t) d[2] << 16) | ((uint32_t) d[3] << 24); ao_intflash_write32(pos, w); pos += 4; d += 4; @@ -158,7 +158,7 @@ ao_eeprom_read(ao_pos_t pos, void *v, uint16_t len) if (pos >= ao_eeprom_total || pos + len > ao_eeprom_total) return 0; while (len--) - *d++ = ao_intflash_read(pos++); + *d++ = ao_intflash_read((uint16_t) (pos++)); return 1; } diff --git a/src/stm/ao_exti_stm.c b/src/stm/ao_exti_stm.c index 3a2748a9..2a05a508 100644 --- a/src/stm/ao_exti_stm.c +++ b/src/stm/ao_exti_stm.c @@ -32,7 +32,7 @@ static void ao_exti_one_isr(uint8_t pin) { } static void ao_exti_range_isr(uint8_t first, uint8_t last, uint16_t mask) { - uint16_t pending = (ao_last_exti = stm_exti.pr) & mask; + uint16_t pending = (uint16_t) (ao_last_exti = stm_exti.pr) & mask; uint8_t pin; static uint16_t last_mask; static uint8_t last_pin; diff --git a/src/stm/ao_i2c_stm.c b/src/stm/ao_i2c_stm.c index 8f549318..e634377c 100644 --- a/src/stm/ao_i2c_stm.c +++ b/src/stm/ao_i2c_stm.c @@ -132,17 +132,17 @@ ao_i2c_ev_isr(uint8_t index) if (sr1 & (1 << STM_I2C_SR1_SB)) stm_i2c->dr = ao_i2c_addr[index]; if (sr1 & (1 << STM_I2C_SR1_ADDR)) { - stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN); + stm_i2c->cr2 &= ~(1UL << STM_I2C_CR2_ITEVTEN); ao_i2c_state[index] = I2C_RUNNING; ao_wakeup(&ao_i2c_state[index]); } if (sr1 & (1 << STM_I2C_SR1_BTF)) { - stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN); + stm_i2c->cr2 &= ~(1UL << STM_I2C_CR2_ITEVTEN); ao_wakeup(&ao_i2c_state[index]); } if (sr1 & (1 << STM_I2C_SR1_RXNE)) { if (ao_i2c_recv_len[index]) { - *(ao_i2c_recv_data[index]++) = stm_i2c->dr; + *(ao_i2c_recv_data[index]++) = (uint8_t) stm_i2c->dr; if (!--ao_i2c_recv_len[index]) ao_wakeup(&ao_i2c_recv_len[index]); } @@ -161,7 +161,7 @@ ao_i2c_er_isr(uint8_t index) sr1 = stm_i2c->sr1; if (sr1 & (1 << STM_I2C_SR1_AF)) { ao_i2c_state[index] = I2C_ERROR; - stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF); + stm_i2c->sr1 = sr1 & ~(1UL << STM_I2C_SR1_AF); ao_wakeup(&ao_i2c_state[index]); } } diff --git a/src/stm/ao_lcd_stm.c b/src/stm/ao_lcd_stm.c index 1947012b..47246678 100644 --- a/src/stm/ao_lcd_stm.c +++ b/src/stm/ao_lcd_stm.c @@ -42,14 +42,14 @@ static struct stm_gpio *gpios[] = { &stm_gpioe }; -static inline int ao_lcd_stm_seg_enabled(int seg) { +static inline int ao_lcd_stm_seg_enabled(uint32_t seg) { if (seg < 32) return (AO_LCD_STM_SEG_ENABLED_0 >> seg) & 1; else return (AO_LCD_STM_SEG_ENABLED_1 >> (seg - 32)) & 1; } -static inline int ao_lcd_stm_com_enabled(int com) { +static inline int ao_lcd_stm_com_enabled(uint32_t com) { return (AO_LCD_STM_COM_ENABLED >> com) & 1; } @@ -294,7 +294,7 @@ ao_lcd_set(uint8_t digit, uint8_t segment, uint8_t value) #ifdef AO_SEGMENT_MAP #if AO_LCD_PER_DIGIT - n = digit * AO_LCD_SEGMENTS + segment; + n = (uint8_t) (digit * AO_LCD_SEGMENTS + segment); com = ao_lcd_map[n].com; seg = ao_lcd_map[n].seg; #else @@ -315,9 +315,9 @@ ao_lcd_set(uint8_t digit, uint8_t segment, uint8_t value) #endif n = (seg >> 5) & 1; if (value) - stm_lcd.ram[com * 2 + n] |= (1 << (seg & 0x1f)); + stm_lcd.ram[com * 2 + n] |= (1UL << (seg & 0x1f)); else - stm_lcd.ram[com * 2 + n] &= ~(1 << (seg & 0x1f)); + stm_lcd.ram[com * 2 + n] &= ~(1UL << (seg & 0x1f)); } #if LCD_DEBUG @@ -347,11 +347,11 @@ ao_lcd_stm_init(void) unsigned int s, c; uint32_t csr; - stm_rcc.ahbenr |= ((AO_LCD_STM_USES_GPIOA << STM_RCC_AHBENR_GPIOAEN) | - (AO_LCD_STM_USES_GPIOB << STM_RCC_AHBENR_GPIOBEN) | - (AO_LCD_STM_USES_GPIOC << STM_RCC_AHBENR_GPIOCEN) | - (AO_LCD_STM_USES_GPIOD << STM_RCC_AHBENR_GPIODEN) | - (AO_LCD_STM_USES_GPIOE << STM_RCC_AHBENR_GPIOEEN)); + stm_rcc.ahbenr |= (((uint32_t) AO_LCD_STM_USES_GPIOA << STM_RCC_AHBENR_GPIOAEN) | + ((uint32_t) AO_LCD_STM_USES_GPIOB << STM_RCC_AHBENR_GPIOBEN) | + ((uint32_t) AO_LCD_STM_USES_GPIOC << STM_RCC_AHBENR_GPIOCEN) | + ((uint32_t) AO_LCD_STM_USES_GPIOD << STM_RCC_AHBENR_GPIODEN) | + ((uint32_t) AO_LCD_STM_USES_GPIOE << STM_RCC_AHBENR_GPIOEEN)); stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_LCDEN); diff --git a/src/stm/ao_led_stm.c b/src/stm/ao_led_stm.c index 7f40eaca..aa59391b 100644 --- a/src/stm/ao_led_stm.c +++ b/src/stm/ao_led_stm.c @@ -61,8 +61,8 @@ ao_led_off(AO_LED_TYPE colors) void ao_led_set(AO_LED_TYPE colors) { - AO_LED_TYPE on = colors & LEDS_AVAILABLE; - AO_LED_TYPE off = ~colors & LEDS_AVAILABLE; + AO_LED_TYPE on = colors & (AO_LED_TYPE) LEDS_AVAILABLE; + AO_LED_TYPE off = (AO_LED_TYPE) (~colors & (AO_LED_TYPE) LEDS_AVAILABLE); ao_led_off(off); ao_led_on(on); @@ -88,7 +88,7 @@ ao_led_init(void) #ifdef LED_PORT stm_rcc.ahbenr |= (1 << LED_PORT_ENABLE); - LED_PORT->odr &= ~LEDS_AVAILABLE; + LED_PORT->odr &= ~(uint32_t) LEDS_AVAILABLE; #else #ifdef LED_PORT_0 stm_rcc.ahbenr |= (1 << LED_PORT_0_ENABLE); diff --git a/src/stm/ao_profile.h b/src/stm/ao_profile.h index 68aac001..fcbba45d 100644 --- a/src/stm/ao_profile.h +++ b/src/stm/ao_profile.h @@ -25,9 +25,9 @@ static inline uint32_t ao_profile_tick(void) { uint16_t hi, lo, second_hi; do { - hi = stm_tim2.cnt; - lo = stm_tim4.cnt; - second_hi = stm_tim2.cnt; + hi = (uint16_t) stm_tim2.cnt; + lo = (uint16_t) stm_tim4.cnt; + second_hi = (uint16_t) stm_tim2.cnt; } while (hi != second_hi); return ((uint32_t) hi << 16) | lo; } diff --git a/src/stm/ao_pwm_stm.c b/src/stm/ao_pwm_stm.c index 341f8887..9f3dde54 100644 --- a/src/stm/ao_pwm_stm.c +++ b/src/stm/ao_pwm_stm.c @@ -107,8 +107,8 @@ ao_pwm_cmd(void) uint8_t ch; uint16_t val; - ch = ao_cmd_decimal(); - val = ao_cmd_decimal(); + ch = (uint8_t) ao_cmd_decimal(); + val = (uint16_t) ao_cmd_decimal(); if (ao_cmd_status != ao_cmd_success) return; diff --git a/src/stm/ao_serial_stm.c b/src/stm/ao_serial_stm.c index 7a552e5d..42bad19e 100644 --- a/src/stm/ao_serial_stm.c +++ b/src/stm/ao_serial_stm.c @@ -64,7 +64,7 @@ _ao_usart_rx(struct ao_stm_usart *usart, int is_stdin) { if (usart->reg->sr & (1 << STM_USART_SR_RXNE)) { if (!ao_fifo_full(usart->rx_fifo)) { - ao_fifo_insert(usart->rx_fifo, usart->reg->dr); + ao_fifo_insert(usart->rx_fifo, (char) usart->reg->dr); ao_wakeup(&usart->rx_fifo); if (is_stdin) ao_wakeup(&ao_stdin_ready); @@ -78,7 +78,7 @@ _ao_usart_rx(struct ao_stm_usart *usart, int is_stdin) } #endif } else { - usart->reg->cr1 &= ~(1 << STM_USART_CR1_RXNEIE); + usart->reg->cr1 &= ~(1UL << STM_USART_CR1_RXNEIE); } } } @@ -89,11 +89,11 @@ ao_usart_isr(struct ao_stm_usart *usart, int is_stdin) _ao_usart_rx(usart, is_stdin); if (!_ao_usart_tx_start(usart)) - usart->reg->cr1 &= ~(1<< STM_USART_CR1_TXEIE); + usart->reg->cr1 &= ~(1UL << STM_USART_CR1_TXEIE); if (usart->reg->sr & (1 << STM_USART_SR_TC)) { usart->tx_running = 0; - usart->reg->cr1 &= ~(1 << STM_USART_CR1_TCIE); + usart->reg->cr1 &= ~(1UL << STM_USART_CR1_TCIE); if (usart->draining) { usart->draining = 0; ao_wakeup(&usart->tx_fifo); @@ -139,7 +139,7 @@ ao_usart_getchar(struct ao_stm_usart *usart) } static inline uint8_t -_ao_usart_sleep_for(struct ao_stm_usart *usart, uint16_t timeout) +_ao_usart_sleep_for(struct ao_stm_usart *usart, AO_TICK_TYPE timeout) { return ao_sleep_for(&usart->rx_fifo, timeout); } @@ -276,7 +276,7 @@ _ao_serial1_pollchar(void) } uint8_t -_ao_serial1_sleep_for(uint16_t timeout) +_ao_serial1_sleep_for(AO_TICK_TYPE timeout) { return _ao_usart_sleep_for(&ao_stm_usart1, timeout); } @@ -320,7 +320,7 @@ _ao_serial2_pollchar(void) } uint8_t -_ao_serial2_sleep_for(uint16_t timeout) +_ao_serial2_sleep_for(AO_TICK_TYPE timeout) { return _ao_usart_sleep_for(&ao_stm_usart2, timeout); } @@ -373,7 +373,7 @@ _ao_serial3_pollchar(void) } uint8_t -_ao_serial3_sleep_for(uint16_t timeout) +_ao_serial3_sleep_for(AO_TICK_TYPE timeout) { return _ao_usart_sleep_for(&ao_stm_usart3, timeout); } @@ -397,9 +397,9 @@ static void ao_serial_set_sw_rts_cts(struct ao_stm_usart *usart, void (*isr)(void), struct stm_gpio *port_rts, - int pin_rts, + uint8_t pin_rts, struct stm_gpio *port_cts, - int pin_cts) + uint8_t pin_cts) { /* Pull RTS low to note that there's space in the FIFO */ diff --git a/src/stm/ao_timer.c b/src/stm/ao_timer.c index eec0a35a..481b81ef 100644 --- a/src/stm/ao_timer.c +++ b/src/stm/ao_timer.c @@ -109,7 +109,7 @@ ao_timer_init(void) stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) | (1 << STM_SYSTICK_CSR_TICKINT) | (STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE)); - stm_nvic.shpr15_12 |= AO_STM_NVIC_CLOCK_PRIORITY << 24; + stm_nvic.shpr15_12 |= (uint32_t) AO_STM_NVIC_CLOCK_PRIORITY << 24; } #endif @@ -125,7 +125,7 @@ ao_clock_init(void) while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY))) ao_arch_nop(); - stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) | + stm_rcc.cfgr = (stm_rcc.cfgr & ~(uint32_t) (STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) | (STM_RCC_CFGR_SW_MSI << STM_RCC_CFGR_SW); /* wait for system to switch to MSI */ @@ -149,7 +149,7 @@ ao_clock_init(void) #if AO_HSE_BYPASS stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP); #else - stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP); + stm_rcc.cr &= ~(uint32_t) (1 << STM_RCC_CR_HSEBYP); #endif /* Enable HSE clock */ stm_rcc.cr |= (1 << STM_RCC_CR_HSEON); @@ -225,8 +225,8 @@ ao_clock_init(void) stm_rcc.cfgr = cfgr; /* Disable the PLL */ - stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON); - while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)) + stm_rcc.cr &= ~(1UL << STM_RCC_CR_PLLON); + while (stm_rcc.cr & (1UL << STM_RCC_CR_PLLRDY)) asm("nop"); /* PLLVCO to 96MHz (for USB) -> PLLMUL = 6, PLLDIV = 4 */ @@ -238,7 +238,7 @@ ao_clock_init(void) cfgr |= (AO_RCC_CFGR_PLLDIV << STM_RCC_CFGR_PLLDIV); /* PLL source */ - cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC); + cfgr &= ~(1UL << STM_RCC_CFGR_PLLSRC); cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK; stm_rcc.cfgr = cfgr; diff --git a/src/stm/ao_usb_stm.c b/src/stm/ao_usb_stm.c index 7f81e20e..8b6d95d8 100644 --- a/src/stm/ao_usb_stm.c +++ b/src/stm/ao_usb_stm.c @@ -313,7 +313,7 @@ ao_usb_init_ep(uint8_t ep, uint32_t addr, uint32_t type, uint32_t stat_rx, uint3 static void ao_usb_set_ep0(void) { - int e; + uint8_t e; ao_usb_sram_addr = 0; @@ -453,7 +453,7 @@ ao_usb_write(const uint8_t *src, uint32_t *base, uint16_t bytes) return; while (bytes >= 2) { debug_data (" %02x %02x", src[0], src[1]); - ao_usb_write_short((src[1] << 8) | src[0], base, offset); + ao_usb_write_short((uint16_t) ((uint16_t) (src[1] << 8) | (uint16_t) src[0]), base, offset); offset += 2; src += 2; bytes -= 2; @@ -477,7 +477,7 @@ ao_usb_read_byte(uint32_t *base, uint16_t offset) static inline uint16_t ao_usb_read_short(uint32_t *base, uint16_t offset) { - return base[offset>>1]; + return (uint16_t) (base[offset>>1]); } static void @@ -492,8 +492,8 @@ ao_usb_read(uint8_t *dst, uint32_t *base, uint16_t offset, uint16_t bytes) } while (bytes >= 2) { uint16_t s = ao_usb_read_short(base, offset); - dst[0] = s; - dst[1] = s >> 8; + dst[0] = (uint8_t) s; + dst[1] = (uint8_t) (s >> 8); debug_data (" %02x %02x", dst[0], dst[1]); offset += 2; dst += 2; @@ -545,7 +545,7 @@ ao_usb_ep0_fill(void) if (len > ao_usb_ep0_out_len) len = ao_usb_ep0_out_len; - ao_usb_ep0_out_len -= len; + ao_usb_ep0_out_len -= (uint8_t) len; /* Pull all of the data out of the packet */ debug_data ("Fill EP0 len %d:", len); @@ -590,7 +590,7 @@ ao_usb_ep0_in_start(uint16_t max) { /* Don't send more than asked for */ if (ao_usb_ep0_in_len > max) - ao_usb_ep0_in_len = max; + ao_usb_ep0_in_len = (uint8_t) max; ao_usb_ep0_flush(); } @@ -602,8 +602,8 @@ static void ao_usb_get_descriptor(uint16_t value, uint16_t length) { const uint8_t *descriptor; - uint8_t type = value >> 8; - uint8_t index = value; + uint8_t type = (uint8_t) (value >> 8); + uint8_t index = (uint8_t) value; descriptor = ao_usb_descriptors; while (descriptor[0] != 0) { @@ -614,7 +614,7 @@ ao_usb_get_descriptor(uint16_t value, uint16_t length) else len = descriptor[0]; if (len > length) - len = length; + len = (uint8_t) length; ao_usb_ep0_in_set(descriptor, len); break; } @@ -654,7 +654,7 @@ ao_usb_ep0_setup(void) break; case AO_USB_REQ_SET_ADDRESS: debug ("set address %d\n", ao_usb_setup.value); - ao_usb_address = ao_usb_setup.value; + ao_usb_address = (uint8_t) ao_usb_setup.value; ao_usb_address_pending = 1; break; case AO_USB_REQ_GET_DESCRIPTOR: @@ -666,7 +666,7 @@ ao_usb_ep0_setup(void) ao_usb_ep0_in_queue_byte(ao_usb_configuration); break; case AO_USB_REQ_SET_CONFIGURATION: - ao_usb_configuration = ao_usb_setup.value; + ao_usb_configuration = (uint8_t) ao_usb_setup.value; debug ("set configuration %d\n", ao_usb_configuration); ao_usb_set_configuration(); break; @@ -776,8 +776,8 @@ stm_usb_lp_isr(void) epr_write = epr; epr_write &= STM_USB_EPR_PRESERVE_MASK; epr_write |= STM_USB_EPR_INVARIANT; - epr_write &= ~(1 << STM_USB_EPR_CTR_RX); - epr_write &= ~(1 << STM_USB_EPR_CTR_TX); + epr_write &= ~(1UL << STM_USB_EPR_CTR_RX); + epr_write &= ~(1UL << STM_USB_EPR_CTR_TX); stm_usb.epr[ep] = epr_write; switch (ep) { @@ -822,7 +822,7 @@ stm_usb_lp_isr(void) if (istr & (1 << STM_USB_ISTR_RESET)) { ++reset_count; - stm_usb.istr &= ~(1 << STM_USB_ISTR_RESET); + stm_usb.istr &= ~(1UL << STM_USB_ISTR_RESET); ao_usb_ep0_receive |= AO_USB_EP0_GOT_RESET; ao_usb_ep0_handle(ao_usb_ep0_receive); } @@ -832,7 +832,7 @@ void stm_usb_fs_wkup_isr(void) { /* USB wakeup, just clear the bit for now */ - stm_usb.istr &= ~(1 << STM_USB_ISTR_WKUP); + stm_usb.istr &= ~(1UL << STM_USB_ISTR_WKUP); } /* Queue the current IN buffer for transmission */ @@ -919,7 +919,7 @@ _ao_usb_out_recv(void) _rx_dbg0("out_recv top"); ao_usb_out_avail = 0; - ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK; + ao_usb_rx_count = (uint8_t) (ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK); _rx_dbg1("out_recv count", ao_usb_rx_count); debug ("recv %d\n", ao_usb_rx_count); @@ -967,7 +967,7 @@ ao_usb_getchar(void) while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN) ao_sleep(AO_USB_OUT_SLEEP_ADDR); ao_arch_release_interrupts(); - return c; + return (char) c; } #ifndef HAS_USB_DISABLE @@ -983,13 +983,13 @@ ao_usb_disable(void) stm_usb.istr = 0; /* Disable USB pull-up */ - stm_syscfg.pmc &= ~(1 << STM_SYSCFG_PMC_USB_PU); + stm_syscfg.pmc &= ~(1UL << STM_SYSCFG_PMC_USB_PU); /* Switch off the device */ stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES); /* Disable the interface */ - stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN); + stm_rcc.apb1enr &= ~(1UL << STM_RCC_APB1ENR_USBEN); ao_arch_release_interrupts(); } #endif @@ -1003,7 +1003,7 @@ ao_usb_enable(void) stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN); /* Disable USB pull-up */ - stm_syscfg.pmc &= ~(1 << STM_SYSCFG_PMC_USB_PU); + stm_syscfg.pmc &= ~(1UL << STM_SYSCFG_PMC_USB_PU); /* Enable USB device */ stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN); diff --git a/src/stm/stm32l.h b/src/stm/stm32l.h index 310b334b..6610f11d 100644 --- a/src/stm/stm32l.h +++ b/src/stm/stm32l.h @@ -40,7 +40,7 @@ struct stm_gpio { }; #define STM_MODER_SHIFT(pin) ((pin) << 1) -#define STM_MODER_MASK 3 +#define STM_MODER_MASK 3UL #define STM_MODER_INPUT 0 #define STM_MODER_OUTPUT 1 #define STM_MODER_ALTERNATE 2 @@ -49,7 +49,7 @@ struct stm_gpio { static inline void stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) { gpio->moder = ((gpio->moder & - ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) | + (uint32_t) ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) | value << STM_MODER_SHIFT(pin)); } @@ -84,14 +84,14 @@ stm_moder_get(struct stm_gpio *gpio, int pin) { } #define STM_OTYPER_SHIFT(pin) (pin) -#define STM_OTYPER_MASK 1 +#define STM_OTYPER_MASK 1UL #define STM_OTYPER_PUSH_PULL 0 #define STM_OTYPER_OPEN_DRAIN 1 static inline void stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) { gpio->otyper = ((gpio->otyper & - ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) | + (uint32_t) ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) | value << STM_OTYPER_SHIFT(pin)); } @@ -101,7 +101,7 @@ stm_otyper_get(struct stm_gpio *gpio, int pin) { } #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1) -#define STM_OSPEEDR_MASK 3 +#define STM_OSPEEDR_MASK 3UL #define STM_OSPEEDR_400kHz 0 #define STM_OSPEEDR_2MHz 1 #define STM_OSPEEDR_10MHz 2 @@ -110,7 +110,7 @@ stm_otyper_get(struct stm_gpio *gpio, int pin) { static inline void stm_ospeedr_set(struct stm_gpio *gpio, int pin, uint32_t value) { gpio->ospeedr = ((gpio->ospeedr & - ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) | + (uint32_t) ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) | value << STM_OSPEEDR_SHIFT(pin)); } @@ -129,7 +129,7 @@ stm_ospeedr_get(struct stm_gpio *gpio, int pin) { } #define STM_PUPDR_SHIFT(pin) ((pin) << 1) -#define STM_PUPDR_MASK 3 +#define STM_PUPDR_MASK 3UL #define STM_PUPDR_NONE 0 #define STM_PUPDR_PULL_UP 1 #define STM_PUPDR_PULL_DOWN 2 @@ -138,7 +138,7 @@ stm_ospeedr_get(struct stm_gpio *gpio, int pin) { static inline void stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) { gpio->pupdr = ((gpio->pupdr & - ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) | + (uint32_t) ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) | value << STM_PUPDR_SHIFT(pin)); } @@ -157,7 +157,7 @@ stm_pupdr_get(struct stm_gpio *gpio, int pin) { } #define STM_AFR_SHIFT(pin) ((pin) << 2) -#define STM_AFR_MASK 0xf +#define STM_AFR_MASK 0xfUL #define STM_AFR_NONE 0 #define STM_AFR_AF0 0x0 #define STM_AFR_AF1 0x1 @@ -184,12 +184,12 @@ stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) { stm_moder_set(gpio, pin, STM_MODER_ALTERNATE); if (pin < 8) gpio->afrl = ((gpio->afrl & - ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) | + (uint32_t) ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) | value << STM_AFR_SHIFT(pin)); else { pin -= 8; gpio->afrh = ((gpio->afrh & - ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) | + (uint32_t) ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) | value << STM_AFR_SHIFT(pin)); } } @@ -233,7 +233,7 @@ stm_gpio_get(struct stm_gpio *gpio, int pin) { static inline uint16_t stm_gpio_get_all(struct stm_gpio *gpio) { - return gpio->idr; + return (uint16_t) gpio->idr; } /* @@ -301,7 +301,7 @@ extern struct stm_usart stm_usart3; #define STM_USART_CR2_LINEN (14) /* LIN mode enable */ #define STM_USART_CR2_STOP (12) /* STOP bits */ -#define STM_USART_CR2_STOP_MASK 3 +#define STM_USART_CR2_STOP_MASK 3UL #define STM_USART_CR2_STOP_1 0 #define STM_USART_CR2_STOP_0_5 1 #define STM_USART_CR2_STOP_2 2 @@ -314,7 +314,7 @@ extern struct stm_usart stm_usart3; #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */ #define STM_USART_CR2_LBDL (5) /* lin break detection length */ #define STM_USART_CR2_ADD (0) -#define STM_USART_CR2_ADD_MASK 0xf +#define STM_USART_CR2_ADD_MASK 0xfUL #define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */ #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */ @@ -365,7 +365,7 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_CR1_CKD_1 0 #define STM_TIM1011_CR1_CKD_2 1 #define STM_TIM1011_CR1_CKD_4 2 -#define STM_TIM1011_CR1_CKD_MASK 3 +#define STM_TIM1011_CR1_CKD_MASK 3UL #define STM_TIM1011_CR1_ARPE 7 #define STM_TIM1011_CR1_URS 2 #define STM_TIM1011_CR1_UDIS 1 @@ -378,7 +378,7 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_SMCR_ETPS_2 1 #define STM_TIM1011_SMCR_ETPS_4 2 #define STM_TIM1011_SMCR_ETPS_8 3 -#define STM_TIM1011_SMCR_ETPS_MASK 3 +#define STM_TIM1011_SMCR_ETPS_MASK 3UL #define STM_TIM1011_SMCR_ETF 8 #define STM_TIM1011_SMCR_ETF_NONE 0 #define STM_TIM1011_SMCR_ETF_CK_INT_2 1 @@ -396,7 +396,7 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_SMCR_ETF_DTS_32_5 13 #define STM_TIM1011_SMCR_ETF_DTS_32_6 14 #define STM_TIM1011_SMCR_ETF_DTS_32_8 15 -#define STM_TIM1011_SMCR_ETF_MASK 15 +#define STM_TIM1011_SMCR_ETF_MASK 15UL #define STM_TIM1011_DIER_CC1E 1 #define STM_TIM1011_DIER_UIE 0 @@ -418,7 +418,7 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7 -#define STM_TIM1011_CCMR1_OC1M_MASK 7 +#define STM_TIM1011_CCMR1_OC1M_MASK 7UL #define STM_TIM1011_CCMR1_OC1PE 3 #define STM_TIM1011_CCMR1_OC1FE 2 #define STM_TIM1011_CCMR1_CC1S 0 @@ -426,7 +426,7 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1 #define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2 #define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3 -#define STM_TIM1011_CCMR1_CC1S_MASK 3 +#define STM_TIM1011_CCMR1_CC1S_MASK 3UL #define STM_TIM1011_CCMR1_IC1F_NONE 0 #define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1 @@ -444,13 +444,13 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13 #define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14 #define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15 -#define STM_TIM1011_CCMR1_IC1F_MASK 15 +#define STM_TIM1011_CCMR1_IC1F_MASK 15UL #define STM_TIM1011_CCMR1_IC1PSC 2 #define STM_TIM1011_CCMR1_IC1PSC_1 0 #define STM_TIM1011_CCMR1_IC1PSC_2 1 #define STM_TIM1011_CCMR1_IC1PSC_4 2 #define STM_TIM1011_CCMR1_IC1PSC_8 3 -#define STM_TIM1011_CCMR1_IC1PSC_MASK 3 +#define STM_TIM1011_CCMR1_IC1PSC_MASK 3UL #define STM_TIM1011_CCMR1_CC1S 0 #define STM_TIM1011_CCER_CC1NP 3 @@ -464,7 +464,7 @@ extern struct stm_tim1011 stm_tim11; #define STM_TIM1011_TI1_RMP_LSI 1 #define STM_TIM1011_TI1_RMP_LSE 2 #define STM_TIM1011_TI1_RMP_RTC 3 -#define STM_TIM1011_TI1_RMP_MASK 3 +#define STM_TIM1011_TI1_RMP_MASK 3UL /* Flash interface */ @@ -547,7 +547,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CR_RTCPRE_HSE_DIV_4 1 #define STM_RCC_CR_RTCPRE_HSE_DIV_8 2 #define STM_RCC_CR_RTCPRE_HSE_DIV_16 3 -#define STM_RCC_CR_RTCPRE_HSE_MASK 3 +#define STM_RCC_CR_RTCPRE_HSE_MASK 3UL #define STM_RCC_CR_CSSON (28) #define STM_RCC_CR_PLLRDY (25) @@ -566,7 +566,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_MCOPRE_DIV_4 2 #define STM_RCC_CFGR_MCOPRE_DIV_8 3 #define STM_RCC_CFGR_MCOPRE_DIV_16 4 -#define STM_RCC_CFGR_MCOPRE_MASK 7 +#define STM_RCC_CFGR_MCOPRE_MASK 7UL #define STM_RCC_CFGR_MCOSEL (24) #define STM_RCC_CFGR_MCOSEL_DISABLE 0 @@ -577,13 +577,13 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_MCOSEL_PLL 5 #define STM_RCC_CFGR_MCOSEL_LSI 6 #define STM_RCC_CFGR_MCOSEL_LSE 7 -#define STM_RCC_CFGR_MCOSEL_MASK 7 +#define STM_RCC_CFGR_MCOSEL_MASK 7UL #define STM_RCC_CFGR_PLLDIV (22) #define STM_RCC_CFGR_PLLDIV_2 1 #define STM_RCC_CFGR_PLLDIV_3 2 #define STM_RCC_CFGR_PLLDIV_4 3 -#define STM_RCC_CFGR_PLLDIV_MASK 3 +#define STM_RCC_CFGR_PLLDIV_MASK 3UL #define STM_RCC_CFGR_PLLMUL (18) #define STM_RCC_CFGR_PLLMUL_3 0 @@ -595,7 +595,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_PLLMUL_24 6 #define STM_RCC_CFGR_PLLMUL_32 7 #define STM_RCC_CFGR_PLLMUL_48 8 -#define STM_RCC_CFGR_PLLMUL_MASK 0xf +#define STM_RCC_CFGR_PLLMUL_MASK 0xfUL #define STM_RCC_CFGR_PLLSRC (16) @@ -605,7 +605,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_PPRE2_DIV_4 5 #define STM_RCC_CFGR_PPRE2_DIV_8 6 #define STM_RCC_CFGR_PPRE2_DIV_16 7 -#define STM_RCC_CFGR_PPRE2_MASK 7 +#define STM_RCC_CFGR_PPRE2_MASK 7UL #define STM_RCC_CFGR_PPRE1 (8) #define STM_RCC_CFGR_PPRE1_DIV_1 0 @@ -613,7 +613,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_PPRE1_DIV_4 5 #define STM_RCC_CFGR_PPRE1_DIV_8 6 #define STM_RCC_CFGR_PPRE1_DIV_16 7 -#define STM_RCC_CFGR_PPRE1_MASK 7 +#define STM_RCC_CFGR_PPRE1_MASK 7UL #define STM_RCC_CFGR_HPRE (4) #define STM_RCC_CFGR_HPRE_DIV_1 0 @@ -625,21 +625,21 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CFGR_HPRE_DIV_128 0xd #define STM_RCC_CFGR_HPRE_DIV_256 0xe #define STM_RCC_CFGR_HPRE_DIV_512 0xf -#define STM_RCC_CFGR_HPRE_MASK 0xf +#define STM_RCC_CFGR_HPRE_MASK 0xfUL #define STM_RCC_CFGR_SWS (2) #define STM_RCC_CFGR_SWS_MSI 0 #define STM_RCC_CFGR_SWS_HSI 1 #define STM_RCC_CFGR_SWS_HSE 2 #define STM_RCC_CFGR_SWS_PLL 3 -#define STM_RCC_CFGR_SWS_MASK 3 +#define STM_RCC_CFGR_SWS_MASK 3UL #define STM_RCC_CFGR_SW (0) #define STM_RCC_CFGR_SW_MSI 0 #define STM_RCC_CFGR_SW_HSI 1 #define STM_RCC_CFGR_SW_HSE 2 #define STM_RCC_CFGR_SW_PLL 3 -#define STM_RCC_CFGR_SW_MASK 3 +#define STM_RCC_CFGR_SW_MASK 3UL #define STM_RCC_AHBENR_DMA1EN (24) #define STM_RCC_AHBENR_FLITFEN (15) @@ -692,7 +692,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CSR_RTCSEL_LSE 1 #define STM_RCC_CSR_RTCSEL_LSI 2 #define STM_RCC_CSR_RTCSEL_HSE 3 -#define STM_RCC_CSR_RTCSEL_MASK 3 +#define STM_RCC_CSR_RTCSEL_MASK 3UL #define STM_RCC_CSR_LSEBYP (10) #define STM_RCC_CSR_LSERDY (9) @@ -710,10 +710,10 @@ extern struct stm_pwr stm_pwr; #define STM_PWR_CR_LPRUN (14) #define STM_PWR_CR_VOS (11) -#define STM_PWR_CR_VOS_1_8 1 -#define STM_PWR_CR_VOS_1_5 2 -#define STM_PWR_CR_VOS_1_2 3 -#define STM_PWR_CR_VOS_MASK 3 +#define STM_PWR_CR_VOS_1_8 1UL +#define STM_PWR_CR_VOS_1_5 2UL +#define STM_PWR_CR_VOS_1_2 3UL +#define STM_PWR_CR_VOS_MASK 3UL #define STM_PWR_CR_FWU (10) #define STM_PWR_CR_ULP (9) @@ -728,7 +728,7 @@ extern struct stm_pwr stm_pwr; #define STM_PWR_CR_PLS_2_9 5 #define STM_PWR_CR_PLS_3_1 6 #define STM_PWR_CR_PLS_EXT 7 -#define STM_PWR_CR_PLS_MASK 7 +#define STM_PWR_CR_PLS_MASK 7UL #define STM_PWR_CR_PVDE (4) #define STM_PWR_CR_CSBF (3) @@ -775,7 +775,7 @@ extern struct stm_tim67 stm_tim6; #define STM_TIM67_CR2_MMS_RESET 0 #define STM_TIM67_CR2_MMS_ENABLE 1 #define STM_TIM67_CR2_MMS_UPDATE 2 -#define STM_TIM67_CR2_MMS_MASK 7 +#define STM_TIM67_CR2_MMS_MASK 7UL #define STM_TIM67_DIER_UDE (8) #define STM_TIM67_DIER_UIE (0) @@ -801,7 +801,7 @@ extern struct stm_lcd stm_lcd; #define STM_LCD_CR_BIAS_1_4 0 #define STM_LCD_CR_BIAS_1_2 1 #define STM_LCD_CR_BIAS_1_3 2 -#define STM_LCD_CR_BIAS_MASK 3 +#define STM_LCD_CR_BIAS_MASK 3UL #define STM_LCD_CR_DUTY (2) #define STM_LCD_CR_DUTY_STATIC 0 @@ -809,7 +809,7 @@ extern struct stm_lcd stm_lcd; #define STM_LCD_CR_DUTY_1_3 2 #define STM_LCD_CR_DUTY_1_4 3 #define STM_LCD_CR_DUTY_1_8 4 -#define STM_LCD_CR_DUTY_MASK 7 +#define STM_LCD_CR_DUTY_MASK 7UL #define STM_LCD_CR_VSEL (1) #define STM_LCD_CR_LCDEN (0) @@ -831,7 +831,7 @@ extern struct stm_lcd stm_lcd; #define STM_LCD_FCR_PS_8192 0xd #define STM_LCD_FCR_PS_16384 0xe #define STM_LCD_FCR_PS_32768 0xf -#define STM_LCD_FCR_PS_MASK 0xf +#define STM_LCD_FCR_PS_MASK 0xfUL #define STM_LCD_FCR_DIV (18) #define STM_LCD_FCR_DIV_16 0x0 @@ -850,14 +850,14 @@ extern struct stm_lcd stm_lcd; #define STM_LCD_FCR_DIV_29 0xd #define STM_LCD_FCR_DIV_30 0xe #define STM_LCD_FCR_DIV_31 0xf -#define STM_LCD_FCR_DIV_MASK 0xf +#define STM_LCD_FCR_DIV_MASK 0xfUL #define STM_LCD_FCR_BLINK (16) #define STM_LCD_FCR_BLINK_DISABLE 0 #define STM_LCD_FCR_BLINK_SEG0_COM0 1 #define STM_LCD_FCR_BLINK_SEG0_COMALL 2 #define STM_LCD_FCR_BLINK_SEGALL_COMALL 3 -#define STM_LCD_FCR_BLINK_MASK 3 +#define STM_LCD_FCR_BLINK_MASK 3UL #define STM_LCD_FCR_BLINKF (13) #define STM_LCD_FCR_BLINKF_8 0 @@ -868,16 +868,16 @@ extern struct stm_lcd stm_lcd; #define STM_LCD_FCR_BLINKF_256 5 #define STM_LCD_FCR_BLINKF_512 6 #define STM_LCD_FCR_BLINKF_1024 7 -#define STM_LCD_FCR_BLINKF_MASK 7 +#define STM_LCD_FCR_BLINKF_MASK 7UL #define STM_LCD_FCR_CC (10) -#define STM_LCD_FCR_CC_MASK 7 +#define STM_LCD_FCR_CC_MASK 7UL #define STM_LCD_FCR_DEAD (7) -#define STM_LCD_FCR_DEAD_MASK 7 +#define STM_LCD_FCR_DEAD_MASK 7UL #define STM_LCD_FCR_PON (4) -#define STM_LCD_FCR_PON_MASK 7 +#define STM_LCD_FCR_PON_MASK 7UL #define STM_LCD_FCR_UDDIE (3) #define STM_LCD_FCR_SOFIE (1) @@ -1006,7 +1006,7 @@ stm_nvic_set_priority(int irq, uint8_t prio) { uint32_t v; v = stm_nvic.ipr[n]; - v &= ~IRQ_PRIO_MASK(irq); + v &= (uint32_t) ~IRQ_PRIO_MASK(irq); v |= (prio) << IRQ_PRIO_BIT(irq); stm_nvic.ipr[n] = v; } @@ -1064,9 +1064,9 @@ struct stm_mpu { extern struct stm_mpu stm_mpu; #define STM_MPU_TYPER_IREGION 16 -#define STM_MPU_TYPER_IREGION_MASK 0xff +#define STM_MPU_TYPER_IREGION_MASK 0xffUL #define STM_MPU_TYPER_DREGION 8 -#define STM_MPU_TYPER_DREGION_MASK 0xff +#define STM_MPU_TYPER_DREGION_MASK 0xffUL #define STM_MPU_TYPER_SEPARATE 0 #define STM_MPU_CR_PRIVDEFENA 2 @@ -1074,14 +1074,14 @@ extern struct stm_mpu stm_mpu; #define STM_MPU_CR_ENABLE 0 #define STM_MPU_RNR_REGION 0 -#define STM_MPU_RNR_REGION_MASK 0xff +#define STM_MPU_RNR_REGION_MASK 0xffUL #define STM_MPU_RBAR_ADDR 5 -#define STM_MPU_RBAR_ADDR_MASK 0x7ffffff +#define STM_MPU_RBAR_ADDR_MASK 0x7ffffffUL #define STM_MPU_RBAR_VALID 4 #define STM_MPU_RBAR_REGION 0 -#define STM_MPU_RBAR_REGION_MASK 0xf +#define STM_MPU_RBAR_REGION_MASK 0xfUL #define STM_MPU_RASR_XN 28 #define STM_MPU_RASR_AP 24 @@ -1091,16 +1091,16 @@ extern struct stm_mpu stm_mpu; #define STM_MPU_RASR_AP_RW_RW 3 #define STM_MPU_RASR_AP_RO_NONE 5 #define STM_MPU_RASR_AP_RO_RO 6 -#define STM_MPU_RASR_AP_MASK 7 +#define STM_MPU_RASR_AP_MASK 7UL #define STM_MPU_RASR_TEX 19 -#define STM_MPU_RASR_TEX_MASK 7 +#define STM_MPU_RASR_TEX_MASK 7UL #define STM_MPU_RASR_S 18 #define STM_MPU_RASR_C 17 #define STM_MPU_RASR_B 16 #define STM_MPU_RASR_SRD 8 -#define STM_MPU_RASR_SRD_MASK 0xff +#define STM_MPU_RASR_SRD_MASK 0xffUL #define STM_MPU_RASR_SIZE 1 -#define STM_MPU_RASR_SIZE_MASK 0x1f +#define STM_MPU_RASR_SIZE_MASK 0x1fUL #define STM_MPU_RASR_ENABLE 0 #define isr_decl(name) void stm_ ## name ## _isr(void) @@ -1223,7 +1223,7 @@ extern struct stm_syscfg stm_syscfg; #define STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH 0 #define STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH 1 #define STM_SYSCFG_MEMRMP_MEM_MODE_SRAM 3 -#define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3 +#define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3UL #define STM_SYSCFG_PMC_USB_PU 0 @@ -1236,7 +1236,7 @@ extern struct stm_syscfg stm_syscfg; static inline void stm_exticr_set(struct stm_gpio *gpio, int pin) { - uint8_t reg = pin >> 2; + uint8_t reg = (uint8_t) (pin >> 2); uint8_t shift = (pin & 3) << 2; uint8_t val = 0; @@ -1254,7 +1254,7 @@ stm_exticr_set(struct stm_gpio *gpio, int pin) { else if (gpio == &stm_gpioe) val = STM_SYSCFG_EXTICR_PE; - stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift; + stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & (uint32_t) ~(0xf << shift)) | val << shift; } @@ -1282,14 +1282,14 @@ extern struct stm_dma stm_dma; #define STM_DMA_INDEX(channel) ((channel) - 1) #define STM_DMA_ISR(index) ((index) << 2) -#define STM_DMA_ISR_MASK 0xf +#define STM_DMA_ISR_MASK 0xfUL #define STM_DMA_ISR_TEIF 3 #define STM_DMA_ISR_HTIF 2 #define STM_DMA_ISR_TCIF 1 #define STM_DMA_ISR_GIF 0 #define STM_DMA_IFCR(index) ((index) << 2) -#define STM_DMA_IFCR_MASK 0xf +#define STM_DMA_IFCR_MASK 0xfUL #define STM_DMA_IFCR_CTEIF 3 #define STM_DMA_IFCR_CHTIF 2 #define STM_DMA_IFCR_CTCIF 1 @@ -1402,7 +1402,7 @@ extern struct stm_spi stm_spi1, stm_spi2, stm_spi3; #define STM_SPI_CR1_BR_PCLK_64 5 #define STM_SPI_CR1_BR_PCLK_128 6 #define STM_SPI_CR1_BR_PCLK_256 7 -#define STM_SPI_CR1_BR_MASK 7 +#define STM_SPI_CR1_BR_MASK 7UL #define STM_SPI_CR1_MSTR 2 #define STM_SPI_CR1_CPOL 1 @@ -1475,7 +1475,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR1_RES_10 1 #define STM_ADC_CR1_RES_8 2 #define STM_ADC_CR1_RES_6 3 -#define STM_ADC_CR1_RES_MASK 3 +#define STM_ADC_CR1_RES_MASK 3UL #define STM_ADC_CR1_AWDEN 23 #define STM_ADC_CR1_JAWDEN 22 #define STM_ADC_CR1_PDI 17 @@ -1489,7 +1489,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR1_DISCNUM_6 5 #define STM_ADC_CR1_DISCNUM_7 6 #define STM_ADC_CR1_DISCNUM_8 7 -#define STM_ADC_CR1_DISCNUM_MASK 7 +#define STM_ADC_CR1_DISCNUM_MASK 7UL #define STM_ADC_CR1_JDISCEN 12 #define STM_ADC_CR1_DISCEN 11 #define STM_ADC_CR1_JAUTO 10 @@ -1499,7 +1499,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR1_AWDIE 6 #define STM_ADC_CR1_EOCIE 5 #define STM_ADC_CR1_AWDCH 0 -#define STM_ADC_CR1_AWDCH_MASK 0x1f +#define STM_ADC_CR1_AWDCH_MASK 0x1fUL #define STM_ADC_CR2_SWSTART 30 #define STM_ADC_CR2_EXTEN 28 @@ -1507,7 +1507,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR2_EXTEN_RISING 1 #define STM_ADC_CR2_EXTEN_FALLING 2 #define STM_ADC_CR2_EXTEN_BOTH 3 -#define STM_ADC_CR2_EXTEN_MASK 3 +#define STM_ADC_CR2_EXTEN_MASK 3UL #define STM_ADC_CR2_EXTSEL 24 #define STM_ADC_CR2_EXTSEL_TIM9_CC2 0 #define STM_ADC_CR2_EXTSEL_TIM9_TRGO 1 @@ -1521,14 +1521,14 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR2_EXTSEL_TIM4_TRGO 9 #define STM_ADC_CR2_EXTSEL_TIM6_TRGO 10 #define STM_ADC_CR2_EXTSEL_EXTI_11 15 -#define STM_ADC_CR2_EXTSEL_MASK 15 +#define STM_ADC_CR2_EXTSEL_MASK 15UL #define STM_ADC_CR2_JWSTART 22 #define STM_ADC_CR2_JEXTEN 20 #define STM_ADC_CR2_JEXTEN_DISABLE 0 #define STM_ADC_CR2_JEXTEN_RISING 1 #define STM_ADC_CR2_JEXTEN_FALLING 2 #define STM_ADC_CR2_JEXTEN_BOTH 3 -#define STM_ADC_CR2_JEXTEN_MASK 3 +#define STM_ADC_CR2_JEXTEN_MASK 3UL #define STM_ADC_CR2_JEXTSEL 16 #define STM_ADC_CR2_JEXTSEL_TIM9_CC1 0 #define STM_ADC_CR2_JEXTSEL_TIM9_TRGO 1 @@ -1542,7 +1542,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR2_JEXTSEL_TIM10_CC1 9 #define STM_ADC_CR2_JEXTSEL_TIM7_TRGO 10 #define STM_ADC_CR2_JEXTSEL_EXTI_15 15 -#define STM_ADC_CR2_JEXTSEL_MASK 15 +#define STM_ADC_CR2_JEXTSEL_MASK 15UL #define STM_ADC_CR2_ALIGN 11 #define STM_ADC_CR2_EOCS 10 #define STM_ADC_CR2_DDS 9 @@ -1556,7 +1556,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CR2_DELS_63 5 #define STM_ADC_CR2_DELS_127 6 #define STM_ADC_CR2_DELS_255 7 -#define STM_ADC_CR2_DELS_MASK 7 +#define STM_ADC_CR2_DELS_MASK 7UL #define STM_ADC_CR2_CONT 1 #define STM_ADC_CR2_ADON 0 @@ -1565,7 +1565,7 @@ extern struct stm_adc stm_adc; #define STM_ADC_CCR_ADCPRE_HSI_1 0 #define STM_ADC_CCR_ADCPRE_HSI_2 1 #define STM_ADC_CCR_ADCPRE_HSI_4 2 -#define STM_ADC_CCR_ADCPRE_MASK 3 +#define STM_ADC_CCR_ADCPRE_MASK 3UL struct stm_temp_cal { uint16_t vref; @@ -1654,7 +1654,7 @@ extern struct stm_i2c stm_i2c1, stm_i2c2; #define STM_I2C_CR2_FREQ_16_MHZ 16 #define STM_I2C_CR2_FREQ_24_MHZ 24 #define STM_I2C_CR2_FREQ_32_MHZ 32 -#define STM_I2C_CR2_FREQ_MASK 0x3f +#define STM_I2C_CR2_FREQ_MASK 0x3fUL #define STM_I2C_SR1_SMBALERT 15 #define STM_I2C_SR1_TIMEOUT 14 @@ -1672,7 +1672,7 @@ extern struct stm_i2c stm_i2c1, stm_i2c2; #define STM_I2C_SR1_SB 0 #define STM_I2C_SR2_PEC 8 -#define STM_I2C_SR2_PEC_MASK 0xff00 +#define STM_I2C_SR2_PEC_MASK 0xff00UL #define STM_I2C_SR2_DUALF 7 #define STM_I2C_SR2_SMBHOST 6 #define STM_I2C_SR2_SMBDEFAULT 5 @@ -1684,7 +1684,7 @@ extern struct stm_i2c stm_i2c1, stm_i2c2; #define STM_I2C_CCR_FS 15 #define STM_I2C_CCR_DUTY 14 #define STM_I2C_CCR_CCR 0 -#define STM_I2C_CCR_MASK 0x7ff +#define STM_I2C_CCR_MASK 0x7ffUL struct stm_tim234 { vuint32_t cr1; @@ -1721,14 +1721,14 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CR1_CKD_1 0 #define STM_TIM234_CR1_CKD_2 1 #define STM_TIM234_CR1_CKD_4 2 -#define STM_TIM234_CR1_CKD_MASK 3 +#define STM_TIM234_CR1_CKD_MASK 3UL #define STM_TIM234_CR1_ARPE 7 #define STM_TIM234_CR1_CMS 5 #define STM_TIM234_CR1_CMS_EDGE 0 #define STM_TIM234_CR1_CMS_CENTER_1 1 #define STM_TIM234_CR1_CMS_CENTER_2 2 #define STM_TIM234_CR1_CMS_CENTER_3 3 -#define STM_TIM234_CR1_CMS_MASK 3 +#define STM_TIM234_CR1_CMS_MASK 3UL #define STM_TIM234_CR1_DIR 4 #define STM_TIM234_CR1_DIR_UP 0 #define STM_TIM234_CR1_DIR_DOWN 1 @@ -1747,7 +1747,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5 #define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6 #define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7 -#define STM_TIM234_CR2_MMS_MASK 7 +#define STM_TIM234_CR2_MMS_MASK 7UL #define STM_TIM234_CR2_CCDS 3 #define STM_TIM234_SMCR_ETP 15 @@ -1757,7 +1757,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_SMCR_ETPS_DIV_2 1 #define STM_TIM234_SMCR_ETPS_DIV_4 2 #define STM_TIM234_SMCR_ETPS_DIV_8 3 -#define STM_TIM234_SMCR_ETPS_MASK 3 +#define STM_TIM234_SMCR_ETPS_MASK 3UL #define STM_TIM234_SMCR_ETF 8 #define STM_TIM234_SMCR_ETF_NONE 0 #define STM_TIM234_SMCR_ETF_INT_N_2 1 @@ -1775,7 +1775,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_SMCR_ETF_DTS_32_N_5 13 #define STM_TIM234_SMCR_ETF_DTS_32_N_6 14 #define STM_TIM234_SMCR_ETF_DTS_32_N_8 15 -#define STM_TIM234_SMCR_ETF_MASK 15 +#define STM_TIM234_SMCR_ETF_MASK 15UL #define STM_TIM234_SMCR_MSM 7 #define STM_TIM234_SMCR_TS 4 #define STM_TIM234_SMCR_TS_ITR0 0 @@ -1786,7 +1786,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_SMCR_TS_TI1FP1 5 #define STM_TIM234_SMCR_TS_TI2FP2 6 #define STM_TIM234_SMCR_TS_ETRF 7 -#define STM_TIM234_SMCR_TS_MASK 7 +#define STM_TIM234_SMCR_TS_MASK 7UL #define STM_TIM234_SMCR_OCCS 3 #define STM_TIM234_SMCR_SMS 0 #define STM_TIM234_SMCR_SMS_DISABLE 0 @@ -1797,7 +1797,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_SMCR_SMS_GATED_MODE 5 #define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6 #define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7 -#define STM_TIM234_SMCR_SMS_MASK 7 +#define STM_TIM234_SMCR_SMS_MASK 7UL #define STM_TIM234_DIER_TDE 14 #define STM_TIM234_DIER_CC4DE 12 @@ -1841,7 +1841,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7 -#define STM_TIM234_CCMR1_OC2M_MASK 7 +#define STM_TIM234_CCMR1_OC2M_MASK 7UL #define STM_TIM234_CCMR1_OC2PE 11 #define STM_TIM234_CCMR1_OC2FE 10 #define STM_TIM234_CCMR1_CC2S 8 @@ -1849,7 +1849,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1 #define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2 #define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3 -#define STM_TIM234_CCMR1_CC2S_MASK 3 +#define STM_TIM234_CCMR1_CC2S_MASK 3UL #define STM_TIM234_CCMR1_OC1CE 7 #define STM_TIM234_CCMR1_OC1M 4 @@ -1861,7 +1861,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7 -#define STM_TIM234_CCMR1_OC1M_MASK 7 +#define STM_TIM234_CCMR1_OC1M_MASK 7UL #define STM_TIM234_CCMR1_OC1PE 3 #define STM_TIM234_CCMR1_OC1FE 2 #define STM_TIM234_CCMR1_CC1S 0 @@ -1869,7 +1869,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1 #define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2 #define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3 -#define STM_TIM234_CCMR1_CC1S_MASK 3 +#define STM_TIM234_CCMR1_CC1S_MASK 3UL #define STM_TIM234_CCMR1_IC2F 12 #define STM_TIM234_CCMR1_IC2F_NONE 0 @@ -1926,7 +1926,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7 -#define STM_TIM234_CCMR2_OC4M_MASK 7 +#define STM_TIM234_CCMR2_OC4M_MASK 7UL #define STM_TIM234_CCMR2_OC4PE 11 #define STM_TIM234_CCMR2_OC4FE 10 #define STM_TIM234_CCMR2_CC4S 8 @@ -1934,7 +1934,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1 #define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2 #define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3 -#define STM_TIM234_CCMR2_CC4S_MASK 3 +#define STM_TIM234_CCMR2_CC4S_MASK 3UL #define STM_TIM234_CCMR2_OC3CE 7 #define STM_TIM234_CCMR2_OC3M 4 @@ -1946,7 +1946,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7 -#define STM_TIM234_CCMR2_OC3M_MASK 7 +#define STM_TIM234_CCMR2_OC3M_MASK 7UL #define STM_TIM234_CCMR2_OC3PE 3 #define STM_TIM234_CCMR2_OC3FE 2 #define STM_TIM234_CCMR2_CC3S 0 @@ -1954,7 +1954,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; #define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1 #define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2 #define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3 -#define STM_TIM234_CCMR2_CC3S_MASK 3 +#define STM_TIM234_CCMR2_CC3S_MASK 3UL #define STM_TIM234_CCER_CC4NP 15 #define STM_TIM234_CCER_CC4P 13 @@ -1996,7 +1996,7 @@ struct stm_usb { #define STM_USB_EPR_STAT_RX_STALL 1 #define STM_USB_EPR_STAT_RX_NAK 2 #define STM_USB_EPR_STAT_RX_VALID 3 -#define STM_USB_EPR_STAT_RX_MASK 3 +#define STM_USB_EPR_STAT_RX_MASK 3UL #define STM_USB_EPR_STAT_RX_WRITE_INVARIANT 0 #define STM_USB_EPR_SETUP 11 #define STM_USB_EPR_EP_TYPE 9 @@ -2004,7 +2004,7 @@ struct stm_usb { #define STM_USB_EPR_EP_TYPE_CONTROL 1 #define STM_USB_EPR_EP_TYPE_ISO 2 #define STM_USB_EPR_EP_TYPE_INTERRUPT 3 -#define STM_USB_EPR_EP_TYPE_MASK 3 +#define STM_USB_EPR_EP_TYPE_MASK 3UL #define STM_USB_EPR_EP_KIND 8 #define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */ #define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */ @@ -2018,9 +2018,9 @@ struct stm_usb { #define STM_USB_EPR_STAT_TX_NAK 2 #define STM_USB_EPR_STAT_TX_VALID 3 #define STM_USB_EPR_STAT_TX_WRITE_INVARIANT 0 -#define STM_USB_EPR_STAT_TX_MASK 3 +#define STM_USB_EPR_STAT_TX_MASK 3UL #define STM_USB_EPR_EA 0 -#define STM_USB_EPR_EA_MASK 0xf +#define STM_USB_EPR_EA_MASK 0xfUL #define STM_USB_CNTR_CTRM 15 #define STM_USB_CNTR_PMAOVRM 14 @@ -2046,19 +2046,19 @@ struct stm_usb { #define STM_USB_ISTR_ESOF 8 #define STM_USB_ISTR_DIR 4 #define STM_USB_ISTR_EP_ID 0 -#define STM_USB_ISTR_EP_ID_MASK 0xf +#define STM_USB_ISTR_EP_ID_MASK 0xfUL #define STM_USB_FNR_RXDP 15 #define STM_USB_FNR_RXDM 14 #define STM_USB_FNR_LCK 13 #define STM_USB_FNR_LSOF 11 -#define STM_USB_FNR_LSOF_MASK 0x3 +#define STM_USB_FNR_LSOF_MASK 0x3UL #define STM_USB_FNR_FN 0 -#define STM_USB_FNR_FN_MASK 0x7ff +#define STM_USB_FNR_FN_MASK 0x7ffUL #define STM_USB_DADDR_EF 7 #define STM_USB_DADDR_ADD 0 -#define STM_USB_DADDR_ADD_MASK 0x7f +#define STM_USB_DADDR_ADD_MASK 0x7fUL extern struct stm_usb stm_usb; @@ -2081,9 +2081,9 @@ union stm_usb_bdt { #define STM_USB_BDT_COUNT_RX_BL_SIZE 15 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK 10 -#define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1f +#define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1fUL #define STM_USB_BDT_COUNT_RX_COUNT_RX 0 -#define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x1ff +#define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x1ffUL #define STM_USB_BDT_SIZE 8 -- 2.30.2