From f95c781bc16d332ea5442590521074396d6981ae Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Sat, 2 Apr 2016 19:43:32 -0700 Subject: [PATCH] altos/stmf0: Support HPE clock source Allows the use of crystals instead of requiring USB. Signed-off-by: Keith Packard --- src/stmf0/ao_timer.c | 39 +++- src/stmf0/stm32f0.h | 423 +++++++++++++++++++++++-------------------- 2 files changed, 258 insertions(+), 204 deletions(-) diff --git a/src/stmf0/ao_timer.c b/src/stmf0/ao_timer.c index d3542a57..e5bf04a3 100644 --- a/src/stmf0/ao_timer.c +++ b/src/stmf0/ao_timer.c @@ -50,12 +50,14 @@ void stm_systick_isr(void) #if AO_DATA_ALL if (++ao_data_count == ao_data_interval) { ao_data_count = 0; +#if HAS_ADC #if HAS_FAKE_FLIGHT if (ao_fake_flight_active) ao_fake_flight_poll(); else #endif ao_adc_poll(); +#endif #if (AO_DATA_ALL & ~(AO_DATA_ADC)) ao_wakeup((void *) &ao_data_count); #endif @@ -92,6 +94,7 @@ ao_timer_init(void) #endif +#if AO_HSI48 static void ao_clock_enable_crs(void) { @@ -128,6 +131,7 @@ ao_clock_enable_crs(void) (0 << STM_CRS_CR_SYNCWARNIE) | (0 << STM_CRS_CR_SYNCOKIE)); } +#endif static void ao_clock_hsi(void) @@ -155,10 +159,11 @@ static void ao_clock_normal_start(void) { #if AO_HSE -#define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_HSE -#define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_HSE + uint32_t cfgr; +#define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_PLL +#define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_PLL #define STM_PLLSRC AO_HSE -#define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK 1 +#define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK STM_RCC_CFGR_PLLSRC_HSE #if AO_HSE_BYPASS stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP); @@ -171,7 +176,29 @@ ao_clock_normal_start(void) asm("nop"); #ifdef STM_PLLSRC -#error No code for PLL initialization yet + /* Disable the PLL */ + stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON); + while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)) + asm("nop"); + + /* PLLVCO to 48MHz (for USB) -> PLLMUL = 3 */ + cfgr = stm_rcc.cfgr; + cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL); + cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL); + + /* PLL source */ + cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC); + cfgr |= (STM_RCC_CFGR_PLLSRC_TARGET_CLOCK << STM_RCC_CFGR_PLLSRC); + stm_rcc.cfgr = cfgr; + + /* Disable pre divider */ + stm_rcc.cfgr2 = (STM_RCC_CFGR2_PREDIV_1 << STM_RCC_CFGR2_PREDIV); + + /* Enable the PLL and wait for it */ + stm_rcc.cr |= (1 << STM_RCC_CR_PLLON); + while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))) + asm("nop"); + #endif #endif @@ -223,6 +250,10 @@ ao_clock_normal_switch(void) /* Turn off the HSI clock */ stm_rcc.cr &= ~(1 << STM_RCC_CR_HSION); #endif +#ifdef STM_PLLSRC + /* USB PLL source */ + stm_rcc.cfgr3 |= (1 << STM_RCC_CFGR3_USBSW); +#endif } void diff --git a/src/stmf0/stm32f0.h b/src/stmf0/stm32f0.h index 14be5fbb..30b45b15 100644 --- a/src/stmf0/stm32f0.h +++ b/src/stmf0/stm32f0.h @@ -475,6 +475,24 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CR2_HSI14RDY 1 #define STM_RCC_CR2_HSI14ON 0 +#define STM_RCC_CFGR2_PREDIV 0 +#define STM_RCC_CFGR2_PREDIV_1 0x0 +#define STM_RCC_CFGR2_PREDIV_2 0x1 +#define STM_RCC_CFGR2_PREDIV_3 0x2 +#define STM_RCC_CFGR2_PREDIV_4 0x3 +#define STM_RCC_CFGR2_PREDIV_5 0x4 +#define STM_RCC_CFGR2_PREDIV_6 0x5 +#define STM_RCC_CFGR2_PREDIV_7 0x6 +#define STM_RCC_CFGR2_PREDIV_8 0x7 +#define STM_RCC_CFGR2_PREDIV_9 0x8 +#define STM_RCC_CFGR2_PREDIV_10 0x9 +#define STM_RCC_CFGR2_PREDIV_11 0xa +#define STM_RCC_CFGR2_PREDIV_12 0xb +#define STM_RCC_CFGR2_PREDIV_13 0xc +#define STM_RCC_CFGR2_PREDIV_14 0xd +#define STM_RCC_CFGR2_PREDIV_15 0xe +#define STM_RCC_CFGR2_PREDIV_16 0xf + #define STM_RCC_CFGR3_USART3SW 18 #define STM_RCC_CFGR3_USART2SW 16 #define STM_RCC_CFGR3_ADCSW 8 @@ -858,7 +876,13 @@ extern struct stm_syscfg stm_syscfg; #define STM_SYSCFG_CFGR1_MEM_MODE_SRAM 3 #define STM_SYSCFG_CFGR1_MEM_MODE_MASK 3 -#if 0 +#define STM_SYSCFG_EXTICR_PA 0 +#define STM_SYSCFG_EXTICR_PB 1 +#define STM_SYSCFG_EXTICR_PC 2 +#define STM_SYSCFG_EXTICR_PD 3 +#define STM_SYSCFG_EXTICR_PE 4 +#define STM_SYSCFG_EXTICR_PF 5 + static inline void stm_exticr_set(struct stm_gpio *gpio, int pin) { uint8_t reg = pin >> 2; @@ -879,8 +903,6 @@ stm_exticr_set(struct stm_gpio *gpio, int pin) { stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift; } -#endif - struct stm_dma_channel { vuint32_t ccr; @@ -1319,7 +1341,7 @@ extern struct stm_i2c stm_i2c1, stm_i2c2; #define STM_I2C_CCR_CCR 0 #define STM_I2C_CCR_MASK 0x7ff -struct stm_tim234 { +struct stm_tim23 { vuint32_t cr1; vuint32_t cr2; vuint32_t smcr; @@ -1344,204 +1366,205 @@ struct stm_tim234 { uint32_t reserved_44; vuint32_t dcr; vuint32_t dmar; - - uint32_t reserved_50; }; -extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; - -#define STM_TIM234_CR1_CKD 8 -#define STM_TIM234_CR1_CKD_1 0 -#define STM_TIM234_CR1_CKD_2 1 -#define STM_TIM234_CR1_CKD_4 2 -#define STM_TIM234_CR1_CKD_MASK 3 -#define STM_TIM234_CR1_ARPE 7 -#define STM_TIM234_CR1_CMS 5 -#define STM_TIM234_CR1_CMS_EDGE 0 -#define STM_TIM234_CR1_CMS_CENTER_1 1 -#define STM_TIM234_CR1_CMS_CENTER_2 2 -#define STM_TIM234_CR1_CMS_CENTER_3 3 -#define STM_TIM234_CR1_CMS_MASK 3 -#define STM_TIM234_CR1_DIR 4 -#define STM_TIM234_CR1_DIR_UP 0 -#define STM_TIM234_CR1_DIR_DOWN 1 -#define STM_TIM234_CR1_OPM 3 -#define STM_TIM234_CR1_URS 2 -#define STM_TIM234_CR1_UDIS 1 -#define STM_TIM234_CR1_CEN 0 - -#define STM_TIM234_CR2_TI1S 7 -#define STM_TIM234_CR2_MMS 4 -#define STM_TIM234_CR2_MMS_RESET 0 -#define STM_TIM234_CR2_MMS_ENABLE 1 -#define STM_TIM234_CR2_MMS_UPDATE 2 -#define STM_TIM234_CR2_MMS_COMPARE_PULSE 3 -#define STM_TIM234_CR2_MMS_COMPARE_OC1REF 4 -#define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5 -#define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6 -#define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7 -#define STM_TIM234_CR2_MMS_MASK 7 -#define STM_TIM234_CR2_CCDS 3 - -#define STM_TIM234_SMCR_ETP 15 -#define STM_TIM234_SMCR_ECE 14 -#define STM_TIM234_SMCR_ETPS 12 -#define STM_TIM234_SMCR_ETPS_OFF 0 -#define STM_TIM234_SMCR_ETPS_DIV_2 1 -#define STM_TIM234_SMCR_ETPS_DIV_4 2 -#define STM_TIM234_SMCR_ETPS_DIV_8 3 -#define STM_TIM234_SMCR_ETPS_MASK 3 -#define STM_TIM234_SMCR_ETF 8 -#define STM_TIM234_SMCR_ETF_NONE 0 -#define STM_TIM234_SMCR_ETF_INT_N_2 1 -#define STM_TIM234_SMCR_ETF_INT_N_4 2 -#define STM_TIM234_SMCR_ETF_INT_N_8 3 -#define STM_TIM234_SMCR_ETF_DTS_2_N_6 4 -#define STM_TIM234_SMCR_ETF_DTS_2_N_8 5 -#define STM_TIM234_SMCR_ETF_DTS_4_N_6 6 -#define STM_TIM234_SMCR_ETF_DTS_4_N_8 7 -#define STM_TIM234_SMCR_ETF_DTS_8_N_6 8 -#define STM_TIM234_SMCR_ETF_DTS_8_N_8 9 -#define STM_TIM234_SMCR_ETF_DTS_16_N_5 10 -#define STM_TIM234_SMCR_ETF_DTS_16_N_6 11 -#define STM_TIM234_SMCR_ETF_DTS_16_N_8 12 -#define STM_TIM234_SMCR_ETF_DTS_32_N_5 13 -#define STM_TIM234_SMCR_ETF_DTS_32_N_6 14 -#define STM_TIM234_SMCR_ETF_DTS_32_N_8 15 -#define STM_TIM234_SMCR_ETF_MASK 15 -#define STM_TIM234_SMCR_MSM 7 -#define STM_TIM234_SMCR_TS 4 -#define STM_TIM234_SMCR_TS_ITR0 0 -#define STM_TIM234_SMCR_TS_ITR1 1 -#define STM_TIM234_SMCR_TS_ITR2 2 -#define STM_TIM234_SMCR_TS_ITR3 3 -#define STM_TIM234_SMCR_TS_TI1F_ED 4 -#define STM_TIM234_SMCR_TS_TI1FP1 5 -#define STM_TIM234_SMCR_TS_TI2FP2 6 -#define STM_TIM234_SMCR_TS_ETRF 7 -#define STM_TIM234_SMCR_TS_MASK 7 -#define STM_TIM234_SMCR_OCCS 3 -#define STM_TIM234_SMCR_SMS 0 -#define STM_TIM234_SMCR_SMS_DISABLE 0 -#define STM_TIM234_SMCR_SMS_ENCODER_MODE_1 1 -#define STM_TIM234_SMCR_SMS_ENCODER_MODE_2 2 -#define STM_TIM234_SMCR_SMS_ENCODER_MODE_3 3 -#define STM_TIM234_SMCR_SMS_RESET_MODE 4 -#define STM_TIM234_SMCR_SMS_GATED_MODE 5 -#define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6 -#define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7 -#define STM_TIM234_SMCR_SMS_MASK 7 - -#define STM_TIM234_SR_CC4OF 12 -#define STM_TIM234_SR_CC3OF 11 -#define STM_TIM234_SR_CC2OF 10 -#define STM_TIM234_SR_CC1OF 9 -#define STM_TIM234_SR_TIF 6 -#define STM_TIM234_SR_CC4IF 4 -#define STM_TIM234_SR_CC3IF 3 -#define STM_TIM234_SR_CC2IF 2 -#define STM_TIM234_SR_CC1IF 1 -#define STM_TIM234_SR_UIF 0 - -#define STM_TIM234_EGR_TG 6 -#define STM_TIM234_EGR_CC4G 4 -#define STM_TIM234_EGR_CC3G 3 -#define STM_TIM234_EGR_CC2G 2 -#define STM_TIM234_EGR_CC1G 1 -#define STM_TIM234_EGR_UG 0 - -#define STM_TIM234_CCMR1_OC2CE 15 -#define STM_TIM234_CCMR1_OC2M 12 -#define STM_TIM234_CCMR1_OC2M_FROZEN 0 -#define STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH 1 -#define STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH 2 -#define STM_TIM234_CCMR1_OC2M_TOGGLE 3 -#define STM_TIM234_CCMR1_OC2M_FORCE_LOW 4 -#define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5 -#define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6 -#define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7 -#define STM_TIM234_CCMR1_OC2M_MASK 7 -#define STM_TIM234_CCMR1_OC2PE 11 -#define STM_TIM234_CCMR1_OC2FE 10 -#define STM_TIM234_CCMR1_CC2S 8 -#define STM_TIM234_CCMR1_CC2S_OUTPUT 0 -#define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1 -#define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2 -#define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3 -#define STM_TIM234_CCMR1_CC2S_MASK 3 - -#define STM_TIM234_CCMR1_OC1CE 7 -#define STM_TIM234_CCMR1_OC1M 4 -#define STM_TIM234_CCMR1_OC1M_FROZEN 0 -#define STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH 1 -#define STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH 2 -#define STM_TIM234_CCMR1_OC1M_TOGGLE 3 -#define STM_TIM234_CCMR1_OC1M_FORCE_LOW 4 -#define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5 -#define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6 -#define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7 -#define STM_TIM234_CCMR1_OC1M_MASK 7 -#define STM_TIM234_CCMR1_OC1PE 11 -#define STM_TIM234_CCMR1_OC1FE 2 -#define STM_TIM234_CCMR1_CC1S 0 -#define STM_TIM234_CCMR1_CC1S_OUTPUT 0 -#define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1 -#define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2 -#define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3 -#define STM_TIM234_CCMR1_CC1S_MASK 3 - -#define STM_TIM234_CCMR2_OC4CE 15 -#define STM_TIM234_CCMR2_OC4M 12 -#define STM_TIM234_CCMR2_OC4M_FROZEN 0 -#define STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH 1 -#define STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH 2 -#define STM_TIM234_CCMR2_OC4M_TOGGLE 3 -#define STM_TIM234_CCMR2_OC4M_FORCE_LOW 4 -#define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5 -#define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6 -#define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7 -#define STM_TIM234_CCMR2_OC4M_MASK 7 -#define STM_TIM234_CCMR2_OC4PE 11 -#define STM_TIM234_CCMR2_OC4FE 10 -#define STM_TIM234_CCMR2_CC4S 8 -#define STM_TIM234_CCMR2_CC4S_OUTPUT 0 -#define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1 -#define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2 -#define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3 -#define STM_TIM234_CCMR2_CC4S_MASK 3 - -#define STM_TIM234_CCMR2_OC3CE 7 -#define STM_TIM234_CCMR2_OC3M 4 -#define STM_TIM234_CCMR2_OC3M_FROZEN 0 -#define STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH 1 -#define STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH 2 -#define STM_TIM234_CCMR2_OC3M_TOGGLE 3 -#define STM_TIM234_CCMR2_OC3M_FORCE_LOW 4 -#define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5 -#define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6 -#define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7 -#define STM_TIM234_CCMR2_OC3M_MASK 7 -#define STM_TIM234_CCMR2_OC3PE 11 -#define STM_TIM234_CCMR2_OC3FE 2 -#define STM_TIM234_CCMR2_CC3S 0 -#define STM_TIM234_CCMR2_CC3S_OUTPUT 0 -#define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1 -#define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2 -#define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3 -#define STM_TIM234_CCMR2_CC3S_MASK 3 - -#define STM_TIM234_CCER_CC4NP 15 -#define STM_TIM234_CCER_CC4P 13 -#define STM_TIM234_CCER_CC4E 12 -#define STM_TIM234_CCER_CC3NP 11 -#define STM_TIM234_CCER_CC3P 9 -#define STM_TIM234_CCER_CC3E 8 -#define STM_TIM234_CCER_CC2NP 7 -#define STM_TIM234_CCER_CC2P 5 -#define STM_TIM234_CCER_CC2E 4 -#define STM_TIM234_CCER_CC1NP 3 -#define STM_TIM234_CCER_CC1P 1 -#define STM_TIM234_CCER_CC1E 0 +extern struct stm_tim23 stm_tim2, stm_tim3; + +#define stm_tim3 (*(struct stm_tim23 *) 0x40000400) +#define stm_tim2 (*(struct stm_tim23 *) 0x40000000) + +#define STM_TIM23_CR1_CKD 8 +#define STM_TIM23_CR1_CKD_1 0 +#define STM_TIM23_CR1_CKD_2 1 +#define STM_TIM23_CR1_CKD_4 2 +#define STM_TIM23_CR1_CKD_MASK 3 +#define STM_TIM23_CR1_ARPE 7 +#define STM_TIM23_CR1_CMS 5 +#define STM_TIM23_CR1_CMS_EDGE 0 +#define STM_TIM23_CR1_CMS_CENTER_1 1 +#define STM_TIM23_CR1_CMS_CENTER_2 2 +#define STM_TIM23_CR1_CMS_CENTER_3 3 +#define STM_TIM23_CR1_CMS_MASK 3 +#define STM_TIM23_CR1_DIR 4 +#define STM_TIM23_CR1_DIR_UP 0 +#define STM_TIM23_CR1_DIR_DOWN 1 +#define STM_TIM23_CR1_OPM 3 +#define STM_TIM23_CR1_URS 2 +#define STM_TIM23_CR1_UDIS 1 +#define STM_TIM23_CR1_CEN 0 + +#define STM_TIM23_CR2_TI1S 7 +#define STM_TIM23_CR2_MMS 4 +#define STM_TIM23_CR2_MMS_RESET 0 +#define STM_TIM23_CR2_MMS_ENABLE 1 +#define STM_TIM23_CR2_MMS_UPDATE 2 +#define STM_TIM23_CR2_MMS_COMPARE_PULSE 3 +#define STM_TIM23_CR2_MMS_COMPARE_OC1REF 4 +#define STM_TIM23_CR2_MMS_COMPARE_OC2REF 5 +#define STM_TIM23_CR2_MMS_COMPARE_OC3REF 6 +#define STM_TIM23_CR2_MMS_COMPARE_OC4REF 7 +#define STM_TIM23_CR2_MMS_MASK 7 +#define STM_TIM23_CR2_CCDS 3 + +#define STM_TIM23_SMCR_ETP 15 +#define STM_TIM23_SMCR_ECE 14 +#define STM_TIM23_SMCR_ETPS 12 +#define STM_TIM23_SMCR_ETPS_OFF 0 +#define STM_TIM23_SMCR_ETPS_DIV_2 1 +#define STM_TIM23_SMCR_ETPS_DIV_4 2 +#define STM_TIM23_SMCR_ETPS_DIV_8 3 +#define STM_TIM23_SMCR_ETPS_MASK 3 +#define STM_TIM23_SMCR_ETF 8 +#define STM_TIM23_SMCR_ETF_NONE 0 +#define STM_TIM23_SMCR_ETF_INT_N_2 1 +#define STM_TIM23_SMCR_ETF_INT_N_4 2 +#define STM_TIM23_SMCR_ETF_INT_N_8 3 +#define STM_TIM23_SMCR_ETF_DTS_2_N_6 4 +#define STM_TIM23_SMCR_ETF_DTS_2_N_8 5 +#define STM_TIM23_SMCR_ETF_DTS_4_N_6 6 +#define STM_TIM23_SMCR_ETF_DTS_4_N_8 7 +#define STM_TIM23_SMCR_ETF_DTS_8_N_6 8 +#define STM_TIM23_SMCR_ETF_DTS_8_N_8 9 +#define STM_TIM23_SMCR_ETF_DTS_16_N_5 10 +#define STM_TIM23_SMCR_ETF_DTS_16_N_6 11 +#define STM_TIM23_SMCR_ETF_DTS_16_N_8 12 +#define STM_TIM23_SMCR_ETF_DTS_32_N_5 13 +#define STM_TIM23_SMCR_ETF_DTS_32_N_6 14 +#define STM_TIM23_SMCR_ETF_DTS_32_N_8 15 +#define STM_TIM23_SMCR_ETF_MASK 15 +#define STM_TIM23_SMCR_MSM 7 +#define STM_TIM23_SMCR_TS 4 +#define STM_TIM23_SMCR_TS_ITR0 0 +#define STM_TIM23_SMCR_TS_ITR1 1 +#define STM_TIM23_SMCR_TS_ITR2 2 +#define STM_TIM23_SMCR_TS_ITR3 3 +#define STM_TIM23_SMCR_TS_TI1F_ED 4 +#define STM_TIM23_SMCR_TS_TI1FP1 5 +#define STM_TIM23_SMCR_TS_TI2FP2 6 +#define STM_TIM23_SMCR_TS_ETRF 7 +#define STM_TIM23_SMCR_TS_MASK 7 +#define STM_TIM23_SMCR_OCCS 3 +#define STM_TIM23_SMCR_SMS 0 +#define STM_TIM23_SMCR_SMS_DISABLE 0 +#define STM_TIM23_SMCR_SMS_ENCODER_MODE_1 1 +#define STM_TIM23_SMCR_SMS_ENCODER_MODE_2 2 +#define STM_TIM23_SMCR_SMS_ENCODER_MODE_3 3 +#define STM_TIM23_SMCR_SMS_RESET_MODE 4 +#define STM_TIM23_SMCR_SMS_GATED_MODE 5 +#define STM_TIM23_SMCR_SMS_TRIGGER_MODE 6 +#define STM_TIM23_SMCR_SMS_EXTERNAL_CLOCK 7 +#define STM_TIM23_SMCR_SMS_MASK 7 + +#define STM_TIM23_SR_CC4OF 12 +#define STM_TIM23_SR_CC3OF 11 +#define STM_TIM23_SR_CC2OF 10 +#define STM_TIM23_SR_CC1OF 9 +#define STM_TIM23_SR_TIF 6 +#define STM_TIM23_SR_CC4IF 4 +#define STM_TIM23_SR_CC3IF 3 +#define STM_TIM23_SR_CC2IF 2 +#define STM_TIM23_SR_CC1IF 1 +#define STM_TIM23_SR_UIF 0 + +#define STM_TIM23_EGR_TG 6 +#define STM_TIM23_EGR_CC4G 4 +#define STM_TIM23_EGR_CC3G 3 +#define STM_TIM23_EGR_CC2G 2 +#define STM_TIM23_EGR_CC1G 1 +#define STM_TIM23_EGR_UG 0 + +#define STM_TIM23_CCMR1_OC2CE 15 +#define STM_TIM23_CCMR1_OC2M 12 +#define STM_TIM23_CCMR1_OC2M_FROZEN 0 +#define STM_TIM23_CCMR1_OC2M_SET_HIGH_ON_MATCH 1 +#define STM_TIM23_CCMR1_OC2M_SET_LOW_ON_MATCH 2 +#define STM_TIM23_CCMR1_OC2M_TOGGLE 3 +#define STM_TIM23_CCMR1_OC2M_FORCE_LOW 4 +#define STM_TIM23_CCMR1_OC2M_FORCE_HIGH 5 +#define STM_TIM23_CCMR1_OC2M_PWM_MODE_1 6 +#define STM_TIM23_CCMR1_OC2M_PWM_MODE_2 7 +#define STM_TIM23_CCMR1_OC2M_MASK 7 +#define STM_TIM23_CCMR1_OC2PE 11 +#define STM_TIM23_CCMR1_OC2FE 10 +#define STM_TIM23_CCMR1_CC2S 8 +#define STM_TIM23_CCMR1_CC2S_OUTPUT 0 +#define STM_TIM23_CCMR1_CC2S_INPUT_TI2 1 +#define STM_TIM23_CCMR1_CC2S_INPUT_TI1 2 +#define STM_TIM23_CCMR1_CC2S_INPUT_TRC 3 +#define STM_TIM23_CCMR1_CC2S_MASK 3 + +#define STM_TIM23_CCMR1_OC1CE 7 +#define STM_TIM23_CCMR1_OC1M 4 +#define STM_TIM23_CCMR1_OC1M_FROZEN 0 +#define STM_TIM23_CCMR1_OC1M_SET_HIGH_ON_MATCH 1 +#define STM_TIM23_CCMR1_OC1M_SET_LOW_ON_MATCH 2 +#define STM_TIM23_CCMR1_OC1M_TOGGLE 3 +#define STM_TIM23_CCMR1_OC1M_FORCE_LOW 4 +#define STM_TIM23_CCMR1_OC1M_FORCE_HIGH 5 +#define STM_TIM23_CCMR1_OC1M_PWM_MODE_1 6 +#define STM_TIM23_CCMR1_OC1M_PWM_MODE_2 7 +#define STM_TIM23_CCMR1_OC1M_MASK 7 +#define STM_TIM23_CCMR1_OC1PE 11 +#define STM_TIM23_CCMR1_OC1FE 2 +#define STM_TIM23_CCMR1_CC1S 0 +#define STM_TIM23_CCMR1_CC1S_OUTPUT 0 +#define STM_TIM23_CCMR1_CC1S_INPUT_TI1 1 +#define STM_TIM23_CCMR1_CC1S_INPUT_TI2 2 +#define STM_TIM23_CCMR1_CC1S_INPUT_TRC 3 +#define STM_TIM23_CCMR1_CC1S_MASK 3 + +#define STM_TIM23_CCMR2_OC4CE 15 +#define STM_TIM23_CCMR2_OC4M 12 +#define STM_TIM23_CCMR2_OC4M_FROZEN 0 +#define STM_TIM23_CCMR2_OC4M_SET_HIGH_ON_MATCH 1 +#define STM_TIM23_CCMR2_OC4M_SET_LOW_ON_MATCH 2 +#define STM_TIM23_CCMR2_OC4M_TOGGLE 3 +#define STM_TIM23_CCMR2_OC4M_FORCE_LOW 4 +#define STM_TIM23_CCMR2_OC4M_FORCE_HIGH 5 +#define STM_TIM23_CCMR2_OC4M_PWM_MODE_1 6 +#define STM_TIM23_CCMR2_OC4M_PWM_MODE_2 7 +#define STM_TIM23_CCMR2_OC4M_MASK 7 +#define STM_TIM23_CCMR2_OC4PE 11 +#define STM_TIM23_CCMR2_OC4FE 10 +#define STM_TIM23_CCMR2_CC4S 8 +#define STM_TIM23_CCMR2_CC4S_OUTPUT 0 +#define STM_TIM23_CCMR2_CC4S_INPUT_TI4 1 +#define STM_TIM23_CCMR2_CC4S_INPUT_TI3 2 +#define STM_TIM23_CCMR2_CC4S_INPUT_TRC 3 +#define STM_TIM23_CCMR2_CC4S_MASK 3 + +#define STM_TIM23_CCMR2_OC3CE 7 +#define STM_TIM23_CCMR2_OC3M 4 +#define STM_TIM23_CCMR2_OC3M_FROZEN 0 +#define STM_TIM23_CCMR2_OC3M_SET_HIGH_ON_MATCH 1 +#define STM_TIM23_CCMR2_OC3M_SET_LOW_ON_MATCH 2 +#define STM_TIM23_CCMR2_OC3M_TOGGLE 3 +#define STM_TIM23_CCMR2_OC3M_FORCE_LOW 4 +#define STM_TIM23_CCMR2_OC3M_FORCE_HIGH 5 +#define STM_TIM23_CCMR2_OC3M_PWM_MODE_1 6 +#define STM_TIM23_CCMR2_OC3M_PWM_MODE_2 7 +#define STM_TIM23_CCMR2_OC3M_MASK 7 +#define STM_TIM23_CCMR2_OC3PE 11 +#define STM_TIM23_CCMR2_OC3FE 2 +#define STM_TIM23_CCMR2_CC3S 0 +#define STM_TIM23_CCMR2_CC3S_OUTPUT 0 +#define STM_TIM23_CCMR2_CC3S_INPUT_TI3 1 +#define STM_TIM23_CCMR2_CC3S_INPUT_TI4 2 +#define STM_TIM23_CCMR2_CC3S_INPUT_TRC 3 +#define STM_TIM23_CCMR2_CC3S_MASK 3 + +#define STM_TIM23_CCER_CC4NP 15 +#define STM_TIM23_CCER_CC4P 13 +#define STM_TIM23_CCER_CC4E 12 +#define STM_TIM23_CCER_CC3NP 11 +#define STM_TIM23_CCER_CC3P 9 +#define STM_TIM23_CCER_CC3E 8 +#define STM_TIM23_CCER_CC2NP 7 +#define STM_TIM23_CCER_CC2P 5 +#define STM_TIM23_CCER_CC2E 4 +#define STM_TIM23_CCER_CC1NP 3 +#define STM_TIM23_CCER_CC1P 1 +#define STM_TIM23_CCER_CC1E 0 struct stm_usb { struct { -- 2.30.2