From e38e1a2f735a1bb4aebf0817cdd99a05567c6340 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Mon, 18 Mar 2019 17:20:14 -0700 Subject: [PATCH] altos/stm32f4: Wrong value for CK48MSEL_PLL_Q This meant that the USB clock wasn't actually getting started... Signed-off-by: Keith Packard --- src/stm32f4/ao_exti.h | 4 ++-- src/stm32f4/ao_exti_stm32f4.c | 2 +- src/stm32f4/stm32f4.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/stm32f4/ao_exti.h b/src/stm32f4/ao_exti.h index 0216f352..03246605 100644 --- a/src/stm32f4/ao_exti.h +++ b/src/stm32f4/ao_exti.h @@ -30,13 +30,13 @@ #define AO_EXTI_PIN_NOCONFIGURE 64 void -ao_exti_setup(struct stm_gpio *gpio, uint8_t pin, uint8_t mode, void (*callback)()); +ao_exti_setup(struct stm_gpio *gpio, uint8_t pin, uint8_t mode, void (*callback)(void)); void ao_exti_set_mode(struct stm_gpio *gpio, uint8_t pin, uint8_t mode); void -ao_exti_set_callback(struct stm_gpio *gpio, uint8_t pin, void (*callback)()); +ao_exti_set_callback(struct stm_gpio *gpio, uint8_t pin, void (*callback)(void)); void ao_exti_enable(struct stm_gpio *gpio, uint8_t pin); diff --git a/src/stm32f4/ao_exti_stm32f4.c b/src/stm32f4/ao_exti_stm32f4.c index 1e288f9c..900fe903 100644 --- a/src/stm32f4/ao_exti_stm32f4.c +++ b/src/stm32f4/ao_exti_stm32f4.c @@ -135,7 +135,7 @@ ao_exti_set_mode(struct stm_gpio *gpio, uint8_t pin, uint8_t mode) { } void -ao_exti_set_callback(struct stm_gpio *gpio, uint8_t pin, void (*callback)()) { +ao_exti_set_callback(struct stm_gpio *gpio, uint8_t pin, void (*callback)(void)) { (void) gpio; ao_exti_callback[pin] = callback; } diff --git a/src/stm32f4/stm32f4.h b/src/stm32f4/stm32f4.h index 3e8ec957..94ee23bf 100644 --- a/src/stm32f4/stm32f4.h +++ b/src/stm32f4/stm32f4.h @@ -269,7 +269,7 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_DCKCFGR2_SDIOSEL_CK_48MHZ 0 #define STM_RCC_DCKCFGR2_SDIOSEL_SYSTEM_CLOCK 1 #define STM_RCC_DCKCFGR2_CK48MSEL 27 -#define STM_RCC_DCKCFGR2_CK48MSEL_PLL_Q 1 +#define STM_RCC_DCKCFGR2_CK48MSEL_PLL_Q 0 #define STM_RCC_DCKCFGR2_CK48MSEL_PLLI2S_Q 1 #define STM_RCC_DCKCFGR2_I2CFMP1SEL 22 #define STM_RCC_DCKCFGR2_I2CFMP1SEL_APB 0 -- 2.30.2