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ICP3 working
author
Robert Garbee
<robert@gag.com>
Wed, 18 Jul 2012 20:24:05 +0000
(14:24 -0600)
committer
Keith Packard
<keithp@keithp.com>
Wed, 17 Oct 2012 05:16:31 +0000
(22:16 -0700)
src/avr/ao_pwmin.c
patch
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diff --git
a/src/avr/ao_pwmin.c
b/src/avr/ao_pwmin.c
index edcb163641cea8a1aa28db542e787d4f9650f892..73a153b2e4cc67332b879e18b02febe1333687c5 100644
(file)
--- a/
src/avr/ao_pwmin.c
+++ b/
src/avr/ao_pwmin.c
@@
-25,27
+25,20
@@
* project payload developed at Challenger Middle School.
*/
* project payload developed at Challenger Middle School.
*/
-volatile __data uint16_t ao_
tick
3_count;
+volatile __data uint16_t ao_
icp
3_count;
static void
ao_pwmin_display(void) __reentrant
{
static void
ao_pwmin_display(void) __reentrant
{
- uint8_t lo = TCNT1L;
- uint8_t hi = TCNT1H;
- uint16_t value = (hi <<8) | lo;
-
- uint8_t lo3 = TCNT3L;
- uint8_t hi3 = TCNT3H;
- uint16_t value3 = (hi3 <<8) | lo3;
-
- /* now display the value we read */
- printf("timer 1: %5u %2x %2x\n", value, hi, lo);
- printf("timer 3: %5u %2x %2x\n", value3, hi3, lo3);
+ /* display the most recent value */
+ printf("icp 3: %5u\n", ao_icp3_count);
}
}
-ISR(TIMER3_C
OMPA
_vect)
+ISR(TIMER3_C
APT
_vect)
{
{
- ++ao_tick3_count;
+ uint8_t lo = ICR3L;
+ uint8_t hi = ICR3H;
+ ao_icp3_count = (hi <<8) | lo;
}
__code struct ao_cmds ao_pwmin_cmds[] = {
}
__code struct ao_cmds ao_pwmin_cmds[] = {
@@
-59,15
+52,15
@@
ao_pwmin_init(void)
/* do hardware setup here */
TCCR3A = ((0 << WGM31) | /* normal mode, OCR3A */
(0 << WGM30)); /* normal mode, OCR3A */
/* do hardware setup here */
TCCR3A = ((0 << WGM31) | /* normal mode, OCR3A */
(0 << WGM30)); /* normal mode, OCR3A */
- TCCR3B = ((
0 << ICNC3) | /* no input capture noise canceler
*/
+ TCCR3B = ((
1 << ICNC3) | /* input capture noise canceler on
*/
(0 << ICES3) | /* input capture on falling edge (don't care) */
(0 << WGM33) | /* normal mode, OCR3A */
(0 << WGM32) | /* normal mode, OCR3A */
(4 << CS30)); /* clk/256 from prescaler */
(0 << ICES3) | /* input capture on falling edge (don't care) */
(0 << WGM33) | /* normal mode, OCR3A */
(0 << WGM32) | /* normal mode, OCR3A */
(4 << CS30)); /* clk/256 from prescaler */
- OCR3A = 1250; /* 8MHz clock */
+
- TIMSK3 = (1 <<
OCIE3A); /* Interrupt on compare match
*/
+ TIMSK3 = (1 <<
ICIE3); /* Interrupt on input compare
*/
/* set the spike filter bit in the TCCR3B register */
/* set the spike filter bit in the TCCR3B register */