#define stm_gpiob (*((struct stm_gpio *) 0x48000400))
#define stm_gpioa (*((struct stm_gpio *) 0x48000000))
-struct stm_usart {
- vuint32_t cr1; /* control register 1 */
- vuint32_t cr2; /* control register 2 */
- vuint32_t cr3; /* control register 3 */
- vuint32_t brr; /* baud rate register */
-
- vuint32_t gtpr; /* guard time and prescaler */
- vuint32_t rtor; /* */
- vuint32_t rqr; /* */
- vuint32_t isr; /* */
-
- vuint32_t icr; /* */
- vuint32_t rdr; /* */
- vuint32_t tdr; /* */
-};
-
-extern struct stm_usart stm_usart1;
-extern struct stm_usart stm_usart2;
-
-#define STM_USART_SR_CTS (9) /* CTS flag */
-#define STM_USART_SR_LBD (8) /* LIN break detection flag */
-#define STM_USART_SR_TXE (7) /* Transmit data register empty */
-#define STM_USART_SR_TC (6) /* Transmission complete */
-#define STM_USART_SR_RXNE (5) /* Read data register not empty */
-#define STM_USART_SR_IDLE (4) /* IDLE line detected */
-#define STM_USART_SR_ORE (3) /* Overrun error */
-#define STM_USART_SR_NF (2) /* Noise detected flag */
-#define STM_USART_SR_FE (1) /* Framing error */
-#define STM_USART_SR_PE (0) /* Parity error */
-
-#define STM_USART_CR1_OVER8 (15) /* Oversampling mode */
-#define STM_USART_CR1_UE (13) /* USART enable */
-#define STM_USART_CR1_M (12) /* Word length */
-#define STM_USART_CR1_WAKE (11) /* Wakeup method */
-#define STM_USART_CR1_PCE (10) /* Parity control enable */
-#define STM_USART_CR1_PS (9) /* Parity selection */
-#define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
-#define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
-#define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
-#define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
-#define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
-#define STM_USART_CR1_TE (3) /* Transmitter enable */
-#define STM_USART_CR1_RE (2) /* Receiver enable */
-#define STM_USART_CR1_RWU (1) /* Receiver wakeup */
-#define STM_USART_CR1_SBK (0) /* Send break */
-
-#define STM_USART_CR2_LINEN (14) /* LIN mode enable */
-#define STM_USART_CR2_STOP (12) /* STOP bits */
-#define STM_USART_CR2_STOP_MASK 3
-#define STM_USART_CR2_STOP_1 0
-#define STM_USART_CR2_STOP_0_5 1
-#define STM_USART_CR2_STOP_2 2
-#define STM_USART_CR2_STOP_1_5 3
-
-#define STM_USART_CR2_CLKEN (11) /* Clock enable */
-#define STM_USART_CR2_CPOL (10) /* Clock polarity */
-#define STM_USART_CR2_CPHA (9) /* Clock phase */
-#define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
-#define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
-#define STM_USART_CR2_LBDL (5) /* lin break detection length */
-#define STM_USART_CR2_ADD (0)
-#define STM_USART_CR2_ADD_MASK 0xf
-
-#define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */
-#define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
-#define STM_USART_CR3_CTSE (9) /* CTS enable */
-#define STM_USART_CR3_RTSE (8) /* RTS enable */
-#define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
-#define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
-#define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
-#define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
-#define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
-#define STM_USART_CR3_IRLP (2) /* IrDA low-power */
-#define STM_USART_CR3_IREN (1) /* IrDA mode enable */
-#define STM_USART_CR3_EIE (0) /* Error interrupt enable */
-
-struct stm_tim {
-};
-
-extern struct stm_tim stm_tim9;
-
-struct stm_tim1011 {
- vuint32_t cr1;
- uint32_t unused_4;
- vuint32_t smcr;
- vuint32_t dier;
- vuint32_t sr;
- vuint32_t egr;
- vuint32_t ccmr1;
- uint32_t unused_1c;
- vuint32_t ccer;
- vuint32_t cnt;
- vuint32_t psc;
- vuint32_t arr;
- uint32_t unused_30;
- vuint32_t ccr1;
- uint32_t unused_38;
- uint32_t unused_3c;
- uint32_t unused_40;
- uint32_t unused_44;
- uint32_t unused_48;
- uint32_t unused_4c;
- vuint32_t or;
-};
-
-extern struct stm_tim1011 stm_tim10;
-extern struct stm_tim1011 stm_tim11;
-
-#define STM_TIM1011_CR1_CKD 8
-#define STM_TIM1011_CR1_CKD_1 0
-#define STM_TIM1011_CR1_CKD_2 1
-#define STM_TIM1011_CR1_CKD_4 2
-#define STM_TIM1011_CR1_CKD_MASK 3
-#define STM_TIM1011_CR1_ARPE 7
-#define STM_TIM1011_CR1_URS 2
-#define STM_TIM1011_CR1_UDIS 1
-#define STM_TIM1011_CR1_CEN 0
-
-#define STM_TIM1011_SMCR_ETP 15
-#define STM_TIM1011_SMCR_ECE 14
-#define STM_TIM1011_SMCR_ETPS 12
-#define STM_TIM1011_SMCR_ETPS_OFF 0
-#define STM_TIM1011_SMCR_ETPS_2 1
-#define STM_TIM1011_SMCR_ETPS_4 2
-#define STM_TIM1011_SMCR_ETPS_8 3
-#define STM_TIM1011_SMCR_ETPS_MASK 3
-#define STM_TIM1011_SMCR_ETF 8
-#define STM_TIM1011_SMCR_ETF_NONE 0
-#define STM_TIM1011_SMCR_ETF_CK_INT_2 1
-#define STM_TIM1011_SMCR_ETF_CK_INT_4 2
-#define STM_TIM1011_SMCR_ETF_CK_INT_8 3
-#define STM_TIM1011_SMCR_ETF_DTS_2_6 4
-#define STM_TIM1011_SMCR_ETF_DTS_2_8 5
-#define STM_TIM1011_SMCR_ETF_DTS_4_6 6
-#define STM_TIM1011_SMCR_ETF_DTS_4_8 7
-#define STM_TIM1011_SMCR_ETF_DTS_8_6 8
-#define STM_TIM1011_SMCR_ETF_DTS_8_8 9
-#define STM_TIM1011_SMCR_ETF_DTS_16_5 10
-#define STM_TIM1011_SMCR_ETF_DTS_16_6 11
-#define STM_TIM1011_SMCR_ETF_DTS_16_8 12
-#define STM_TIM1011_SMCR_ETF_DTS_32_5 13
-#define STM_TIM1011_SMCR_ETF_DTS_32_6 14
-#define STM_TIM1011_SMCR_ETF_DTS_32_8 15
-#define STM_TIM1011_SMCR_ETF_MASK 15
-
-#define STM_TIM1011_DIER_CC1E 1
-#define STM_TIM1011_DIER_UIE 0
-
-#define STM_TIM1011_SR_CC1OF 9
-#define STM_TIM1011_SR_CC1IF 1
-#define STM_TIM1011_SR_UIF 0
-
-#define STM_TIM1011_EGR_CC1G 1
-#define STM_TIM1011_EGR_UG 0
-
-#define STM_TIM1011_CCMR1_OC1CE 7
-#define STM_TIM1011_CCMR1_OC1M 4
-#define STM_TIM1011_CCMR1_OC1M_FROZEN 0
-#define STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH 1
-#define STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
-#define STM_TIM1011_CCMR1_OC1M_TOGGLE 3
-#define STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE 4
-#define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5
-#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6
-#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7
-#define STM_TIM1011_CCMR1_OC1M_MASK 7
-#define STM_TIM1011_CCMR1_OC1PE 3
-#define STM_TIM1011_CCMR1_OC1FE 2
-#define STM_TIM1011_CCMR1_CC1S 0
-#define STM_TIM1011_CCMR1_CC1S_OUTPUT 0
-#define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1
-#define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2
-#define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3
-#define STM_TIM1011_CCMR1_CC1S_MASK 3
-
-#define STM_TIM1011_CCMR1_IC1F_NONE 0
-#define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1
-#define STM_TIM1011_CCMR1_IC1F_CK_INT_4 2
-#define STM_TIM1011_CCMR1_IC1F_CK_INT_8 3
-#define STM_TIM1011_CCMR1_IC1F_DTS_2_6 4
-#define STM_TIM1011_CCMR1_IC1F_DTS_2_8 5
-#define STM_TIM1011_CCMR1_IC1F_DTS_4_6 6
-#define STM_TIM1011_CCMR1_IC1F_DTS_4_8 7
-#define STM_TIM1011_CCMR1_IC1F_DTS_8_6 8
-#define STM_TIM1011_CCMR1_IC1F_DTS_8_8 9
-#define STM_TIM1011_CCMR1_IC1F_DTS_16_5 10
-#define STM_TIM1011_CCMR1_IC1F_DTS_16_6 11
-#define STM_TIM1011_CCMR1_IC1F_DTS_16_8 12
-#define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13
-#define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14
-#define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15
-#define STM_TIM1011_CCMR1_IC1F_MASK 15
-#define STM_TIM1011_CCMR1_IC1PSC 2
-#define STM_TIM1011_CCMR1_IC1PSC_1 0
-#define STM_TIM1011_CCMR1_IC1PSC_2 1
-#define STM_TIM1011_CCMR1_IC1PSC_4 2
-#define STM_TIM1011_CCMR1_IC1PSC_8 3
-#define STM_TIM1011_CCMR1_IC1PSC_MASK 3
-#define STM_TIM1011_CCMR1_CC1S 0
-
-#define STM_TIM1011_CCER_CC1NP 3
-#define STM_TIM1011_CCER_CC1P 1
-#define STM_TIM1011_CCER_CC1E 0
-
-#define STM_TIM1011_OR_TI1_RMP_RI 3
-#define STM_TIM1011_ETR_RMP 2
-#define STM_TIM1011_TI1_RMP 0
-#define STM_TIM1011_TI1_RMP_GPIO 0
-#define STM_TIM1011_TI1_RMP_LSI 1
-#define STM_TIM1011_TI1_RMP_LSE 2
-#define STM_TIM1011_TI1_RMP_RTC 3
-#define STM_TIM1011_TI1_RMP_MASK 3
-
/* Flash interface */
struct stm_flash {
#define STM_PWR_CSR_SBF (1)
#define STM_PWR_CSR_WUF (0)
-struct stm_tim67 {
- vuint32_t cr1;
- vuint32_t cr2;
- uint32_t _unused_08;
- vuint32_t dier;
-
- vuint32_t sr;
- vuint32_t egr;
- uint32_t _unused_18;
- uint32_t _unused_1c;
-
- uint32_t _unused_20;
- vuint32_t cnt;
- vuint32_t psc;
- vuint32_t arr;
-};
-
-extern struct stm_tim67 stm_tim6;
-
-#define STM_TIM67_CR1_ARPE (7)
-#define STM_TIM67_CR1_OPM (3)
-#define STM_TIM67_CR1_URS (2)
-#define STM_TIM67_CR1_UDIS (1)
-#define STM_TIM67_CR1_CEN (0)
-
-#define STM_TIM67_CR2_MMS (4)
-#define STM_TIM67_CR2_MMS_RESET 0
-#define STM_TIM67_CR2_MMS_ENABLE 1
-#define STM_TIM67_CR2_MMS_UPDATE 2
-#define STM_TIM67_CR2_MMS_MASK 7
-
-#define STM_TIM67_DIER_UDE (8)
-#define STM_TIM67_DIER_UIE (0)
-
-#define STM_TIM67_SR_UIF (0)
-
-#define STM_TIM67_EGR_UG (0)
-
-struct stm_lcd {
- vuint32_t cr;
- vuint32_t fcr;
- vuint32_t sr;
- vuint32_t clr;
- uint32_t unused_0x10;
- vuint32_t ram[8*2];
-};
-
-extern struct stm_lcd stm_lcd;
-
-#define STM_LCD_CR_MUX_SEG (7)
-
-#define STM_LCD_CR_BIAS (5)
-#define STM_LCD_CR_BIAS_1_4 0
-#define STM_LCD_CR_BIAS_1_2 1
-#define STM_LCD_CR_BIAS_1_3 2
-#define STM_LCD_CR_BIAS_MASK 3
-
-#define STM_LCD_CR_DUTY (2)
-#define STM_LCD_CR_DUTY_STATIC 0
-#define STM_LCD_CR_DUTY_1_2 1
-#define STM_LCD_CR_DUTY_1_3 2
-#define STM_LCD_CR_DUTY_1_4 3
-#define STM_LCD_CR_DUTY_1_8 4
-#define STM_LCD_CR_DUTY_MASK 7
-
-#define STM_LCD_CR_VSEL (1)
-#define STM_LCD_CR_LCDEN (0)
-
-#define STM_LCD_FCR_PS (22)
-#define STM_LCD_FCR_PS_1 0x0
-#define STM_LCD_FCR_PS_2 0x1
-#define STM_LCD_FCR_PS_4 0x2
-#define STM_LCD_FCR_PS_8 0x3
-#define STM_LCD_FCR_PS_16 0x4
-#define STM_LCD_FCR_PS_32 0x5
-#define STM_LCD_FCR_PS_64 0x6
-#define STM_LCD_FCR_PS_128 0x7
-#define STM_LCD_FCR_PS_256 0x8
-#define STM_LCD_FCR_PS_512 0x9
-#define STM_LCD_FCR_PS_1024 0xa
-#define STM_LCD_FCR_PS_2048 0xb
-#define STM_LCD_FCR_PS_4096 0xc
-#define STM_LCD_FCR_PS_8192 0xd
-#define STM_LCD_FCR_PS_16384 0xe
-#define STM_LCD_FCR_PS_32768 0xf
-#define STM_LCD_FCR_PS_MASK 0xf
-
-#define STM_LCD_FCR_DIV (18)
-#define STM_LCD_FCR_DIV_16 0x0
-#define STM_LCD_FCR_DIV_17 0x1
-#define STM_LCD_FCR_DIV_18 0x2
-#define STM_LCD_FCR_DIV_19 0x3
-#define STM_LCD_FCR_DIV_20 0x4
-#define STM_LCD_FCR_DIV_21 0x5
-#define STM_LCD_FCR_DIV_22 0x6
-#define STM_LCD_FCR_DIV_23 0x7
-#define STM_LCD_FCR_DIV_24 0x8
-#define STM_LCD_FCR_DIV_25 0x9
-#define STM_LCD_FCR_DIV_26 0xa
-#define STM_LCD_FCR_DIV_27 0xb
-#define STM_LCD_FCR_DIV_28 0xc
-#define STM_LCD_FCR_DIV_29 0xd
-#define STM_LCD_FCR_DIV_30 0xe
-#define STM_LCD_FCR_DIV_31 0xf
-#define STM_LCD_FCR_DIV_MASK 0xf
-
-#define STM_LCD_FCR_BLINK (16)
-#define STM_LCD_FCR_BLINK_DISABLE 0
-#define STM_LCD_FCR_BLINK_SEG0_COM0 1
-#define STM_LCD_FCR_BLINK_SEG0_COMALL 2
-#define STM_LCD_FCR_BLINK_SEGALL_COMALL 3
-#define STM_LCD_FCR_BLINK_MASK 3
-
-#define STM_LCD_FCR_BLINKF (13)
-#define STM_LCD_FCR_BLINKF_8 0
-#define STM_LCD_FCR_BLINKF_16 1
-#define STM_LCD_FCR_BLINKF_32 2
-#define STM_LCD_FCR_BLINKF_64 3
-#define STM_LCD_FCR_BLINKF_128 4
-#define STM_LCD_FCR_BLINKF_256 5
-#define STM_LCD_FCR_BLINKF_512 6
-#define STM_LCD_FCR_BLINKF_1024 7
-#define STM_LCD_FCR_BLINKF_MASK 7
-
-#define STM_LCD_FCR_CC (10)
-#define STM_LCD_FCR_CC_MASK 7
-
-#define STM_LCD_FCR_DEAD (7)
-#define STM_LCD_FCR_DEAD_MASK 7
-
-#define STM_LCD_FCR_PON (4)
-#define STM_LCD_FCR_PON_MASK 7
-
-#define STM_LCD_FCR_UDDIE (3)
-#define STM_LCD_FCR_SOFIE (1)
-#define STM_LCD_FCR_HD (0)
-
-#define STM_LCD_SR_FCRSF (5)
-#define STM_LCD_SR_RDY (4)
-#define STM_LCD_SR_UDD (3)
-#define STM_LCD_SR_UDR (2)
-#define STM_LCD_SR_SOF (1)
-#define STM_LCD_SR_ENS (0)
-
-#define STM_LCD_CLR_UDDC (3)
-#define STM_LCD_CLR_SOFC (1)
-
/* The SYSTICK starts at 0xe000e010 */
struct stm_systick {
#define STM_SCB_AIRCR_VECTCLRACTIVE 1
#define STM_SCB_AIRCR_VECTRESET 0
-struct stm_mpu {
- vuint32_t typer;
- vuint32_t cr;
- vuint32_t rnr;
- vuint32_t rbar;
-
- vuint32_t rasr;
- vuint32_t rbar_a1;
- vuint32_t rasr_a1;
- vuint32_t rbar_a2;
- vuint32_t rasr_a2;
- vuint32_t rbar_a3;
- vuint32_t rasr_a3;
-};
-
-extern struct stm_mpu stm_mpu;
-
-#define STM_MPU_TYPER_IREGION 16
-#define STM_MPU_TYPER_IREGION_MASK 0xff
-#define STM_MPU_TYPER_DREGION 8
-#define STM_MPU_TYPER_DREGION_MASK 0xff
-#define STM_MPU_TYPER_SEPARATE 0
-
-#define STM_MPU_CR_PRIVDEFENA 2
-#define STM_MPU_CR_HFNMIENA 1
-#define STM_MPU_CR_ENABLE 0
-
-#define STM_MPU_RNR_REGION 0
-#define STM_MPU_RNR_REGION_MASK 0xff
-
-#define STM_MPU_RBAR_ADDR 5
-#define STM_MPU_RBAR_ADDR_MASK 0x7ffffff
-
-#define STM_MPU_RBAR_VALID 4
-#define STM_MPU_RBAR_REGION 0
-#define STM_MPU_RBAR_REGION_MASK 0xf
-
-#define STM_MPU_RASR_XN 28
-#define STM_MPU_RASR_AP 24
-#define STM_MPU_RASR_AP_NONE_NONE 0
-#define STM_MPU_RASR_AP_RW_NONE 1
-#define STM_MPU_RASR_AP_RW_RO 2
-#define STM_MPU_RASR_AP_RW_RW 3
-#define STM_MPU_RASR_AP_RO_NONE 5
-#define STM_MPU_RASR_AP_RO_RO 6
-#define STM_MPU_RASR_AP_MASK 7
-#define STM_MPU_RASR_TEX 19
-#define STM_MPU_RASR_TEX_MASK 7
-#define STM_MPU_RASR_S 18
-#define STM_MPU_RASR_C 17
-#define STM_MPU_RASR_B 16
-#define STM_MPU_RASR_SRD 8
-#define STM_MPU_RASR_SRD_MASK 0xff
-#define STM_MPU_RASR_SIZE 1
-#define STM_MPU_RASR_SIZE_MASK 0x1f
-#define STM_MPU_RASR_ENABLE 0
-
#define isr(name) void stm_ ## name ## _isr(void);
isr(nmi)
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