#include <ao_cc1120.h>
#include <ao_exti.h>
-uint8_t ao_radio_done;
+uint8_t ao_radio_wake;
uint8_t ao_radio_mutex;
uint8_t ao_radio_abort;
uint32_t ao_radio_cal = 1186611;
+#define FOSC 32000000
+
#define ao_radio_select() ao_spi_get_mask(AO_CC1120_SPI_CS_PORT,(1 << AO_CC1120_SPI_CS_PIN),AO_CC1120_SPI_BUS)
#define ao_radio_deselect() ao_spi_put_mask(AO_CC1120_SPI_CS_PORT,(1 << AO_CC1120_SPI_CS_PIN),AO_CC1120_SPI_BUS)
#define ao_radio_spi_send(d,l) ao_spi_send((d), (l), AO_CC1120_SPI_BUS)
uint8_t d;
#if CC1120_DEBUG
- printf("ao_radio_reg_read (%04x): ", addr); flush();
+ printf("\t\tao_radio_reg_read (%04x): ", addr); flush();
#endif
if (CC1120_IS_EXTENDED(addr)) {
data[0] = ((1 << CC1120_READ) |
uint8_t d;
#if CC1120_DEBUG
- printf("ao_radio_reg_write (%04x): %02x\n", addr, value);
+ printf("\t\tao_radio_reg_write (%04x): %02x\n", addr, value);
#endif
if (CC1120_IS_EXTENDED(addr)) {
data[0] = ((1 << CC1120_READ) |
{
uint8_t in;
+#if CC1120_DEBUG
+ printf("\t\tao_radio_strobe (%02x): ", addr); flush();
+#endif
ao_radio_select();
ao_radio_duplex(&addr, &in, 1);
ao_radio_deselect();
+#if CC1120_DEBUG
+ printf("%02x\n", in);
+#endif
return in;
}
CC1120_FIFO);
uint8_t status;
+ printf ("num tx bytes: %d\n", ao_radio_reg_read(CC1120_NUM_TXBYTES));
ao_radio_select();
ao_radio_duplex(&addr, &status, 1);
ao_radio_spi_send_fixed(data, len);
ao_radio_deselect();
+ printf ("num tx bytes: %d\n", ao_radio_reg_read(CC1120_NUM_TXBYTES));
return status;
}
ao_radio_recv_abort(void)
{
ao_radio_abort = 1;
- ao_wakeup(&ao_radio_done);
+ ao_wakeup(&ao_radio_wake);
}
#define ao_radio_rdf_value 0x55
-static const uint16_t rdf_setup[] = {
+/*
+ * RDF deviation is 5kHz
+ *
+ * fdev = fosc >> 24 * (256 + dev_m) << dev_e
+ *
+ * 32e6Hz / (2 ** 24) * (256 + 71) * (2 ** 3) = 4989
+ */
+
+#define RDF_DEV_E 3
+#define RDF_DEV_M 71
+#define RDF_PACKET_LEN 50
+
+/*
+ * For our RDF beacon, set the symbol rate to 2kBaud (for a 1kHz tone)
+ *
+ * (2**20 - DATARATE_M) * 2 ** DATARATE_E
+ * Rdata = -------------------------------------- * fosc
+ * 2 ** 39
+ *
+ * DATARATE_M = 511705
+ * DATARATE_E = 6
+ *
+ * To make the tone last for 200ms, we need 2000 * .2 = 400 bits or 50 bytes
+ */
+#define RDF_DRATE_E 6
+#define RDF_DRATE_M 511705
+#define RDF_PACKET_LEN 50
+
+static const uint16_t rdf_setup[] = {
+ CC1120_DEVIATION_M, RDF_DEV_M,
+ CC1120_MODCFG_DEV_E, ((CC1120_MODCFG_DEV_E_MODEM_MODE_NORMAL << CC1120_MODCFG_DEV_E_MODEM_MODE) |
+ (CC1120_MODCFG_DEV_E_MOD_FORMAT_2_GFSK << CC1120_MODCFG_DEV_E_MOD_FORMAT) |
+ (RDF_DEV_E << CC1120_MODCFG_DEV_E_DEV_E)),
+ CC1120_DRATE2, ((RDF_DRATE_E << CC1120_DRATE2_DATARATE_E) |
+ (((RDF_DRATE_M >> 16) & CC1120_DRATE2_DATARATE_M_19_16_MASK) << CC1120_DRATE2_DATARATE_M_19_16)),
+ CC1120_DRATE1, ((RDF_DRATE_M >> 8) & 0xff),
+ CC1120_DRATE0, ((RDF_DRATE_M >> 0) & 0xff),
+ CC1120_PKT_CFG2, ((CC1120_PKT_CFG2_CCA_MODE_ALWAYS_CLEAR << CC1120_PKT_CFG2_CCA_MODE) |
+ (CC1120_PKT_CFG2_PKT_FORMAT_NORMAL << CC1120_PKT_CFG2_PKT_FORMAT)),
+ CC1120_PKT_CFG1, ((0 << CC1120_PKT_CFG1_WHITE_DATA) |
+ (CC1120_PKT_CFG1_ADDR_CHECK_CFG_NONE << CC1120_PKT_CFG1_ADDR_CHECK_CFG) |
+ (CC1120_PKT_CFG1_CRC_CFG_DISABLED << CC1120_PKT_CFG1_CRC_CFG) |
+ (0 << CC1120_PKT_CFG1_APPEND_STATUS)),
};
+#define int_pin(w) printf("\t%s: %d\n", \
+ w,\
+ (AO_CC1120_INT_PORT.idr >> AO_CC1120_INT_PIN) & 1)
+
+static uint8_t
+ao_radio_marc_status(void)
+{
+ return ao_radio_reg_read(CC1120_MARC_STATUS1);
+}
+
+static uint8_t
+ao_radio_tx_done(void)
+{
+ return ao_radio_marc_status() == CC1120_MARC_STATUS1_TX_FINISHED;
+}
+
+static uint8_t
+ao_radio_rx_done(void)
+{
+ return ao_radio_marc_status() == CC1120_MARC_STATUS1_RX_FINISHED;
+}
+
void
ao_radio_rdf(uint8_t len)
{
int i;
- ao_radio_abort = 0;
ao_radio_get(len);
- ao_radio_done = 0;
+ ao_radio_abort = 0;
for (i = 0; i < sizeof (rdf_setup) / sizeof (rdf_setup[0]); i += 2)
ao_radio_reg_write(rdf_setup[i], rdf_setup[i+1]);
- ao_radio_fifo_write_fixed(ao_radio_rdf_value, len);
+ ao_radio_reg_write(CC1120_PKT_LEN, len);
+ int_pin ("Before CFG");
ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_RX0TX1_CFG);
- ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
+ int_pin ("After CFG");
ao_radio_strobe(CC1120_STX);
+ ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
+ int_pin ("After strobe");
+ ao_delay(AO_MS_TO_TICKS(100));
+ ao_radio_fifo_write_fixed(ao_radio_rdf_value, len);
+ int_pin ("After delay");
cli();
- while (!ao_radio_done)
- ao_sleep(&ao_radio_done);
+ for (i = 0; i < 20; i++) {
+#if CC1120_DEBUG
+ ao_delay(AO_MS_TO_TICKS(50));
+ int_pin ("Waited");
+ printf ("Status %02x num_tx_bytes %d marc status %x\n",
+ ao_radio_status(),
+ ao_radio_reg_read(CC1120_NUM_TXBYTES),
+ ao_radio_marc_status());
+#else
+ ao_sleep(&ao_radio_wake);
+#endif
+ }
sei();
+ printf ("num_tx_bytes %d marc status %x\n",
+ ao_radio_reg_read(CC1120_NUM_TXBYTES),
+ ao_radio_marc_status());
+ if (!ao_radio_tx_done())
+ ao_radio_idle();
ao_radio_set_packet();
ao_radio_put();
}
void
ao_radio_rdf_abort(void)
{
+ ao_radio_abort = 1;
+ ao_wakeup(&ao_radio_wake);
}
static void
#endif
ao_radio_get(0xff);
ao_radio_strobe(CC1120_STX);
+#if CC1120_DEBUG
+ { int t;
+ for (t = 0; t < 10; t++) {
+ printf ("status: %02x\n", ao_radio_status());
+ ao_delay(AO_MS_TO_TICKS(100));
+ }
+ }
+#endif
radio_on = 1;
}
if (mode == 3) {
void
ao_radio_send(void *d, uint8_t size)
{
+ uint8_t marc_status;
+
ao_radio_get(size);
- ao_radio_done = 0;
+ ao_radio_wake = 0;
ao_radio_fifo_write(d, size);
- ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_RX0TX1_CFG);
ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
ao_radio_strobe(CC1120_STX);
cli();
- while (!ao_radio_done)
- ao_sleep(&ao_radio_done);
+ for (;;) {
+ if (ao_radio_wake) {
+ marc_status = ao_radio_marc_status();
+ if (marc_status != CC1120_MARC_STATUS1_NO_FAILURE)
+ break;
+ ao_radio_wake = 0;
+ }
+ ao_sleep(&ao_radio_wake);
+ }
sei();
ao_radio_put();
}
uint8_t
ao_radio_recv(__xdata void *d, uint8_t size)
{
+ uint8_t marc_status = CC1120_MARC_STATUS1_NO_FAILURE;
+
/* configure interrupt pin */
ao_radio_get(size);
- ao_radio_done = 0;
- ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_RXFIFO_THR_PKT);
+ ao_radio_wake = 0;
ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
ao_radio_strobe(CC1120_SRX);
cli();
- while (!ao_radio_done && !ao_radio_abort)
- ao_sleep(&ao_radio_done);
+ for (;;) {
+ if (ao_radio_abort)
+ break;
+ if (ao_radio_wake) {
+ marc_status = ao_radio_marc_status();
+ if (marc_status != CC1120_MARC_STATUS1_NO_FAILURE)
+ break;
+ ao_radio_wake = 0;
+ }
+ ao_sleep(&ao_radio_wake);
+ }
sei();
- if (ao_radio_done)
+ if (marc_status != CC1120_MARC_STATUS1_RX_FINISHED)
ao_radio_fifo_read(d, size);
ao_radio_put();
- return 0;
+ return marc_status == CC1120_MARC_STATUS1_RX_FINISHED;
}
+/*
+ * Packet deviation is 20.5kHz
+ *
+ * fdev = fosc >> 24 * (256 + dev_m) << dev_e
+ *
+ * 32e6Hz / (2 ** 24) * (256 + 80) * (2 ** 5) = 20508Hz
+ */
+
+#define PACKET_DEV_E 5
+#define PACKET_DEV_M 80
+
+/*
+ * For our packet data, set the symbol rate to 38360 Baud
+ *
+ * (2**20 - DATARATE_M) * 2 ** DATARATE_E
+ * Rdata = -------------------------------------- * fosc
+ * 2 ** 39
+ *
+ * DATARATE_M = 405002
+ * DATARATE_E = 10
+ *
+ * To make the tone last for 200ms, we need 2000 * .2 = 400 bits or 50 bytes
+ */
+#define PACKET_DRATE_E 10
+#define PACKET_DRATE_M 405002
+
static const uint16_t packet_setup[] = {
+ CC1120_DEVIATION_M, PACKET_DEV_M,
+ CC1120_MODCFG_DEV_E, ((CC1120_MODCFG_DEV_E_MODEM_MODE_NORMAL << CC1120_MODCFG_DEV_E_MODEM_MODE) |
+ (CC1120_MODCFG_DEV_E_MOD_FORMAT_2_GFSK << CC1120_MODCFG_DEV_E_MOD_FORMAT) |
+ (PACKET_DEV_E << CC1120_MODCFG_DEV_E_DEV_E)),
+ CC1120_DRATE2, ((PACKET_DRATE_E << CC1120_DRATE2_DATARATE_E) |
+ (((PACKET_DRATE_M >> 16) & CC1120_DRATE2_DATARATE_M_19_16_MASK) << CC1120_DRATE2_DATARATE_M_19_16)),
+ CC1120_DRATE1, ((PACKET_DRATE_M >> 8) & 0xff),
+ CC1120_DRATE0, ((PACKET_DRATE_M >> 0) & 0xff),
+ CC1120_PKT_CFG2, ((CC1120_PKT_CFG2_CCA_MODE_ALWAYS_CLEAR << CC1120_PKT_CFG2_CCA_MODE) |
+ (CC1120_PKT_CFG2_PKT_FORMAT_NORMAL << CC1120_PKT_CFG2_PKT_FORMAT)),
+ CC1120_PKT_CFG1, ((1 << CC1120_PKT_CFG1_WHITE_DATA) |
+ (CC1120_PKT_CFG1_ADDR_CHECK_CFG_NONE << CC1120_PKT_CFG1_ADDR_CHECK_CFG) |
+ (CC1120_PKT_CFG1_CRC_CFG_DISABLED << CC1120_PKT_CFG1_CRC_CFG) |
+ (1 << CC1120_PKT_CFG1_APPEND_STATUS)),
};
void
if ((state >> CC1120_STATUS_STATE) == CC1120_STATUS_STATE_IDLE)
break;
}
+ ao_radio_strobe(CC1120_SFTX);
+ ao_radio_strobe(CC1120_SFRX);
}
static const uint16_t radio_setup[] = {
ao_radio_isr(void)
{
ao_exti_disable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
- ao_radio_done = 1;
- ao_wakeup(&ao_radio_done);
+ ao_radio_wake = 1;
+ ao_wakeup(&ao_radio_wake);
}
static void
{
int i;
+ ao_radio_strobe(CC1120_SRES);
+
for (i = 0; i < sizeof (radio_setup) / sizeof (radio_setup[0]); i += 2)
ao_radio_reg_write(radio_setup[i], radio_setup[i+1]);
- /* Disable GPIO2 pin (radio_int) */
- ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_HIGHZ);
+ /* Enable marc status interrupt on gpio 2 pin */
+ ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_MARC_MCU_WAKEUP);
/* Enable the EXTI interrupt for the appropriate pin */
ao_enable_port(AO_CC1120_INT_PORT);
- ao_exti_setup(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN, AO_EXTI_MODE_RISING, ao_radio_isr);
+ ao_exti_setup(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN, AO_EXTI_MODE_FALLING, ao_radio_isr);
ao_radio_set_packet();
ao_radio_configured = 1;
printf ("Status: %02x\n", status);
printf ("CHIP_RDY: %d\n", (status >> CC1120_STATUS_CHIP_RDY) & 1);
printf ("STATE: %s\n", cc1120_state_name[(status >> CC1120_STATUS_STATE) & CC1120_STATUS_STATE_MASK]);
+ printf ("MARC: %02x\n", ao_radio_marc_status());
for (i = 0; i < AO_NUM_CC1120_REG; i++)
printf ("\t%02x %-20.20s\n", ao_radio_reg_read(ao_cc1120_reg[i].addr), ao_cc1120_reg[i].name);
ao_radio_put();
}
+
+static void ao_radio_beep(void) {
+ ao_radio_rdf(120);
+}
+
#endif
static const struct ao_cmds ao_radio_cmds[] = {
{ ao_radio_test, "C <1 start, 0 stop, none both>\0Radio carrier test" },
#if CC1120_DEBUG
{ ao_radio_show, "R\0Show CC1120 status" },
+ { ao_radio_beep, "B\0Emit an RDF beacon" },
#endif
{ 0, NULL }
};
#define CC1120_SYNC1 0x06
#define CC1120_SYNC0 0x07
#define CC1120_SYNC_CFG1 0x08
+#define CC1120_SYNC_CFG1_DEM_CFG 5
+#define CC1120_SYNC_CFG1_DEM_CFG_PQT_GATING_DISABLED 0
+#define CC1120_SYNC_CFG1_DEM_CFG_PQT_GATING_ENABLED 2
+#define CC1120_SYNC_CFG1_DEM_CFG_MASK 0x7
+
+#define CC1120_SYNC_CFG1_SYNC_THR 0
+#define CC1120_SYNC_CFG1_SYNC_MASK 0x1f
+
#define CC1120_SYNC_CFG0 0x09
+#define CC1120_SYNC_CFG0_SYNC_MODE 2
+#define CC1120_SYNC_CFG0_SYNC_MODE_NONE 0
+#define CC1120_SYNC_CFG0_SYNC_MODE_11_BITS 1
+#define CC1120_SYNC_CFG0_SYNC_MODE_16_BITS 2
+#define CC1120_SYNC_CFG0_SYNC_MODE_18_BITS 3
+#define CC1120_SYNC_CFG0_SYNC_MODE_24_BITS 4
+#define CC1120_SYNC_CFG0_SYNC_MODE_32_BITS 5
+#define CC1120_SYNC_CFG0_SYNC_MODE_16H_BITS 6
+#define CC1120_SYNC_CFG0_SYNC_MODE_16D_BITS 7
+#define CC1120_SYNC_CFG0_SYNC_MODE_MASK 7
+#define CC1120_SYNC_CFG0_SYNC_NUM_ERROR 0
+#define CC1120_SYNC_CFG0_SYNC_NUM_ERROR_0 0
+#define CC1120_SYNC_CFG0_SYNC_NUM_ERROR_2 1
+#define CC1120_SYNC_CFG0_SYNC_NUM_ERROR_DISABLED 3
+#define CC1120_SYNC_CFG0_SYNC_NUM_ERROR_MASK 3
+
#define CC1120_DEVIATION_M 0x0a
#define CC1120_MODCFG_DEV_E 0x0b
+#define CC1120_MODCFG_DEV_E_MODEM_MODE 6
+#define CC1120_MODCFG_DEV_E_MODEM_MODE_NORMAL 0
+#define CC1120_MODCFG_DEV_E_MODEM_MODE_DSSS_REPEAT 1
+#define CC1120_MODCFG_DEV_E_MODEM_MODE_DSSS_PN 2
+#define CC1120_MODCFG_DEV_E_MODEM_MODE_MASK 3
+#define CC1120_MODCFG_DEV_E_MOD_FORMAT 3
+#define CC1120_MODCFG_DEV_E_MOD_FORMAT_2_FSK 0
+#define CC1120_MODCFG_DEV_E_MOD_FORMAT_2_GFSK 1
+#define CC1120_MODCFG_DEV_E_MOD_FORMAT_ASK_OOK 3
+#define CC1120_MODCFG_DEV_E_MOD_FORMAT_4_FSK 4
+#define CC1120_MODCFG_DEV_E_MOD_FORMAT_4_GFSK 5
+#define CC1120_MODCFG_DEV_E_MOD_FORMAT_SC_MSK_UNSHAPED 6
+#define CC1120_MODCFG_DEV_E_MOD_FORMAT_SC_MSK_SHAPED 7
+#define CC1120_MODCFG_DEV_E_MOD_FORMAT_MASK 7
+#define CC1120_MODCFG_DEV_E_DEV_E 0
+#define CC1120_MODCFG_DEV_E_DEV_E_MASK 7
+
#define CC1120_DCFILT_CFG 0x0c
#define CC1120_PREAMBLE_CFG1 0x0d
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE 2
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_NONE 0
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_0_5_BYTE 1
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_1_BYTE 2
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_1_5_BYTE 3
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_2_BYTES 4
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_3_BYTES 5
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_4_BYTES 6
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_5_BYTES 7
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_6_BYTES 8
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_7_BYTES 9
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_8_BYTES 10
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_12_BYTES 11
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_24_BYTES 12
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_30_BYTES 13
+#define CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_MASK 0xf
+
+#define CC1120_PREAMBLE_CFG1_PREAMBLE_WORD 0
+#define CC1120_PREAMBLE_CFG1_PREAMBLE_WORD_AA 0
+#define CC1120_PREAMBLE_CFG1_PREAMBLE_WORD_55 1
+#define CC1120_PREAMBLE_CFG1_PREAMBLE_WORD_33 2
+#define CC1120_PREAMBLE_CFG1_PREAMBLE_WORD_CC 3
+#define CC1120_PREAMBLE_CFG1_PREAMBLE_WORD_MASK 3
+
#define CC1120_PREAMBLE_CFG0 0x0e
#define CC1120_FREQ_IF_CFG 0x0f
#define CC1120_IQIC 0x10
#define CC1120_CHAN_BW 0x11
#define CC1120_MDMCFG1 0x12
+#define CC1120_MDMCFG1_CARRIER_SENSE_GATE 7
+#define CC1120_MDMCFG1_FIFO_EN 6
+#define CC1120_MDMCFG1_MANCHESTER_EN 5
+#define CC1120_MDMCFG1_INVERT_DATA_EN 4
+#define CC1120_MDMCFG1_COLLISION_DETECT_EN 3
+#define CC1120_MDMCFG1_DVGA_GAIN 1
+#define CC1120_MDMCFG1_DVGA_GAIN_0 0
+#define CC1120_MDMCFG1_DVGA_GAIN_3 1
+#define CC1120_MDMCFG1_DVGA_GAIN_6 2
+#define CC1120_MDMCFG1_DVGA_GAIN_9 3
+#define CC1120_MDMCFG1_DVGA_GAIN_MASK 3
+#define CC1120_MDMCFG1_SINGLE_ADC_EN 0
+
#define CC1120_MDMCFG0 0x13
#define CC1120_DRATE2 0x14
+#define CC1120_DRATE2_DATARATE_E 4
+#define CC1120_DRATE2_DATARATE_E_MASK 0xf
+#define CC1120_DRATE2_DATARATE_M_19_16 0
+#define CC1120_DRATE2_DATARATE_M_19_16_MASK 0xf
+
#define CC1120_DRATE1 0x15
#define CC1120_DRATE0 0x16
#define CC1120_AGC_REF 0x17
#define CC1120_FIFO_CFG 0x1e
#define CC1120_DEV_ADDR 0x1f
#define CC1120_SETTLING_CFG 0x20
+#define CC1120_SETTLING_CFG_FS_AUTOCAL 3
+#define CC1120_SETTLING_CFG_FS_AUTOCAL_NEVER 0
+#define CC1120_SETTLING_CFG_FS_AUTOCAL_IDLE_TO_ON 1
+#define CC1120_SETTLING_CFG_FS_AUTOCAL_ON_TO_IDLE 2
+#define CC1120_SETTLING_CFG_FS_AUTOCAL_EVERY_4TH_TIME 3
+#define CC1120_SETTLING_CFG_FS_AUTOCAL_MASK 3
+#define CC1120_SETTLING_CFG_LOCK_TIME 1
+#define CC1120_SETTLING_CFG_LOCK_TIME_50_20 0
+#define CC1120_SETTLING_CFG_LOCK_TIME_70_30 1
+#define CC1120_SETTLING_CFG_LOCK_TIME_100_40 2
+#define CC1120_SETTLING_CFG_LOCK_TIME_150_60 3
+#define CC1120_SETTLING_CFG_LOCK_TIME_MASK 3
+#define CC1120_SETTLING_CFG_FSREG_TIME 0
+#define CC1120_SETTLING_CFG_FSREG_TIME_30 0
+#define CC1120_SETTLING_CFG_FSREG_TIME_60 1
+#define CC1120_SETTLING_CFG_FSREG_TIME_MASK 1
+
#define CC1120_FS_CFG 0x21
+#define CC1120_FS_CFG_LOCK_EN 4
+#define CC1120_FS_CFG_FSD_BANDSELECT 0
+#define CC1120_FS_CFG_FSD_BANDSELECT_820_960 2
+#define CC1120_FS_CFG_FSD_BANDSELECT_410_480 4
+#define CC1120_FS_CFG_FSD_BANDSELECT_273_320 6
+#define CC1120_FS_CFG_FSD_BANDSELECT_205_240 8
+#define CC1120_FS_CFG_FSD_BANDSELECT_164_192 10
+#define CC1120_FS_CFG_FSD_BANDSELECT_136_160 11
+#define CC1120_FS_CFG_FSD_BANDSELECT_MASK 0xf
+
#define CC1120_WOR_CFG1 0x22
#define CC1120_WOR_CFG0 0x23
#define CC1120_WOR_EVENT0_MSB 0x24
#define CC1120_WOR_EVENT0_LSB 0x25
#define CC1120_PKT_CFG2 0x26
+#define CC1120_PKT_CFG2_CCA_MODE 2
+#define CC1120_PKT_CFG2_CCA_MODE_ALWAYS_CLEAR 0
+#define CC1120_PKT_CFG2_CCA_MODE_RSSI_THRESHOLD 1
+#define CC1120_PKT_CFG2_CCA_MODE_NOT_RECEIVING 2
+#define CC1120_PKT_CFG2_CCA_MODE_RSSI_OR_NOT 3
+#define CC1120_PKT_CFG2_CCA_MODE_RSSI_AND_ETSI_LBT 4
+#define CC1120_PKT_CFG2_CCA_MODE_MASK 7
+#define CC1120_PKT_CFG2_PKT_FORMAT 0
+#define CC1120_PKT_CFG2_PKT_FORMAT_NORMAL 0
+#define CC1120_PKT_CFG2_PKT_FORMAT_SYNCHRONOUS_SERIAL 1
+#define CC1120_PKT_CFG2_PKT_FORMAT_RANDOM 2
+#define CC1120_PKT_CFG2_PKT_FORMAT_TRANSPARENT_SERIAL 3
+#define CC1120_PKT_CFG2_PKT_FORMAT_MASK 3
+
#define CC1120_PKT_CFG1 0x27
+#define CC1120_PKT_CFG1_WHITE_DATA 6
+#define CC1120_PKT_CFG1_ADDR_CHECK_CFG 4
+#define CC1120_PKT_CFG1_ADDR_CHECK_CFG_NONE 0
+#define CC1120_PKT_CFG1_ADDR_CHECK_CFG_CHECK 1
+#define CC1120_PKT_CFG1_ADDR_CHECK_CFG_00_BROADCAST 2
+#define CC1120_PKT_CFG1_ADDR_CHECK_CFG_00_FF_BROADCAST 3
+#define CC1120_PKT_CFG1_ADDR_CHECK_CFG_MASK 3
+#define CC1120_PKT_CFG1_CRC_CFG 2
+#define CC1120_PKT_CFG1_CRC_CFG_DISABLED 0
+#define CC1120_PKT_CFG1_CRC_CFG_CRC16_INIT_ONES 1
+#define CC1120_PKT_CFG1_CRC_CFG_CRC16_INIT_ZEROS 2
+#define CC1120_PKT_CFG1_CRC_CFG_MASK 3
+#define CC1120_PKT_CFG1_BYTE_SWAP_EN 1
+#define CC1120_PKT_CFG1_APPEND_STATUS 0
+
#define CC1120_PKT_CFG0 0x28
+#define CC1120_PKT_CFG0_LENGTH_CONFIG 5
+#define CC1120_PKT_CFG0_LENGTH_CONFIG_FIXED 0
+#define CC1120_PKT_CFG0_LENGTH_CONFIG_VARIABLE 1
+#define CC1120_PKT_CFG0_LENGTH_CONFIG_INFINITE 2
+#define CC1120_PKT_CFG0_LENGTH_CONFIG_VARIABLE_5LSB 3
+#define CC1120_PKT_CFG0_LENGTH_CONFIG_MASK 3
+#define CC1120_PKT_CFG0_PKG_BIT_LEN 2
+#define CC1120_PKT_CFG0_PKG_BIT_LEN_MASK 7
+#define CC1120_PKT_CFG0_UART_MODE_EN 1
+#define CC1120_PKT_CFG0_UART_SWAP_EN 0
+
#define CC1120_RFEND_CFG1 0x29
#define CC1120_RFEND_CFG0 0x2a
#define CC1120_PA_CFG2 0x2b
#define CC1120_RX_STATUS (CC1120_EXTENDED_BIT | 0x92)
#define CC1120_TX_STATUS (CC1120_EXTENDED_BIT | 0x93)
#define CC1120_MARC_STATUS1 (CC1120_EXTENDED_BIT | 0x94)
+# define CC1120_MARC_STATUS1_NO_FAILURE 0
+# define CC1120_MARC_STATUS1_RX_TIMEOUT 1
+# define CC1120_MARC_STATUS1_RX_TERMINATION 2
+# define CC1120_MARC_STATUS1_EWOR_SYNC_LOST 3
+# define CC1120_MARC_STATUS1_MAXIMUM_LENGTH 4
+# define CC1120_MARC_STATUS1_ADDRESS 5
+# define CC1120_MARC_STATUS1_CRC 6
+# define CC1120_MARC_STATUS1_TX_FIFO_OVERFLOW 7
+# define CC1120_MARC_STATUS1_TX_FIFO_UNDERFLOW 8
+# define CC1120_MARC_STATUS1_RX_FIFO_OVERFLOW 9
+# define CC1120_MARC_STATUS1_RX_FIFO_UNDERFLOW 10
+# define CC1120_MARC_STATUS1_TX_ON_CCA_FAILED 11
+# define CC1120_MARC_STATUS1_TX_FINISHED 0x40
+# define CC1120_MARC_STATUS1_RX_FINISHED 0x80
#define CC1120_MARC_STATUS0 (CC1120_EXTENDED_BIT | 0x95)
#define CC1120_PA_IFAMP_TEST (CC1120_EXTENDED_BIT | 0x96)
#define CC1120_FSRF_TEST (CC1120_EXTENDED_BIT | 0x97)
*\r
***************************************************************/\r
\r
-\r
CC1120_SYNC3, 0x93, /* Sync Word Configuration [31:24] */\r
CC1120_SYNC2, 0x0b, /* Sync Word Configuration [23:16] */\r
CC1120_SYNC1, 0x51, /* Sync Word Configuration [15:8] */\r
CC1120_SYNC0, 0xde, /* Sync Word Configuration [7:0] */\r
CC1120_SYNC_CFG1, 0x08, /* Sync Word Detection Configuration */\r
CC1120_SYNC_CFG0, 0x17, /* Sync Word Length Configuration */\r
+#if 0\r
CC1120_DEVIATION_M, 0x50, /* Frequency Deviation Configuration */\r
CC1120_MODCFG_DEV_E, 0x0d, /* Modulation Format and Frequency Deviation Configuration */\r
+#endif\r
CC1120_DCFILT_CFG, 0x1c, /* Digital DC Removal Configuration */\r
CC1120_PREAMBLE_CFG1, 0x18, /* Preamble Length Configuration */\r
CC1120_PREAMBLE_CFG0, 0x2a, /* */\r
CC1120_CHAN_BW, 0x02, /* Channel Filter Configuration */\r
CC1120_MDMCFG1, 0x46, /* General Modem Parameter Configuration */\r
CC1120_MDMCFG0, 0x05, /* General Modem Parameter Configuration */\r
+#if 0\r
CC1120_DRATE2, 0x93, /* Data Rate Configuration Exponent and Mantissa [19:16] */\r
CC1120_DRATE1, 0xa4, /* Data Rate Configuration Mantissa [15:8] */\r
CC1120_DRATE0, 0x00, /* Data Rate Configuration Mantissa [7:0] */\r
+#endif\r
CC1120_AGC_REF, 0x20, /* AGC Reference Level Configuration */\r
CC1120_AGC_CS_THR, 0x19, /* Carrier Sense Threshold Configuration */\r
CC1120_AGC_GAIN_ADJUST, 0x00, /* RSSI Offset Configuration */\r
CC1120_AGC_CFG0, 0xcf, /* AGC Configuration */\r
CC1120_FIFO_CFG, 0x00, /* FIFO Configuration */\r
CC1120_DEV_ADDR, 0x00, /* Device Address Configuration */\r
- CC1120_SETTLING_CFG, 0x03, /* Frequency Synthesizer Calibration and Settling Configuration */\r
- CC1120_FS_CFG, 0x14, /* Frequency Synthesizer Configuration */\r
+ CC1120_SETTLING_CFG, /* Frequency Synthesizer Calibration and Settling Configuration */\r
+ (CC1120_SETTLING_CFG_FS_AUTOCAL_IDLE_TO_ON << CC1120_SETTLING_CFG_FS_AUTOCAL) |\r
+ (CC1120_SETTLING_CFG_LOCK_TIME_50_20 << CC1120_SETTLING_CFG_LOCK_TIME) |\r
+ (CC1120_SETTLING_CFG_FSREG_TIME_60 << CC1120_SETTLING_CFG_FSREG_TIME),\r
+ CC1120_FS_CFG, /* Frequency Synthesizer Configuration */\r
+ (1 << CC1120_FS_CFG_LOCK_EN) |\r
+ (CC1120_FS_CFG_FSD_BANDSELECT_410_480 << CC1120_FS_CFG_FSD_BANDSELECT),\r
CC1120_WOR_CFG1, 0x08, /* eWOR Configuration, Reg 1 */\r
CC1120_WOR_CFG0, 0x21, /* eWOR Configuration, Reg 0 */\r
CC1120_WOR_EVENT0_MSB, 0x00, /* Event 0 Configuration */\r
CC1120_WOR_EVENT0_LSB, 0x00, /* Event 0 Configuration */\r
+#if 0\r
CC1120_PKT_CFG2, 0x04, /* Packet Configuration, Reg 2 */\r
CC1120_PKT_CFG1, 0x45, /* Packet Configuration, Reg 1 */\r
+#endif\r
CC1120_PKT_CFG0, 0x20, /* Packet Configuration, Reg 0 */\r
CC1120_RFEND_CFG1, 0x0f, /* RFEND Configuration, Reg 1 */\r
CC1120_RFEND_CFG0, 0x00, /* RFEND Configuration, Reg 0 */\r
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