Adjust clock/data phase for spi test

diff --git a/target/ee/ee.c b/target/ee/ee.c
index 221d597939a54c569a95c9a15b361dfdc2f949c2..83dd57ebf32636fc96acc3336dafb06e0afe42ed 100644 (file)
--- a/target/ee/ee.c
+++ b/target/ee/ee.c
@@ -73,6 +73,7 @@ delay (unsigned char n)
 void
 cs(uint8_t b)
 {
 void
 cs(uint8_t b)
 {

+       SCK = 0;

        CS = b;
        delay(1);
 }
        CS = b;
        delay(1);
 }


@@ -81,10 +82,10 @@ void
 out_bit(uint8_t b)
 {
        MOSI = b;
 out_bit(uint8_t b)
 {
        MOSI = b;

+       delay(1);

        SCK = 1;
        delay(1);
        SCK = 0;
        SCK = 1;
        delay(1);
        SCK = 0;

-       delay(1);

 }
 
 void
 }
 
 void


@@ -103,11 +104,12 @@ uint8_t
 in_bit(void)
 {
        uint8_t b;
 in_bit(void)
 {
        uint8_t b;

+       
+       delay(1);

        SCK = 1;
        delay(1);
        b = MISO;
        SCK = 0;
        SCK = 1;
        delay(1);
        b = MISO;
        SCK = 0;

-       delay(1);

        return b;
 }
 
        return b;
 }