X-Git-Url: https://git.gag.com/?p=fw%2Faltos;a=blobdiff_plain;f=target%2Ftimer%2Fcc1111.h;fp=target%2Ftimer%2Fcc1111.h;h=76c95c2747a18351160a19b7cb1721f072c193d2;hp=7a531cc0a04e3ef080c00875079d7b96f36520a7;hb=17d2432a8b9c15963cd3b821f025ad33972ef477;hpb=8a9a3f02b951382573ff74dd6ce5a1c0f335fa86 diff --git a/target/timer/cc1111.h b/target/timer/cc1111.h index 7a531cc0..76c95c27 100644 --- a/target/timer/cc1111.h +++ b/target/timer/cc1111.h @@ -2,23 +2,23 @@ Register Declarations for the ChipCon CC1111 Processor Range Copyright © 2008 Keith Packard - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. Adapted from the Cygnal C8051F12x config file which is: - + Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl This library is free software; you can redistribute it and/or @@ -135,37 +135,37 @@ sfr at 0xDD T1CC1H ; /* */ sfr at 0xDE T1CC2L ; /* */ sfr at 0xDF T1CC2H ; /* */ sfr at 0xE0 ACC ; /* ACCUMULATOR */ -sfr at 0xE1 RFST ; /* */ -sfr at 0xE2 T1CNTL ; /* */ -sfr at 0xE3 T1CNTH ; /* */ -sfr at 0xE4 T1CTL ; /* */ -sfr at 0xE5 T1CCTL0 ; /* */ -sfr at 0xE6 T1CCTL1 ; /* */ -sfr at 0xE7 T1CCTL2 ; /* */ -sfr at 0xE8 IRCON2 ; /* */ -sfr at 0xE9 RFIF ; /* */ -sfr at 0xEA T4CNT ; /* */ -sfr at 0xEB T4CTL ; /* */ -sfr at 0xEC T4CCTL0 ; /* */ -sfr at 0xED T4CC0 ; /* */ -sfr at 0xEE T4CCTL1 ; /* */ -sfr at 0xEF T4CC1 ; /* */ -sfr at 0xF0 B ; /* */ -sfr at 0xF1 PERCFG ; /* */ -sfr at 0xF2 ADCCFG ; /* */ -sfr at 0xF3 P0SEL ; /* */ -sfr at 0xF4 P1SEL ; /* */ -sfr at 0xF5 P2SEL ; /* */ -sfr at 0xF6 P1INP ; /* */ -sfr at 0xF7 P2INP ; /* */ -sfr at 0xF8 U1CSR ; /* */ -sfr at 0xF9 U1DBUF ; /* */ -sfr at 0xFA U1BAUD ; /* */ -sfr at 0xFB U1UCR ; /* */ -sfr at 0xFC U1GCR ; /* */ -sfr at 0xFD P0DIR ; /* */ -sfr at 0xFE P1DIR ; /* */ -sfr at 0xFF P2DIR ; /* */ +sfr at 0xE1 RFST ; /* */ +sfr at 0xE2 T1CNTL ; /* */ +sfr at 0xE3 T1CNTH ; /* */ +sfr at 0xE4 T1CTL ; /* */ +sfr at 0xE5 T1CCTL0 ; /* */ +sfr at 0xE6 T1CCTL1 ; /* */ +sfr at 0xE7 T1CCTL2 ; /* */ +sfr at 0xE8 IRCON2 ; /* */ +sfr at 0xE9 RFIF ; /* */ +sfr at 0xEA T4CNT ; /* */ +sfr at 0xEB T4CTL ; /* */ +sfr at 0xEC T4CCTL0 ; /* */ +sfr at 0xED T4CC0 ; /* */ +sfr at 0xEE T4CCTL1 ; /* */ +sfr at 0xEF T4CC1 ; /* */ +sfr at 0xF0 B ; /* */ +sfr at 0xF1 PERCFG ; /* */ +sfr at 0xF2 ADCCFG ; /* */ +sfr at 0xF3 P0SEL ; /* */ +sfr at 0xF4 P1SEL ; /* */ +sfr at 0xF5 P2SEL ; /* */ +sfr at 0xF6 P1INP ; /* */ +sfr at 0xF7 P2INP ; /* */ +sfr at 0xF8 U1CSR ; /* */ +sfr at 0xF9 U1DBUF ; /* */ +sfr at 0xFA U1BAUD ; /* */ +sfr at 0xFB U1UCR ; /* */ +sfr at 0xFC U1GCR ; /* */ +sfr at 0xFD P0DIR ; /* */ +sfr at 0xFE P1DIR ; /* */ +sfr at 0xFF P2DIR ; /* */ /* BIT Registers */