X-Git-Url: https://git.gag.com/?p=fw%2Faltos;a=blobdiff_plain;f=src%2Fstmf0%2Fstm32f0.h;h=d528e492127657f4bf5de4d6d85e860e8fe8c05e;hp=32864ced9f63ca1e1836d00171399178c14b91a3;hb=1667cb8e8b702b05fc3ec39ee49029885df64a4a;hpb=79f3434013650fe4e3d76e5eb56a10000ee34249 diff --git a/src/stmf0/stm32f0.h b/src/stmf0/stm32f0.h index 32864ced..d528e492 100644 --- a/src/stmf0/stm32f0.h +++ b/src/stmf0/stm32f0.h @@ -3,7 +3,8 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of @@ -23,6 +24,7 @@ typedef volatile uint32_t vuint32_t; typedef volatile void * vvoid_t; typedef volatile uint16_t vuint16_t; +typedef volatile uint8_t vuint8_t; struct stm_gpio { vuint32_t moder; @@ -474,6 +476,24 @@ extern struct stm_rcc stm_rcc; #define STM_RCC_CR2_HSI14RDY 1 #define STM_RCC_CR2_HSI14ON 0 +#define STM_RCC_CFGR2_PREDIV 0 +#define STM_RCC_CFGR2_PREDIV_1 0x0 +#define STM_RCC_CFGR2_PREDIV_2 0x1 +#define STM_RCC_CFGR2_PREDIV_3 0x2 +#define STM_RCC_CFGR2_PREDIV_4 0x3 +#define STM_RCC_CFGR2_PREDIV_5 0x4 +#define STM_RCC_CFGR2_PREDIV_6 0x5 +#define STM_RCC_CFGR2_PREDIV_7 0x6 +#define STM_RCC_CFGR2_PREDIV_8 0x7 +#define STM_RCC_CFGR2_PREDIV_9 0x8 +#define STM_RCC_CFGR2_PREDIV_10 0x9 +#define STM_RCC_CFGR2_PREDIV_11 0xa +#define STM_RCC_CFGR2_PREDIV_12 0xb +#define STM_RCC_CFGR2_PREDIV_13 0xc +#define STM_RCC_CFGR2_PREDIV_14 0xd +#define STM_RCC_CFGR2_PREDIV_15 0xe +#define STM_RCC_CFGR2_PREDIV_16 0xf + #define STM_RCC_CFGR3_USART3SW 18 #define STM_RCC_CFGR3_USART2SW 16 #define STM_RCC_CFGR3_ADCSW 8 @@ -568,6 +588,37 @@ extern struct stm_pwr stm_pwr; #define STM_PWR_CSR_SBF (1) #define STM_PWR_CSR_WUF (0) +struct stm_crc { + union { + vuint32_t u32; + vuint16_t u16; + vuint8_t u8; + } dr; + vuint32_t idr; + vuint32_t cr; + uint32_t _0c; + + vuint32_t init; + vuint32_t pol; +}; + +extern struct stm_crc stm_crc; + +#define stm_crc (*((struct stm_crc *) 0x40023000)) + +#define STM_CRC_CR_REV_OUT 7 +#define STM_CRC_CR_REV_IN 5 +#define STM_CRC_CR_REV_IN_NONE 0 +#define STM_CRC_CR_REV_IN_BY_BYTE 1 +#define STM_CRC_CR_REV_IN_BY_HALF_WORD 2 +#define STM_CRC_CR_REV_IN_BY_WORD 3 +#define STM_CRC_CR_POLYSIZE 3 +#define STM_CRC_CR_POLYSIZE_32 0 +#define STM_CRC_CR_POLYSIZE_16 1 +#define STM_CRC_CR_POLYSIZE_8 2 +#define STM_CRC_CR_POLYSIZE_7 3 +#define STM_CRC_CR_RESET 0 + /* The SYSTICK starts at 0xe000e010 */ struct stm_systick { @@ -763,7 +814,7 @@ isr(tim7) #define STM_ISR_TSC_POS 8 #define STM_ISR_DMA_CH1_POS 9 #define STM_ISR_DMA_CH2_3_DMA2_CH1_2_POS 10 -#define STM_ISR_DMA_CH44_5_6_7_DMA2_CH3_4_5_POS 11 +#define STM_ISR_DMA_CH4_5_6_7_DMA2_CH3_4_5_POS 11 #define STM_ISR_ADC_COMP_POS 12 #define STM_ISR_TIM1_BRK_UP_TRG_COM_POS 13 #define STM_ISR_TIM1_CC_POS 14 @@ -787,8 +838,11 @@ isr(tim7) struct stm_syscfg { vuint32_t cfgr1; + uint32_t reserved_04; vuint32_t exticr[4]; vuint32_t cfgr2; + uint8_t reserved_1c[0x80-0x1c]; + vuint32_t itline[31]; }; extern struct stm_syscfg stm_syscfg; @@ -826,7 +880,13 @@ extern struct stm_syscfg stm_syscfg; #define STM_SYSCFG_CFGR1_MEM_MODE_SRAM 3 #define STM_SYSCFG_CFGR1_MEM_MODE_MASK 3 -#if 0 +#define STM_SYSCFG_EXTICR_PA 0 +#define STM_SYSCFG_EXTICR_PB 1 +#define STM_SYSCFG_EXTICR_PC 2 +#define STM_SYSCFG_EXTICR_PD 3 +#define STM_SYSCFG_EXTICR_PE 4 +#define STM_SYSCFG_EXTICR_PF 5 + static inline void stm_exticr_set(struct stm_gpio *gpio, int pin) { uint8_t reg = pin >> 2; @@ -847,8 +907,6 @@ stm_exticr_set(struct stm_gpio *gpio, int pin) { stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift; } -#endif - struct stm_dma_channel { vuint32_t ccr; @@ -858,7 +916,7 @@ struct stm_dma_channel { vuint32_t reserved; }; -#define STM_NUM_DMA 6 +#define STM_NUM_DMA 5 struct stm_dma { vuint32_t isr; @@ -868,7 +926,7 @@ struct stm_dma { extern struct stm_dma stm_dma; -/* DMA channels go from 1 to 6, instead of 0 to 5 (sigh) +/* DMA channels go from 1 to 5, instead of 0 to 4 (sigh) */ #define STM_DMA_INDEX(channel) ((channel) - 1) @@ -1010,7 +1068,7 @@ extern struct stm_spi stm_spi1, stm_spi2, stm_spi3; #define STM_SPI_CR1_BIDIOE 14 #define STM_SPI_CR1_CRCEN 13 #define STM_SPI_CR1_CRCNEXT 12 -#define STM_SPI_CR1_DFF 11 +#define STM_SPI_CR1_CRCL 11 #define STM_SPI_CR1_RXONLY 10 #define STM_SPI_CR1_SSM 9 #define STM_SPI_CR1_SSI 8 @@ -1031,17 +1089,43 @@ extern struct stm_spi stm_spi1, stm_spi2, stm_spi3; #define STM_SPI_CR1_CPOL 1 #define STM_SPI_CR1_CPHA 0 +#define STM_SPI_CR2_LDMA_TX 14 +#define STM_SPI_CR2_LDMA_RX 13 +#define STM_SPI_CR2_FRXTH 12 +#define STM_SPI_CR2_DS 8 +#define STM_SPI_CR2_DS_4 0x3 +#define STM_SPI_CR2_DS_5 0x4 +#define STM_SPI_CR2_DS_6 0x5 +#define STM_SPI_CR2_DS_7 0x6 +#define STM_SPI_CR2_DS_8 0x7 +#define STM_SPI_CR2_DS_9 0x8 +#define STM_SPI_CR2_DS_10 0x9 +#define STM_SPI_CR2_DS_11 0xa +#define STM_SPI_CR2_DS_12 0xb +#define STM_SPI_CR2_DS_13 0xc +#define STM_SPI_CR2_DS_14 0xd +#define STM_SPI_CR2_DS_15 0xe +#define STM_SPI_CR2_DS_16 0xf #define STM_SPI_CR2_TXEIE 7 #define STM_SPI_CR2_RXNEIE 6 #define STM_SPI_CR2_ERRIE 5 +#define STM_SPI_CR2_FRF 4 +# define STM_SPI_CR2_FRF_MOTOROLA 0 +# define STM_SPI_CR2_FRF_TI 1 +#define STM_SPI_CR2_NSSP 3 #define STM_SPI_CR2_SSOE 2 #define STM_SPI_CR2_TXDMAEN 1 #define STM_SPI_CR2_RXDMAEN 0 +#define STM_SPI_SR_FTLVL 11 +#define STM_SPI_SR_FRLVL 9 +#define STM_SPI_SR_FRE 8 #define STM_SPI_SR_BSY 7 #define STM_SPI_SR_OVR 6 #define STM_SPI_SR_MODF 5 #define STM_SPI_SR_CRCERR 4 +#define STM_SPI_SR_UDR 3 +#define STM_SPI_SR_CHSIDE 2 #define STM_SPI_SR_TXE 1 #define STM_SPI_SR_RXNE 0 @@ -1261,7 +1345,291 @@ extern struct stm_i2c stm_i2c1, stm_i2c2; #define STM_I2C_CCR_CCR 0 #define STM_I2C_CCR_MASK 0x7ff -struct stm_tim234 { +struct stm_tim1 { + vuint32_t cr1; + vuint32_t cr2; + vuint32_t smcr; + vuint32_t dier; + + vuint32_t sr; + vuint32_t egr; + vuint32_t ccmr1; + vuint32_t ccmr2; + + vuint32_t ccer; + vuint32_t cnt; + vuint32_t psc; + vuint32_t arr; + + vuint32_t rcr; + vuint32_t ccr1; + vuint32_t ccr2; + vuint32_t ccr3; + + vuint32_t ccr4; + vuint32_t bdtr; + vuint32_t dcr; + vuint32_t dmar; +}; + +#define STM_TIM1_CR1_CKD 8 +#define STM_TIM1_CR1_CKD_1 0 +#define STM_TIM1_CR1_CKD_2 1 +#define STM_TIM1_CR1_CKD_4 2 + +#define STM_TIM1_CR1_ARPE 7 + +#define STM_TIM1_CR1_CMS 5 +#define STM_TIM1_CR1_CMS_EDGE 0 +#define STM_TIM1_CR1_CMS_CENTER_1 1 +#define STM_TIM1_CR1_CMS_CENTER_2 2 +#define STM_TIM1_CR1_CMS_CENTER_3 3 + +#define STM_TIM1_CR1_DIR 4 +#define STM_TIM1_CR1_DIR_UP 0 +#define STM_TIM1_CR1_DIR_DOWn 1 +#define STM_TIM1_CR1_OPM 3 +#define STM_TIM1_CR1_URS 2 +#define STM_TIM1_CR1_UDIS 1 +#define STM_TIM1_CR1_CEN 0 + +#define STM_TIM1_CR2_OIS4 14 +#define STM_TIM1_CR2_OIS3N 13 +#define STM_TIM1_CR2_OIS3 12 +#define STM_TIM1_CR2_OIS2N 11 +#define STM_TIM1_CR2_OIS2 10 +#define STM_TIM1_CR2_OIS1N 9 +#define STM_TIM1_CR2_OSI1 8 +#define STM_TIM1_CR2_TI1S 7 +#define STM_TIM1_CR2_MMS 4 +#define STM_TIM1_CR2_MMS_RESET 0 +#define STM_TIM1_CR2_MMS_ENABLE 1 +#define STM_TIM1_CR2_MMS_UPDATE 2 +#define STM_TIM1_CR2_MMS_COMPARE_PULSE 3 +#define STM_TIM1_CR2_MMS_COMPARE_OC1REF 4 +#define STM_TIM1_CR2_MMS_COMPARE_OC2REF 5 +#define STM_TIM1_CR2_MMS_COMPARE_OC3REF 6 +#define STM_TIM1_CR2_MMS_COMPARE_OC4REF 7 +#define STM_TIM1_CR2_CCDS 3 +#define STM_TIM1_CR2_CCUS 2 +#define STM_TIM1_CR2_CCPC 0 + +#define STM_TIM1_SMCR_ETP 15 +#define STM_TIM1_SMCR_ECE 14 +#define STM_TIM1_SMCR_ETPS 12 +#define STM_TIM1_SMCR_ETPS_OFF 0 +#define STM_TIM1_SMCR_ETPS_DIV_2 1 +#define STM_TIM1_SMCR_ETPS_DIV_4 2 +#define STM_TIM1_SMCR_ETPS_DIV_8 3 + +#define STM_TIM1_SMCR_ETF 8 +#define STM_TIM1_SMCR_ETF_NONE 0 +#define STM_TIM1_SMCR_ETF_DIV_1_N_2 1 +#define STM_TIM1_SMCR_ETF_DIV_1_N_4 2 +#define STM_TIM1_SMCR_ETF_DIV_1_N_8 3 +#define STM_TIM1_SMCR_ETF_DIV_2_N_6 4 +#define STM_TIM1_SMCR_ETF_DIV_2_N_8 5 +#define STM_TIM1_SMCR_ETF_DIV_4_N_6 6 +#define STM_TIM1_SMCR_ETF_DIV_4_N_8 7 +#define STM_TIM1_SMCR_ETF_DIV_8_N_6 8 +#define STM_TIM1_SMCR_ETF_DIV_8_N_8 9 +#define STM_TIM1_SMCR_ETF_DIV_16_N_5 10 +#define STM_TIM1_SMCR_ETF_DIV_16_N_6 11 +#define STM_TIM1_SMCR_ETF_DIV_16_N_8 12 +#define STM_TIM1_SMCR_ETF_DIV_32_N_5 13 +#define STM_TIM1_SMCR_ETF_DIV_32_N_6 14 +#define STM_TIM1_SMCR_ETF_DIV_32_N_8 15 + +#define STM_TIM1_SMCR_MSM 7 +#define STM_TIM1_SMCR_TS 4 +#define STM_TIM1_SMCR_TS_ITR0 0 +#define STM_TIM1_SMCR_TS_ITR1 1 +#define STM_TIM1_SMCR_TS_ITR2 2 +#define STM_TIM1_SMCR_TS_ITR3 3 +#define STM_TIM1_SMCR_TS_TI1F_ED 4 +#define STM_TIM1_SMCR_TS_TI1FP1 5 +#define STM_TIM1_SMCR_TS_TI2FP2 6 +#define STM_TIM1_SMCR_TS_ETRF 7 + +#define STM_TIM1_SMCR_OCCS 3 +#define STM_TIM1_SMCR_SMS 0 +#define STM_TIM1_SMCR_SMS_DISABLE 0 +#define STM_TIM1_SMCR_SMS_ENCODER_1 1 +#define STM_TIM1_SMCR_SMS_ENCODER_2 2 +#define STM_TIM1_SMCR_SMS_ENCODER_3 3 +#define STM_TIM1_SMCR_SMS_RESET 4 +#define STM_TIM1_SMCR_SMS_GATED 5 +#define STM_TIM1_SMCR_SMS_TRIGGER 6 +#define STM_TIM1_SMCR_SMS_EXTERNAL 7 + +#define STM_TIM1_DIER_TDE 14 +#define STM_TIM1_DIER_COMDE 13 +#define STM_TIM1_DIER_CC4DE 12 +#define STM_TIM1_DIER_CC3DE 11 +#define STM_TIM1_DIER_CC2DE 10 +#define STM_TIM1_DIER_CC1DE 9 +#define STM_TIM1_DIER_UDE 8 +#define STM_TIM1_DIER_BIE 7 +#define STM_TIM1_DIER_TIE 6 +#define STM_TIM1_DIER_COMIE 5 +#define STM_TIM1_DIER_CC4IE 4 +#define STM_TIM1_DIER_CC3IE 3 +#define STM_TIM1_DIER_CC2IE 2 +#define STM_TIM1_DIER_CC1IE 1 +#define STM_TIM1_DIER_UIE 0 + +#define STM_TIM1_SR_CC4OF 12 +#define STM_TIM1_SR_CC3OF 11 +#define STM_TIM1_SR_CC2OF 10 +#define STM_TIM1_SR_CC1OF 9 +#define STM_TIM1_SR_BIF 7 +#define STM_TIM1_SR_TIF 6 +#define STM_TIM1_SR_COMIF 5 +#define STM_TIM1_SR_CC4IF 4 +#define STM_TIM1_SR_CC3IF 3 +#define STM_TIM1_SR_CC2IF 2 +#define STM_TIM1_SR_CC1IF 1 +#define STM_TIM1_SR_UIF 0 + +#define STM_TIM1_EGR_BG 7 +#define STM_TIM1_EGR_TG 6 +#define STM_TIM1_EGR_COMG 5 +#define STM_TIM1_EGR_CC4G 4 +#define STM_TIM1_EGR_CC3G 3 +#define STM_TIM1_EGR_CC2G 2 +#define STM_TIM1_EGR_CC1G 1 +#define STM_TIM1_EGR_UG 0 + +#define STM_TIM1_CCMR1_OC2CE 15 +#define STM_TIM1_CCMR1_OC2M 12 +#define STM_TIM1_CCMR1_OC2PE 11 +#define STM_TIM1_CCMR1_OC2FE 10 +#define STM_TIM1_CCMR1_CC2S 8 +#define STM_TIM1_CCMR1_OC1CE 7 +#define STM_TIM1_CCMR1_OC1M 4 +#define STM_TIM1_CCMR_OCM_FROZEN 0 +#define STM_TIM1_CCMR_OCM_1_HIGH_MATCH 1 +#define STM_TIM1_CCMR_OCM_1_LOW_MATCH 2 +#define STM_TIM1_CCMR_OCM_TOGGLE 3 +#define STM_TIM1_CCMR_OCM_FORCE_LOW 4 +#define STM_TIM1_CCMR_OCM_FORCE_HIGH 5 +#define STM_TIM1_CCMR_OCM_PWM_MODE_1 6 +#define STM_TIM1_CCMR_OCM_PWM_MODE_2 7 + +#define STM_TIM1_CCMR1_OC1PE 3 +#define STM_TIM1_CCMR1_OC1FE 2 +#define STM_TIM1_CCMR1_CC1S 0 +#define STM_TIM1_CCMR_CCS_OUTPUT 0 +#define STM_TIM1_CCMR_CCS_INPUT_TI1 1 +#define STM_TIM1_CCMR_CCS_INPUT_TI2 2 +#define STM_TIM1_CCMR_CCS_INPUT_TRC 3 + +#define STM_TIM1_CCMR1_IC2F 12 +#define STM_TIM1_CCMR1_IC2PSC 10 +#define STM_TIM1_CCMR1_CC2S 8 +#define STM_TIM1_CCMR1_IC1F 4 +#define STM_TIM1_CCMR1_IC1F_NONE 0 +#define STM_TIM1_CCMR1_IC1F_DIV_1_N_2 1 +#define STM_TIM1_CCMR1_IC1F_DIV_1_N_4 2 +#define STM_TIM1_CCMR1_IC1F_DIV_1_N_8 3 +#define STM_TIM1_CCMR1_IC1F_DIV_2_N_6 4 +#define STM_TIM1_CCMR1_IC1F_DIV_2_N_8 5 +#define STM_TIM1_CCMR1_IC1F_DIV_4_N_6 6 +#define STM_TIM1_CCMR1_IC1F_DIV_4_N_8 7 +#define STM_TIM1_CCMR1_IC1F_DIV_8_N_6 8 +#define STM_TIM1_CCMR1_IC1F_DIV_8_N_8 9 +#define STM_TIM1_CCMR1_IC1F_DIV_16_N_5 10 +#define STM_TIM1_CCMR1_IC1F_DIV_16_N_6 11 +#define STM_TIM1_CCMR1_IC1F_DIV_16_N_8 12 +#define STM_TIM1_CCMR1_IC1F_DIV_32_N_5 13 +#define STM_TIM1_CCMR1_IC1F_DIV_32_N_6 14 +#define STM_TIM1_CCMR1_IC1F_DIV_32_N_8 15 + +#define STM_TIM1_CCMR1_IC1PSC 2 +#define STM_TIM1_CCMR1_IC1PSC_NONE 0 +#define STM_TIM1_CCMR1_IC1PSC_2 1 +#define STM_TIM1_CCMR1_IC1PSC_4 2 +#define STM_TIM1_CCMR1_IC1PSC_8 3 + +#define STM_TIM1_CCMR1_CC1S 0 +#define STM_TIM1_CCMR1_CC1S_OUTPUT 0 +#define STM_TIM1_CCMR1_CC1S_TI1 1 +#define STM_TIM1_CCMR1_CC1S_TI2 2 +#define STM_TIM1_CCMR1_CC1S_TRC 3 + +#define STM_TIM1_CCMR2_OC4CE 15 +#define STM_TIM1_CCMR2_OC4M 12 +#define STM_TIM1_CCMR2_OC4PE 11 +#define STM_TIM1_CCMR2_OC4FE 10 +#define STM_TIM1_CCMR2_CC4S 8 +#define STM_TIM1_CCMR2_CCS_OUTPUT 0 +#define STM_TIM1_CCMR2_CCS_INPUT_TI3 1 +#define STM_TIM1_CCMR2_CCS_INPUT_TI4 2 +#define STM_TIM1_CCMR2_CCS_INPUT_TRC 3 +#define STM_TIM1_CCMR2_OC3CE 7 +#define STM_TIM1_CCMR2_OC3M 4 +#define STM_TIM1_CCMR2_OC3PE 3 +#define STM_TIM1_CCMR2_OC3FE 2 +#define STM_TIM1_CCMR2_CC3S 0 + +#define STM_TIM1_CCMR2_IC4F 12 +#define STM_TIM1_CCMR2_IC2PSC 10 +#define STM_TIM1_CCMR2_CC4S 8 +#define STM_TIM1_CCMR2_IC3F 4 +#define STM_TIM1_CCMR2_IC1F_NONE 0 +#define STM_TIM1_CCMR2_IC1F_DIV_1_N_2 1 +#define STM_TIM1_CCMR2_IC1F_DIV_1_N_4 2 +#define STM_TIM1_CCMR2_IC1F_DIV_1_N_8 3 +#define STM_TIM1_CCMR2_IC1F_DIV_2_N_6 4 +#define STM_TIM1_CCMR2_IC1F_DIV_2_N_8 5 +#define STM_TIM1_CCMR2_IC1F_DIV_4_N_6 6 +#define STM_TIM1_CCMR2_IC1F_DIV_4_N_8 7 +#define STM_TIM1_CCMR2_IC1F_DIV_8_N_6 8 +#define STM_TIM1_CCMR2_IC1F_DIV_8_N_8 9 +#define STM_TIM1_CCMR2_IC1F_DIV_16_N_5 10 +#define STM_TIM1_CCMR2_IC1F_DIV_16_N_6 11 +#define STM_TIM1_CCMR2_IC1F_DIV_16_N_8 12 +#define STM_TIM1_CCMR2_IC1F_DIV_32_N_5 13 +#define STM_TIM1_CCMR2_IC1F_DIV_32_N_6 14 +#define STM_TIM1_CCMR2_IC1F_DIV_32_N_8 15 + +#define STM_TIM1_CCER_CC4P 13 +#define STM_TIM1_CCER_CC4E 12 +#define STM_TIM1_CCER_CC3NP 11 +#define STM_TIM1_CCER_CC3NE 10 +#define STM_TIM1_CCER_CC3P 9 +#define STM_TIM1_CCER_CC3E 8 +#define STM_TIM1_CCER_CC2NP 7 +#define STM_TIM1_CCER_CC2NE 6 +#define STM_TIM1_CCER_CC2P 5 +#define STM_TIM1_CCER_CC2E 4 +#define STM_TIM1_CCER_CC1BP 3 +#define STM_TIM1_CCER_CC1NE 2 +#define STM_TIM1_CCER_CC1P 1 +#define STM_TIM1_CCER_CC1E 0 + +#define STM_TIM1_BDTR_MOE 15 +#define STM_TIM1_BDTR_AOE 14 +#define STM_TIM1_BDTR_BKP 13 +#define STM_TIM1_BDTR_BKE 12 +#define STM_TIM1_BDTR_OSSR 11 +#define STM_TIM1_BDTR_OSSI 10 +#define STM_TIM1_BDTR_LOCK 8 +#define STM_TIM1_BDTR_LOCK_OFF 0 +#define STM_TIM1_BDTR_LOCK_LEVEL_1 1 +#define STM_TIM1_BDTR_LOCK_LEVEL_2 2 +#define STM_TIM1_BDTR_LOCK_LEVEL_3 3 + +#define STM_TIM1_BDTR_DTG 0 + +#define STM_TIM1_DCR_DBL 8 +#define STM_TIM1_DCR_DBA 0 + +extern struct stm_tim1 stm_tim1; + +#define stm_tim1 (*(struct stm_tim1 *)0x40012c00) + +struct stm_tim23 { vuint32_t cr1; vuint32_t cr2; vuint32_t smcr; @@ -1286,204 +1654,205 @@ struct stm_tim234 { uint32_t reserved_44; vuint32_t dcr; vuint32_t dmar; - - uint32_t reserved_50; }; -extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4; - -#define STM_TIM234_CR1_CKD 8 -#define STM_TIM234_CR1_CKD_1 0 -#define STM_TIM234_CR1_CKD_2 1 -#define STM_TIM234_CR1_CKD_4 2 -#define STM_TIM234_CR1_CKD_MASK 3 -#define STM_TIM234_CR1_ARPE 7 -#define STM_TIM234_CR1_CMS 5 -#define STM_TIM234_CR1_CMS_EDGE 0 -#define STM_TIM234_CR1_CMS_CENTER_1 1 -#define STM_TIM234_CR1_CMS_CENTER_2 2 -#define STM_TIM234_CR1_CMS_CENTER_3 3 -#define STM_TIM234_CR1_CMS_MASK 3 -#define STM_TIM234_CR1_DIR 4 -#define STM_TIM234_CR1_DIR_UP 0 -#define STM_TIM234_CR1_DIR_DOWN 1 -#define STM_TIM234_CR1_OPM 3 -#define STM_TIM234_CR1_URS 2 -#define STM_TIM234_CR1_UDIS 1 -#define STM_TIM234_CR1_CEN 0 - -#define STM_TIM234_CR2_TI1S 7 -#define STM_TIM234_CR2_MMS 4 -#define STM_TIM234_CR2_MMS_RESET 0 -#define STM_TIM234_CR2_MMS_ENABLE 1 -#define STM_TIM234_CR2_MMS_UPDATE 2 -#define STM_TIM234_CR2_MMS_COMPARE_PULSE 3 -#define STM_TIM234_CR2_MMS_COMPARE_OC1REF 4 -#define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5 -#define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6 -#define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7 -#define STM_TIM234_CR2_MMS_MASK 7 -#define STM_TIM234_CR2_CCDS 3 - -#define STM_TIM234_SMCR_ETP 15 -#define STM_TIM234_SMCR_ECE 14 -#define STM_TIM234_SMCR_ETPS 12 -#define STM_TIM234_SMCR_ETPS_OFF 0 -#define STM_TIM234_SMCR_ETPS_DIV_2 1 -#define STM_TIM234_SMCR_ETPS_DIV_4 2 -#define STM_TIM234_SMCR_ETPS_DIV_8 3 -#define STM_TIM234_SMCR_ETPS_MASK 3 -#define STM_TIM234_SMCR_ETF 8 -#define STM_TIM234_SMCR_ETF_NONE 0 -#define STM_TIM234_SMCR_ETF_INT_N_2 1 -#define STM_TIM234_SMCR_ETF_INT_N_4 2 -#define STM_TIM234_SMCR_ETF_INT_N_8 3 -#define STM_TIM234_SMCR_ETF_DTS_2_N_6 4 -#define STM_TIM234_SMCR_ETF_DTS_2_N_8 5 -#define STM_TIM234_SMCR_ETF_DTS_4_N_6 6 -#define STM_TIM234_SMCR_ETF_DTS_4_N_8 7 -#define STM_TIM234_SMCR_ETF_DTS_8_N_6 8 -#define STM_TIM234_SMCR_ETF_DTS_8_N_8 9 -#define STM_TIM234_SMCR_ETF_DTS_16_N_5 10 -#define STM_TIM234_SMCR_ETF_DTS_16_N_6 11 -#define STM_TIM234_SMCR_ETF_DTS_16_N_8 12 -#define STM_TIM234_SMCR_ETF_DTS_32_N_5 13 -#define STM_TIM234_SMCR_ETF_DTS_32_N_6 14 -#define STM_TIM234_SMCR_ETF_DTS_32_N_8 15 -#define STM_TIM234_SMCR_ETF_MASK 15 -#define STM_TIM234_SMCR_MSM 7 -#define STM_TIM234_SMCR_TS 4 -#define STM_TIM234_SMCR_TS_ITR0 0 -#define STM_TIM234_SMCR_TS_ITR1 1 -#define STM_TIM234_SMCR_TS_ITR2 2 -#define STM_TIM234_SMCR_TS_ITR3 3 -#define STM_TIM234_SMCR_TS_TI1F_ED 4 -#define STM_TIM234_SMCR_TS_TI1FP1 5 -#define STM_TIM234_SMCR_TS_TI2FP2 6 -#define STM_TIM234_SMCR_TS_ETRF 7 -#define STM_TIM234_SMCR_TS_MASK 7 -#define STM_TIM234_SMCR_OCCS 3 -#define STM_TIM234_SMCR_SMS 0 -#define STM_TIM234_SMCR_SMS_DISABLE 0 -#define STM_TIM234_SMCR_SMS_ENCODER_MODE_1 1 -#define STM_TIM234_SMCR_SMS_ENCODER_MODE_2 2 -#define STM_TIM234_SMCR_SMS_ENCODER_MODE_3 3 -#define STM_TIM234_SMCR_SMS_RESET_MODE 4 -#define STM_TIM234_SMCR_SMS_GATED_MODE 5 -#define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6 -#define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7 -#define STM_TIM234_SMCR_SMS_MASK 7 - -#define STM_TIM234_SR_CC4OF 12 -#define STM_TIM234_SR_CC3OF 11 -#define STM_TIM234_SR_CC2OF 10 -#define STM_TIM234_SR_CC1OF 9 -#define STM_TIM234_SR_TIF 6 -#define STM_TIM234_SR_CC4IF 4 -#define STM_TIM234_SR_CC3IF 3 -#define STM_TIM234_SR_CC2IF 2 -#define STM_TIM234_SR_CC1IF 1 -#define STM_TIM234_SR_UIF 0 - -#define STM_TIM234_EGR_TG 6 -#define STM_TIM234_EGR_CC4G 4 -#define STM_TIM234_EGR_CC3G 3 -#define STM_TIM234_EGR_CC2G 2 -#define STM_TIM234_EGR_CC1G 1 -#define STM_TIM234_EGR_UG 0 - -#define STM_TIM234_CCMR1_OC2CE 15 -#define STM_TIM234_CCMR1_OC2M 12 -#define STM_TIM234_CCMR1_OC2M_FROZEN 0 -#define STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH 1 -#define STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH 2 -#define STM_TIM234_CCMR1_OC2M_TOGGLE 3 -#define STM_TIM234_CCMR1_OC2M_FORCE_LOW 4 -#define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5 -#define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6 -#define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7 -#define STM_TIM234_CCMR1_OC2M_MASK 7 -#define STM_TIM234_CCMR1_OC2PE 11 -#define STM_TIM234_CCMR1_OC2FE 10 -#define STM_TIM234_CCMR1_CC2S 8 -#define STM_TIM234_CCMR1_CC2S_OUTPUT 0 -#define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1 -#define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2 -#define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3 -#define STM_TIM234_CCMR1_CC2S_MASK 3 - -#define STM_TIM234_CCMR1_OC1CE 7 -#define STM_TIM234_CCMR1_OC1M 4 -#define STM_TIM234_CCMR1_OC1M_FROZEN 0 -#define STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH 1 -#define STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH 2 -#define STM_TIM234_CCMR1_OC1M_TOGGLE 3 -#define STM_TIM234_CCMR1_OC1M_FORCE_LOW 4 -#define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5 -#define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6 -#define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7 -#define STM_TIM234_CCMR1_OC1M_MASK 7 -#define STM_TIM234_CCMR1_OC1PE 11 -#define STM_TIM234_CCMR1_OC1FE 2 -#define STM_TIM234_CCMR1_CC1S 0 -#define STM_TIM234_CCMR1_CC1S_OUTPUT 0 -#define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1 -#define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2 -#define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3 -#define STM_TIM234_CCMR1_CC1S_MASK 3 - -#define STM_TIM234_CCMR2_OC4CE 15 -#define STM_TIM234_CCMR2_OC4M 12 -#define STM_TIM234_CCMR2_OC4M_FROZEN 0 -#define STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH 1 -#define STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH 2 -#define STM_TIM234_CCMR2_OC4M_TOGGLE 3 -#define STM_TIM234_CCMR2_OC4M_FORCE_LOW 4 -#define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5 -#define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6 -#define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7 -#define STM_TIM234_CCMR2_OC4M_MASK 7 -#define STM_TIM234_CCMR2_OC4PE 11 -#define STM_TIM234_CCMR2_OC4FE 10 -#define STM_TIM234_CCMR2_CC4S 8 -#define STM_TIM234_CCMR2_CC4S_OUTPUT 0 -#define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1 -#define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2 -#define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3 -#define STM_TIM234_CCMR2_CC4S_MASK 3 - -#define STM_TIM234_CCMR2_OC3CE 7 -#define STM_TIM234_CCMR2_OC3M 4 -#define STM_TIM234_CCMR2_OC3M_FROZEN 0 -#define STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH 1 -#define STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH 2 -#define STM_TIM234_CCMR2_OC3M_TOGGLE 3 -#define STM_TIM234_CCMR2_OC3M_FORCE_LOW 4 -#define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5 -#define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6 -#define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7 -#define STM_TIM234_CCMR2_OC3M_MASK 7 -#define STM_TIM234_CCMR2_OC3PE 11 -#define STM_TIM234_CCMR2_OC3FE 2 -#define STM_TIM234_CCMR2_CC3S 0 -#define STM_TIM234_CCMR2_CC3S_OUTPUT 0 -#define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1 -#define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2 -#define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3 -#define STM_TIM234_CCMR2_CC3S_MASK 3 - -#define STM_TIM234_CCER_CC4NP 15 -#define STM_TIM234_CCER_CC4P 13 -#define STM_TIM234_CCER_CC4E 12 -#define STM_TIM234_CCER_CC3NP 11 -#define STM_TIM234_CCER_CC3P 9 -#define STM_TIM234_CCER_CC3E 8 -#define STM_TIM234_CCER_CC2NP 7 -#define STM_TIM234_CCER_CC2P 5 -#define STM_TIM234_CCER_CC2E 4 -#define STM_TIM234_CCER_CC1NP 3 -#define STM_TIM234_CCER_CC1P 1 -#define STM_TIM234_CCER_CC1E 0 +extern struct stm_tim23 stm_tim2, stm_tim3; + +#define stm_tim3 (*(struct stm_tim23 *) 0x40000400) +#define stm_tim2 (*(struct stm_tim23 *) 0x40000000) + +#define STM_TIM23_CR1_CKD 8 +#define STM_TIM23_CR1_CKD_1 0 +#define STM_TIM23_CR1_CKD_2 1 +#define STM_TIM23_CR1_CKD_4 2 +#define STM_TIM23_CR1_CKD_MASK 3 +#define STM_TIM23_CR1_ARPE 7 +#define STM_TIM23_CR1_CMS 5 +#define STM_TIM23_CR1_CMS_EDGE 0 +#define STM_TIM23_CR1_CMS_CENTER_1 1 +#define STM_TIM23_CR1_CMS_CENTER_2 2 +#define STM_TIM23_CR1_CMS_CENTER_3 3 +#define STM_TIM23_CR1_CMS_MASK 3 +#define STM_TIM23_CR1_DIR 4 +#define STM_TIM23_CR1_DIR_UP 0 +#define STM_TIM23_CR1_DIR_DOWN 1 +#define STM_TIM23_CR1_OPM 3 +#define STM_TIM23_CR1_URS 2 +#define STM_TIM23_CR1_UDIS 1 +#define STM_TIM23_CR1_CEN 0 + +#define STM_TIM23_CR2_TI1S 7 +#define STM_TIM23_CR2_MMS 4 +#define STM_TIM23_CR2_MMS_RESET 0 +#define STM_TIM23_CR2_MMS_ENABLE 1 +#define STM_TIM23_CR2_MMS_UPDATE 2 +#define STM_TIM23_CR2_MMS_COMPARE_PULSE 3 +#define STM_TIM23_CR2_MMS_COMPARE_OC1REF 4 +#define STM_TIM23_CR2_MMS_COMPARE_OC2REF 5 +#define STM_TIM23_CR2_MMS_COMPARE_OC3REF 6 +#define STM_TIM23_CR2_MMS_COMPARE_OC4REF 7 +#define STM_TIM23_CR2_MMS_MASK 7 +#define STM_TIM23_CR2_CCDS 3 + +#define STM_TIM23_SMCR_ETP 15 +#define STM_TIM23_SMCR_ECE 14 +#define STM_TIM23_SMCR_ETPS 12 +#define STM_TIM23_SMCR_ETPS_OFF 0 +#define STM_TIM23_SMCR_ETPS_DIV_2 1 +#define STM_TIM23_SMCR_ETPS_DIV_4 2 +#define STM_TIM23_SMCR_ETPS_DIV_8 3 +#define STM_TIM23_SMCR_ETPS_MASK 3 +#define STM_TIM23_SMCR_ETF 8 +#define STM_TIM23_SMCR_ETF_NONE 0 +#define STM_TIM23_SMCR_ETF_INT_N_2 1 +#define STM_TIM23_SMCR_ETF_INT_N_4 2 +#define STM_TIM23_SMCR_ETF_INT_N_8 3 +#define STM_TIM23_SMCR_ETF_DTS_2_N_6 4 +#define STM_TIM23_SMCR_ETF_DTS_2_N_8 5 +#define STM_TIM23_SMCR_ETF_DTS_4_N_6 6 +#define STM_TIM23_SMCR_ETF_DTS_4_N_8 7 +#define STM_TIM23_SMCR_ETF_DTS_8_N_6 8 +#define STM_TIM23_SMCR_ETF_DTS_8_N_8 9 +#define STM_TIM23_SMCR_ETF_DTS_16_N_5 10 +#define STM_TIM23_SMCR_ETF_DTS_16_N_6 11 +#define STM_TIM23_SMCR_ETF_DTS_16_N_8 12 +#define STM_TIM23_SMCR_ETF_DTS_32_N_5 13 +#define STM_TIM23_SMCR_ETF_DTS_32_N_6 14 +#define STM_TIM23_SMCR_ETF_DTS_32_N_8 15 +#define STM_TIM23_SMCR_ETF_MASK 15 +#define STM_TIM23_SMCR_MSM 7 +#define STM_TIM23_SMCR_TS 4 +#define STM_TIM23_SMCR_TS_ITR0 0 +#define STM_TIM23_SMCR_TS_ITR1 1 +#define STM_TIM23_SMCR_TS_ITR2 2 +#define STM_TIM23_SMCR_TS_ITR3 3 +#define STM_TIM23_SMCR_TS_TI1F_ED 4 +#define STM_TIM23_SMCR_TS_TI1FP1 5 +#define STM_TIM23_SMCR_TS_TI2FP2 6 +#define STM_TIM23_SMCR_TS_ETRF 7 +#define STM_TIM23_SMCR_TS_MASK 7 +#define STM_TIM23_SMCR_OCCS 3 +#define STM_TIM23_SMCR_SMS 0 +#define STM_TIM23_SMCR_SMS_DISABLE 0 +#define STM_TIM23_SMCR_SMS_ENCODER_MODE_1 1 +#define STM_TIM23_SMCR_SMS_ENCODER_MODE_2 2 +#define STM_TIM23_SMCR_SMS_ENCODER_MODE_3 3 +#define STM_TIM23_SMCR_SMS_RESET_MODE 4 +#define STM_TIM23_SMCR_SMS_GATED_MODE 5 +#define STM_TIM23_SMCR_SMS_TRIGGER_MODE 6 +#define STM_TIM23_SMCR_SMS_EXTERNAL_CLOCK 7 +#define STM_TIM23_SMCR_SMS_MASK 7 + +#define STM_TIM23_SR_CC4OF 12 +#define STM_TIM23_SR_CC3OF 11 +#define STM_TIM23_SR_CC2OF 10 +#define STM_TIM23_SR_CC1OF 9 +#define STM_TIM23_SR_TIF 6 +#define STM_TIM23_SR_CC4IF 4 +#define STM_TIM23_SR_CC3IF 3 +#define STM_TIM23_SR_CC2IF 2 +#define STM_TIM23_SR_CC1IF 1 +#define STM_TIM23_SR_UIF 0 + +#define STM_TIM23_EGR_TG 6 +#define STM_TIM23_EGR_CC4G 4 +#define STM_TIM23_EGR_CC3G 3 +#define STM_TIM23_EGR_CC2G 2 +#define STM_TIM23_EGR_CC1G 1 +#define STM_TIM23_EGR_UG 0 + +#define STM_TIM23_CCMR1_OC2CE 15 +#define STM_TIM23_CCMR1_OC2M 12 +#define STM_TIM23_CCMR1_OC2M_FROZEN 0 +#define STM_TIM23_CCMR1_OC2M_SET_HIGH_ON_MATCH 1 +#define STM_TIM23_CCMR1_OC2M_SET_LOW_ON_MATCH 2 +#define STM_TIM23_CCMR1_OC2M_TOGGLE 3 +#define STM_TIM23_CCMR1_OC2M_FORCE_LOW 4 +#define STM_TIM23_CCMR1_OC2M_FORCE_HIGH 5 +#define STM_TIM23_CCMR1_OC2M_PWM_MODE_1 6 +#define STM_TIM23_CCMR1_OC2M_PWM_MODE_2 7 +#define STM_TIM23_CCMR1_OC2M_MASK 7 +#define STM_TIM23_CCMR1_OC2PE 11 +#define STM_TIM23_CCMR1_OC2FE 10 +#define STM_TIM23_CCMR1_CC2S 8 +#define STM_TIM23_CCMR1_CC2S_OUTPUT 0 +#define STM_TIM23_CCMR1_CC2S_INPUT_TI2 1 +#define STM_TIM23_CCMR1_CC2S_INPUT_TI1 2 +#define STM_TIM23_CCMR1_CC2S_INPUT_TRC 3 +#define STM_TIM23_CCMR1_CC2S_MASK 3 + +#define STM_TIM23_CCMR1_OC1CE 7 +#define STM_TIM23_CCMR1_OC1M 4 +#define STM_TIM23_CCMR1_OC1M_FROZEN 0 +#define STM_TIM23_CCMR1_OC1M_SET_HIGH_ON_MATCH 1 +#define STM_TIM23_CCMR1_OC1M_SET_LOW_ON_MATCH 2 +#define STM_TIM23_CCMR1_OC1M_TOGGLE 3 +#define STM_TIM23_CCMR1_OC1M_FORCE_LOW 4 +#define STM_TIM23_CCMR1_OC1M_FORCE_HIGH 5 +#define STM_TIM23_CCMR1_OC1M_PWM_MODE_1 6 +#define STM_TIM23_CCMR1_OC1M_PWM_MODE_2 7 +#define STM_TIM23_CCMR1_OC1M_MASK 7 +#define STM_TIM23_CCMR1_OC1PE 11 +#define STM_TIM23_CCMR1_OC1FE 2 +#define STM_TIM23_CCMR1_CC1S 0 +#define STM_TIM23_CCMR1_CC1S_OUTPUT 0 +#define STM_TIM23_CCMR1_CC1S_INPUT_TI1 1 +#define STM_TIM23_CCMR1_CC1S_INPUT_TI2 2 +#define STM_TIM23_CCMR1_CC1S_INPUT_TRC 3 +#define STM_TIM23_CCMR1_CC1S_MASK 3 + +#define STM_TIM23_CCMR2_OC4CE 15 +#define STM_TIM23_CCMR2_OC4M 12 +#define STM_TIM23_CCMR2_OCM_FROZEN 0 +#define STM_TIM23_CCMR2_OCM_SET_HIGH_ON_MATCH 1 +#define STM_TIM23_CCMR2_OCM_SET_LOW_ON_MATCH 2 +#define STM_TIM23_CCMR2_OCM_TOGGLE 3 +#define STM_TIM23_CCMR2_OCM_FORCE_LOW 4 +#define STM_TIM23_CCMR2_OCM_FORCE_HIGH 5 +#define STM_TIM23_CCMR2_OCM_PWM_MODE_1 6 +#define STM_TIM23_CCMR2_OCM_PWM_MODE_2 7 +#define STM_TIM23_CCMR2_OCM_MASK 7 +#define STM_TIM23_CCMR2_OC4PE 11 +#define STM_TIM23_CCMR2_OC4FE 10 +#define STM_TIM23_CCMR2_CC4S 8 +#define STM_TIM23_CCMR2_CC4S_OUTPUT 0 +#define STM_TIM23_CCMR2_CC4S_INPUT_TI4 1 +#define STM_TIM23_CCMR2_CC4S_INPUT_TI3 2 +#define STM_TIM23_CCMR2_CC4S_INPUT_TRC 3 +#define STM_TIM23_CCMR2_CC4S_MASK 3 + +#define STM_TIM23_CCMR2_OC3CE 7 +#define STM_TIM23_CCMR2_OC3M 4 +#define STM_TIM23_CCMR2_OCM_FROZEN 0 +#define STM_TIM23_CCMR2_OCM_SET_HIGH_ON_MATCH 1 +#define STM_TIM23_CCMR2_OCM_SET_LOW_ON_MATCH 2 +#define STM_TIM23_CCMR2_OCM_TOGGLE 3 +#define STM_TIM23_CCMR2_OCM_FORCE_LOW 4 +#define STM_TIM23_CCMR2_OCM_FORCE_HIGH 5 +#define STM_TIM23_CCMR2_OC3M_PWM_MODE_1 6 +#define STM_TIM23_CCMR2_OCM_PWM_MODE_2 7 +#define STM_TIM23_CCMR2_OCM_MASK 7 +#define STM_TIM23_CCMR2_OC3PE 11 +#define STM_TIM23_CCMR2_OC3FE 2 +#define STM_TIM23_CCMR2_CC3S 0 +#define STM_TIM23_CCMR2_CC3S_OUTPUT 0 +#define STM_TIM23_CCMR2_CC3S_INPUT_TI3 1 +#define STM_TIM23_CCMR2_CC3S_INPUT_TI4 2 +#define STM_TIM23_CCMR2_CC3S_INPUT_TRC 3 +#define STM_TIM23_CCMR2_CC3S_MASK 3 + +#define STM_TIM23_CCER_CC4NP 15 +#define STM_TIM23_CCER_CC4P 13 +#define STM_TIM23_CCER_CC4E 12 +#define STM_TIM23_CCER_CC3NP 11 +#define STM_TIM23_CCER_CC3P 9 +#define STM_TIM23_CCER_CC3E 8 +#define STM_TIM23_CCER_CC2NP 7 +#define STM_TIM23_CCER_CC2P 5 +#define STM_TIM23_CCER_CC2E 4 +#define STM_TIM23_CCER_CC1NP 3 +#define STM_TIM23_CCER_CC1P 1 +#define STM_TIM23_CCER_CC1E 0 struct stm_usb { struct {