X-Git-Url: https://git.gag.com/?p=fw%2Faltos;a=blobdiff_plain;f=src%2Fstm%2Fstm32l.h;h=799cccbd2a1848bd9510ad0aa1f62d2cea857ee3;hp=e950d09bf5b8b905b6b32d7e37c290ce549ba696;hb=ee91e1da606c8a8fade278a3aeae9c1cc9014b84;hpb=b119e19604aa557a40e848c60d98a67b5f259bbd

diff --git a/src/stm/stm32l.h b/src/stm/stm32l.h
index e950d09b..799cccbd 100644
--- a/src/stm/stm32l.h
+++ b/src/stm/stm32l.h
@@ -52,7 +52,7 @@ stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
 		       value << STM_MODER_SHIFT(pin));
 }
 	
-static inline vuint32_t
+static inline uint32_t
 stm_moder_get(struct stm_gpio *gpio, int pin) {
 	return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
 }
@@ -69,7 +69,7 @@ stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
 			value << STM_OTYPER_SHIFT(pin));
 }
 	
-static inline vuint32_t
+static inline uint32_t
 stm_otyper_get(struct stm_gpio *gpio, int pin) {
 	return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
 }
@@ -88,7 +88,7 @@ stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
 		       value << STM_OSPEEDR_SHIFT(pin));
 }
 	
-static inline vuint32_t
+static inline uint32_t
 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
 	return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
 }
@@ -171,12 +171,32 @@ stm_gpio_get(struct stm_gpio *gpio, int pin) {
 	return (gpio->idr >> pin) & 1;
 }
 
-extern struct stm_gpio stm_gpioa;
-extern struct stm_gpio stm_gpiob;
-extern struct stm_gpio stm_gpioc;
-extern struct stm_gpio stm_gpiod;
-extern struct stm_gpio stm_gpioe;
-extern struct stm_gpio stm_gpioh;
+static inline uint16_t
+stm_gpio_get_all(struct stm_gpio *gpio) {
+	return gpio->idr;
+}
+
+/*
+ * We can't define these in registers.ld or our fancy
+ * ao_enable_gpio macro will expand into a huge pile of code
+ * as the compiler won't do correct constant folding and
+ * dead-code elimination
+
+ extern struct stm_gpio stm_gpioa;
+ extern struct stm_gpio stm_gpiob;
+ extern struct stm_gpio stm_gpioc;
+ extern struct stm_gpio stm_gpiod;
+ extern struct stm_gpio stm_gpioe;
+ extern struct stm_gpio stm_gpioh;
+
+*/
+
+#define stm_gpioh  (*((struct stm_gpio *) 0x40021400))
+#define stm_gpioe  (*((struct stm_gpio *) 0x40021000))
+#define stm_gpiod  (*((struct stm_gpio *) 0x40020c00))
+#define stm_gpioc  (*((struct stm_gpio *) 0x40020800))
+#define stm_gpiob  (*((struct stm_gpio *) 0x40020400))
+#define stm_gpioa  (*((struct stm_gpio *) 0x40020000))
 
 struct stm_usart {
 	vuint32_t	sr;	/* status register */
@@ -435,6 +455,9 @@ extern struct stm_flash	stm_flash;
 #define STM_FLASH_PEKEYR_PEKEY1	0x89ABCDEF
 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
 
+#define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
+#define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
+
 struct stm_rcc {
 	vuint32_t	cr;
 	vuint32_t	icscr;
@@ -811,30 +834,59 @@ extern struct stm_lcd stm_lcd;
 #define STM_LCD_CLR_UDDC		(3)
 #define STM_LCD_CLR_SOFC		(1)
 
+/* The SYSTICK starts at 0xe000e010 */
+
+struct stm_systick {
+	vuint32_t	csr;
+	vuint32_t	rvr;
+	vuint32_t	cvr;
+	vuint32_t	calib;
+};
+
+extern struct stm_systick stm_systick;
+
+#define STM_SYSTICK_CSR_ENABLE		0
+#define STM_SYSTICK_CSR_TICKINT		1
+#define STM_SYSTICK_CSR_CLKSOURCE	2
+#define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8		0
+#define  STM_SYSTICK_CSR_CLKSOURCE_HCLK			1
+#define STM_SYSTICK_CSR_COUNTFLAG	16
+
+/* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
+
 struct stm_nvic {
-	vuint32_t	iser[3];	/* 0x000 */
+	vuint32_t	iser[8];	/* 0x000 0xe000e100 Set Enable Register */
+
+	uint8_t		_unused020[0x080 - 0x020];
+
+	vuint32_t	icer[8];	/* 0x080 0xe000e180 Clear Enable Register */
 
-	uint8_t		_unused00c[0x080 - 0x00c];
+	uint8_t		_unused0a0[0x100 - 0x0a0];
 
-	vuint32_t	icer[3];	/* 0x080 */
+	vuint32_t	ispr[8];	/* 0x100 0xe000e200 Set Pending Register */
 
-	uint8_t		_unused08c[0x100 - 0x08c];
+	uint8_t		_unused120[0x180 - 0x120];
 
-	vuint32_t	ispr[3];	/* 0x100 */
+	vuint32_t	icpr[8];	/* 0x180 0xe000e280 Clear Pending Register */
 
-	uint8_t		_unused10c[0x180 - 0x10c];
+	uint8_t		_unused1a0[0x200 - 0x1a0];
 
-	vuint32_t	icpr[3];	/* 0x180 */
+	vuint32_t	iabr[8];	/* 0x200 0xe000e300 Active Bit Register */
 
-	uint8_t		_unused18c[0x200 - 0x18c];
+	uint8_t		_unused220[0x300 - 0x220];
 
-	vuint32_t	iabr[3];	/* 0x200 */
+	vuint32_t	ipr[60];	/* 0x300 0xe000e400 Priority Register */
 
-	uint8_t		_unused20c[0x300 - 0x20c];
+	uint8_t		_unused3f0[0xc00 - 0x3f0];
 
-	vuint32_t	ipr[21];	/* 0x300 */
+	vuint32_t	cpuid_base;	/* 0xc00 0xe000ed00 CPUID Base Register */
+	vuint32_t	ics;		/* 0xc04 0xe000ed04 Interrupt Control State Register */
+	vuint32_t	vto;		/* 0xc08 0xe000ed08 Vector Table Offset Register */
+	vuint32_t	ai_rc;		/* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */
+	vuint32_t	sc;		/* 0xc10 0xe000ed10 System Control Register */
+	vuint32_t	cc;		/* 0xc14 0xe000ed14 Configuration Control Register */
 
-	uint8_t		_unused324[0xe00 - 0x324];
+	uint8_t		_unusedc18[0xe00 - 0xc18];
 
 	vuint32_t	stir;		/* 0xe00 */
 };
@@ -901,6 +953,93 @@ stm_nvic_get_priority(int irq) {
 	return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 }
 
+struct stm_scb {
+	vuint32_t	cpuid;
+	vuint32_t	icsr;
+	vuint32_t	vtor;
+	vuint32_t	aircr;
+
+	vuint32_t	scr;
+	vuint32_t	ccr;
+	vuint32_t	shpr1;
+	vuint32_t	shpr2;
+
+	vuint32_t	shpr3;
+	vuint32_t	shcrs;
+	vuint32_t	cfsr;
+	vuint32_t	hfsr;
+
+	uint32_t	unused_30;
+	vuint32_t	mmfar;
+	vuint32_t	bfar;
+};
+
+extern struct stm_scb stm_scb;
+
+#define STM_SCB_AIRCR_VECTKEY		16
+#define  STM_SCB_AIRCR_VECTKEY_KEY		0x05fa
+#define STM_SCB_AIRCR_PRIGROUP		8
+#define STM_SCB_AIRCR_SYSRESETREQ	2
+#define STM_SCB_AIRCR_VECTCLRACTIVE	1
+#define STM_SCB_AIRCR_VECTRESET		0
+
+struct stm_mpu {
+	vuint32_t	typer;
+	vuint32_t	cr;
+	vuint32_t	rnr;
+	vuint32_t	rbar;
+
+	vuint32_t	rasr;
+	vuint32_t	rbar_a1;
+	vuint32_t	rasr_a1;
+	vuint32_t	rbar_a2;
+	vuint32_t	rasr_a2;
+	vuint32_t	rbar_a3;
+	vuint32_t	rasr_a3;
+};
+
+extern struct stm_mpu stm_mpu;
+
+#define STM_MPU_TYPER_IREGION	16
+#define  STM_MPU_TYPER_IREGION_MASK	0xff
+#define STM_MPU_TYPER_DREGION	8
+#define  STM_MPU_TYPER_DREGION_MASK	0xff
+#define STM_MPU_TYPER_SEPARATE	0
+
+#define STM_MPU_CR_PRIVDEFENA	2
+#define STM_MPU_CR_HFNMIENA	1
+#define STM_MPU_CR_ENABLE	0
+
+#define STM_MPU_RNR_REGION	0
+#define STM_MPU_RNR_REGION_MASK		0xff
+
+#define STM_MPU_RBAR_ADDR	5
+#define STM_MPU_RBAR_ADDR_MASK		0x7ffffff
+
+#define STM_MPU_RBAR_VALID	4
+#define STM_MPU_RBAR_REGION	0
+#define STM_MPU_RBAR_REGION_MASK	0xf
+
+#define STM_MPU_RASR_XN		28
+#define STM_MPU_RASR_AP		24
+#define  STM_MPU_RASR_AP_NONE_NONE	0
+#define  STM_MPU_RASR_AP_RW_NONE	1
+#define  STM_MPU_RASR_AP_RW_RO		2
+#define  STM_MPU_RASR_AP_RW_RW		3
+#define  STM_MPU_RASR_AP_RO_NONE	5
+#define  STM_MPU_RASR_AP_RO_RO		6
+#define  STM_MPU_RASR_AP_MASK		7
+#define STM_MPU_RASR_TEX	19
+#define  STM_MPU_RASR_TEX_MASK		7
+#define STM_MPU_RASR_S		18
+#define STM_MPU_RASR_C		17
+#define STM_MPU_RASR_B		16
+#define STM_MPU_RASR_SRD	8
+#define  STM_MPU_RASR_SRD_MASK		0xff
+#define STM_MPU_RASR_SIZE	1
+#define  STM_MPU_RASR_SIZE_MASK		0x1f
+#define STM_MPU_RASR_ENABLE	0
+
 #define isr(name) void stm_ ## name ## _isr(void);
 
 isr(nmi)
@@ -1368,6 +1507,36 @@ extern struct stm_temp_cal	stm_temp_cal;
 #define stm_temp_cal_cold	25
 #define stm_temp_cal_hot	110
 
+struct stm_dbg_mcu {
+	uint32_t	idcode;
+};
+
+extern struct stm_dbg_mcu	stm_dbg_mcu;
+
+static inline uint16_t
+stm_dev_id(void) {
+	return stm_dbg_mcu.idcode & 0xfff;
+}
+
+struct stm_flash_size {
+	uint16_t	f_size;
+};
+
+extern struct stm_flash_size	stm_flash_size_medium;
+extern struct stm_flash_size	stm_flash_size_large;
+
+/* Returns flash size in bytes */
+extern uint32_t
+stm_flash_size(void);
+
+struct stm_device_id {
+	uint32_t	u_id0;
+	uint32_t	u_id1;
+	uint32_t	u_id2;
+};
+
+extern struct stm_device_id	stm_device_id;
+
 #define STM_NUM_I2C	2
 
 #define STM_I2C_INDEX(channel)	((channel) - 1)
@@ -1568,6 +1737,13 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
 #define STM_TIM234_SR_CC1IF	1
 #define STM_TIM234_SR_UIF	0
 
+#define STM_TIM234_EGR_TG	6
+#define STM_TIM234_EGR_CC4G	4
+#define STM_TIM234_EGR_CC3G	3
+#define STM_TIM234_EGR_CC2G	2
+#define STM_TIM234_EGR_CC1G	1
+#define STM_TIM234_EGR_UG	0
+
 #define STM_TIM234_CCMR1_OC2CE	15
 #define STM_TIM234_CCMR1_OC2M	12
 #define  STM_TIM234_CCMR1_OC2M_FROZEN			0
@@ -1608,7 +1784,7 @@ extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC		3
 #define  STM_TIM234_CCMR1_CC1S_MASK			3
 
-#define STM_TIM234_CCMR2_OC2CE	15
+#define STM_TIM234_CCMR2_OC4CE	15
 #define STM_TIM234_CCMR2_OC4M	12
 #define  STM_TIM234_CCMR2_OC4M_FROZEN			0
 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH	1