X-Git-Url: https://git.gag.com/?p=fw%2Faltos;a=blobdiff_plain;f=src%2Fstm%2Fstm32l.h;h=63bde0f8b29b475d887ddd2624c43fcc70395040;hp=d953aee433d5691b4061d82a49b882ac6fe82ad5;hb=56a7cbbf51f5c9ebbfe17d1cc30ed807572af3cc;hpb=4b13d3c659240e5a8347b1ba7ab0bf1d8355eba3

diff --git a/src/stm/stm32l.h b/src/stm/stm32l.h
index d953aee4..63bde0f8 100644
--- a/src/stm/stm32l.h
+++ b/src/stm/stm32l.h
@@ -435,6 +435,9 @@ extern struct stm_flash	stm_flash;
 #define STM_FLASH_PEKEYR_PEKEY1	0x89ABCDEF
 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
 
+#define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
+#define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
+
 struct stm_rcc {
 	vuint32_t	cr;
 	vuint32_t	icscr;
@@ -811,30 +814,59 @@ extern struct stm_lcd stm_lcd;
 #define STM_LCD_CLR_UDDC		(3)
 #define STM_LCD_CLR_SOFC		(1)
 
+/* The SYSTICK starts at 0xe000e010 */
+
+struct stm_systick {
+	vuint32_t	csr;
+	vuint32_t	rvr;
+	vuint32_t	cvr;
+	vuint32_t	calib;
+};
+
+extern struct stm_systick stm_systick;
+
+#define STM_SYSTICK_CSR_ENABLE		0
+#define STM_SYSTICK_CSR_TICKINT		1
+#define STM_SYSTICK_CSR_CLKSOURCE	2
+#define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8		0
+#define  STM_SYSTICK_CSR_CLKSOURCE_HCLK			1
+#define STM_SYSTICK_CSR_COUNTFLAG	16
+
+/* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
+
 struct stm_nvic {
-	vuint32_t	iser[3];	/* 0x000 */
+	vuint32_t	iser[8];	/* 0x000 0xe000e100 Set Enable Register */
+
+	uint8_t		_unused020[0x080 - 0x020];
+
+	vuint32_t	icer[8];	/* 0x080 0xe000e180 Clear Enable Register */
 
-	uint8_t		_unused00c[0x080 - 0x00c];
+	uint8_t		_unused0a0[0x100 - 0x0a0];
 
-	vuint32_t	icer[3];	/* 0x080 */
+	vuint32_t	ispr[8];	/* 0x100 0xe000e200 Set Pending Register */
 
-	uint8_t		_unused08c[0x100 - 0x08c];
+	uint8_t		_unused120[0x180 - 0x120];
 
-	vuint32_t	ispr[3];	/* 0x100 */
+	vuint32_t	icpr[8];	/* 0x180 0xe000e280 Clear Pending Register */
 
-	uint8_t		_unused10c[0x180 - 0x10c];
+	uint8_t		_unused1a0[0x200 - 0x1a0];
 
-	vuint32_t	icpr[3];	/* 0x180 */
+	vuint32_t	iabr[8];	/* 0x200 0xe000e300 Active Bit Register */
 
-	uint8_t		_unused18c[0x200 - 0x18c];
+	uint8_t		_unused220[0x300 - 0x220];
 
-	vuint32_t	iabr[3];	/* 0x200 */
+	vuint32_t	ipr[60];	/* 0x300 0xe000e400 Priority Register */
 
-	uint8_t		_unused20c[0x300 - 0x20c];
+	uint8_t		_unused3f0[0xc00 - 0x3f0];
 
-	vuint32_t	ipr[21];	/* 0x300 */
+	vuint32_t	cpuid_base;	/* 0xc00 0xe000ed00 CPUID Base Register */
+	vuint32_t	ics;		/* 0xc04 0xe000ed04 Interrupt Control State Register */
+	vuint32_t	vto;		/* 0xc08 0xe000ed08 Vector Table Offset Register */
+	vuint32_t	ai_rc;		/* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */
+	vuint32_t	sc;		/* 0xc10 0xe000ed10 System Control Register */
+	vuint32_t	cc;		/* 0xc14 0xe000ed14 Configuration Control Register */
 
-	uint8_t		_unused324[0xe00 - 0x324];
+	uint8_t		_unusedc18[0xe00 - 0xc18];
 
 	vuint32_t	stir;		/* 0xe00 */
 };
@@ -901,6 +933,36 @@ stm_nvic_get_priority(int irq) {
 	return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 }
 
+struct stm_scb {
+	vuint32_t	cpuid;
+	vuint32_t	icsr;
+	vuint32_t	vtor;
+	vuint32_t	aircr;
+
+	vuint32_t	scr;
+	vuint32_t	ccr;
+	vuint32_t	shpr1;
+	vuint32_t	shpr2;
+
+	vuint32_t	shpr3;
+	vuint32_t	shcrs;
+	vuint32_t	cfsr;
+	vuint32_t	hfsr;
+
+	uint32_t	unused_30;
+	vuint32_t	mmfar;
+	vuint32_t	bfar;
+};
+
+extern struct stm_scb stm_scb;
+
+#define STM_SCB_AIRCR_VECTKEY		16
+#define  STM_SCB_AIRCR_VECTKEY_KEY		0x05fa
+#define STM_SCB_AIRCR_PRIGROUP		8
+#define STM_SCB_AIRCR_SYSRESETREQ	2
+#define STM_SCB_AIRCR_VECTCLRACTIVE	1
+#define STM_SCB_AIRCR_VECTRESET		0
+
 struct stm_mpu {
 	vuint32_t	typer;
 	vuint32_t	cr;