X-Git-Url: https://git.gag.com/?p=fw%2Faltos;a=blobdiff_plain;f=src%2Fstm%2Fao_spi_stm.c;h=1a04a2899a825afa758726d5625d3c11a7536c34;hp=e69c2d7b8dc4932202ec87d0df5f05dd360b90a6;hb=6aeb000899ad7f22e92b487b5891664554bc4d33;hpb=5866d191cee56949ccab4c154a14604e83163d42 diff --git a/src/stm/ao_spi_stm.c b/src/stm/ao_spi_stm.c index e69c2d7b..1a04a289 100644 --- a/src/stm/ao_spi_stm.c +++ b/src/stm/ao_spi_stm.c @@ -3,7 +3,8 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of @@ -24,7 +25,7 @@ struct ao_spi_stm_info { }; static uint8_t ao_spi_mutex[STM_NUM_SPI]; -static uint8_t ao_spi_index[STM_NUM_SPI]; +static uint8_t ao_spi_pin_config[STM_NUM_SPI]; static const struct ao_spi_stm_info ao_spi_stm_info[STM_NUM_SPI] = { { @@ -84,6 +85,46 @@ validate_spi(struct stm_spi *stm_spi, int which, uint16_t len) #define validate_spi(stm_spi, which, len) do { (void) (which); (void) (len); } while (0) #endif +static void +ao_spi_set_dma_mosi(uint8_t id, const void *data, uint16_t len, uint32_t minc) +{ + struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi; + uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index; + + ao_dma_set_transfer(mosi_dma_index, + &stm_spi->dr, + (void *) data, + len, + (0 << STM_DMA_CCR_MEM2MEM) | + (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) | + (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) | + (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) | + (minc << STM_DMA_CCR_MINC) | + (0 << STM_DMA_CCR_PINC) | + (0 << STM_DMA_CCR_CIRC) | + (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR)); +} + +static void +ao_spi_set_dma_miso(uint8_t id, void *data, uint16_t len, uint32_t minc) +{ + struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi; + uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index; + + ao_dma_set_transfer(miso_dma_index, + &stm_spi->dr, + data, + len, + (0 << STM_DMA_CCR_MEM2MEM) | + (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) | + (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) | + (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) | + (minc << STM_DMA_CCR_MINC) | + (0 << STM_DMA_CCR_PINC) | + (0 << STM_DMA_CCR_CIRC) | + (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR)); +} + static void ao_spi_run(uint8_t id, uint8_t which, uint16_t len) { @@ -123,40 +164,15 @@ void ao_spi_send(const void *block, uint16_t len, uint8_t spi_index) { uint8_t id = AO_SPI_INDEX(spi_index); - struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi; - uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index; - uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index; /* Set up the transmit DMA to deliver data */ - ao_dma_set_transfer(mosi_dma_index, - &stm_spi->dr, - (void *) block, - len, - (0 << STM_DMA_CCR_MEM2MEM) | - (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) | - (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) | - (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) | - (1 << STM_DMA_CCR_MINC) | - (0 << STM_DMA_CCR_PINC) | - (0 << STM_DMA_CCR_CIRC) | - (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR)); + ao_spi_set_dma_mosi(id, block, len, 1); /* Set up the receive DMA -- when this is done, we know the SPI unit * is idle. Without this, we'd have to poll waiting for the BSY bit to * be cleared */ - ao_dma_set_transfer(miso_dma_index, - &stm_spi->dr, - &spi_dev_null, - len, - (0 << STM_DMA_CCR_MEM2MEM) | - (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) | - (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) | - (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) | - (0 << STM_DMA_CCR_MINC) | - (0 << STM_DMA_CCR_PINC) | - (0 << STM_DMA_CCR_CIRC) | - (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR)); + ao_spi_set_dma_miso(id, &spi_dev_null, len, 0); ao_spi_run(id, 1, len); } @@ -165,44 +181,51 @@ void ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index) { uint8_t id = AO_SPI_INDEX(spi_index); - struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi; - uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index; - uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index; /* Set up the transmit DMA to deliver data */ - ao_dma_set_transfer(mosi_dma_index, - &stm_spi->dr, - &value, - len, - (0 << STM_DMA_CCR_MEM2MEM) | - (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) | - (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) | - (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) | - (0 << STM_DMA_CCR_MINC) | - (0 << STM_DMA_CCR_PINC) | - (0 << STM_DMA_CCR_CIRC) | - (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR)); + ao_spi_set_dma_mosi(id, &value, len, 0); /* Set up the receive DMA -- when this is done, we know the SPI unit * is idle. Without this, we'd have to poll waiting for the BSY bit to * be cleared */ - ao_dma_set_transfer(miso_dma_index, - &stm_spi->dr, - &spi_dev_null, - len, - (0 << STM_DMA_CCR_MEM2MEM) | - (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) | - (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) | - (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) | - (0 << STM_DMA_CCR_MINC) | - (0 << STM_DMA_CCR_PINC) | - (0 << STM_DMA_CCR_CIRC) | - (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR)); + ao_spi_set_dma_miso(id, &spi_dev_null, len, 0); ao_spi_run(id, 3, len); } +void +ao_spi_start_bytes(uint8_t spi_index) +{ + uint8_t id = AO_SPI_INDEX(spi_index); + struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi; + + stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) | + (0 << STM_SPI_CR2_RXNEIE) | + (0 << STM_SPI_CR2_ERRIE) | + (0 << STM_SPI_CR2_SSOE) | + (0 << STM_SPI_CR2_TXDMAEN) | + (0 << STM_SPI_CR2_RXDMAEN)); + validate_spi(stm_spi, 5, 0xffff); +} + +void +ao_spi_stop_bytes(uint8_t spi_index) +{ + uint8_t id = AO_SPI_INDEX(spi_index); + struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi; + + while ((stm_spi->sr & (1 << STM_SPI_SR_TXE)) == 0) + ; + while (stm_spi->sr & (1 << STM_SPI_SR_BSY)) + ; + /* Clear the OVR flag */ + (void) stm_spi->dr; + (void) stm_spi->sr; + validate_spi(stm_spi, 6, 0xffff); + stm_spi->cr2 = 0; +} + void ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index) { @@ -235,87 +258,38 @@ void ao_spi_recv(void *block, uint16_t len, uint8_t spi_index) { uint8_t id = AO_SPI_INDEX(spi_index); - struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi; - uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index; - uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index; spi_dev_null = 0xff; /* Set up transmit DMA to make the SPI hardware actually run */ - ao_dma_set_transfer(mosi_dma_index, - &stm_spi->dr, - &spi_dev_null, - len, - (0 << STM_DMA_CCR_MEM2MEM) | - (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) | - (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) | - (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) | - (0 << STM_DMA_CCR_MINC) | - (0 << STM_DMA_CCR_PINC) | - (0 << STM_DMA_CCR_CIRC) | - (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR)); + ao_spi_set_dma_mosi(id, &spi_dev_null, len, 0); /* Set up the receive DMA to capture data */ - ao_dma_set_transfer(miso_dma_index, - &stm_spi->dr, - block, - len, - (0 << STM_DMA_CCR_MEM2MEM) | - (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) | - (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) | - (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) | - (1 << STM_DMA_CCR_MINC) | - (0 << STM_DMA_CCR_PINC) | - (0 << STM_DMA_CCR_CIRC) | - (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR)); + ao_spi_set_dma_miso(id, block, len, 1); ao_spi_run(id, 9, len); } void -ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index) +ao_spi_duplex(const void *out, void *in, uint16_t len, uint8_t spi_index) { uint8_t id = AO_SPI_INDEX(spi_index); - struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi; - uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index; - uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index; /* Set up transmit DMA to send data */ - ao_dma_set_transfer(mosi_dma_index, - &stm_spi->dr, - out, - len, - (0 << STM_DMA_CCR_MEM2MEM) | - (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) | - (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) | - (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) | - (1 << STM_DMA_CCR_MINC) | - (0 << STM_DMA_CCR_PINC) | - (0 << STM_DMA_CCR_CIRC) | - (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR)); + ao_spi_set_dma_mosi(id, out, len, 1); /* Set up the receive DMA to capture data */ - ao_dma_set_transfer(miso_dma_index, - &stm_spi->dr, - in, - len, - (0 << STM_DMA_CCR_MEM2MEM) | - (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) | - (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) | - (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) | - (1 << STM_DMA_CCR_MINC) | - (0 << STM_DMA_CCR_PINC) | - (0 << STM_DMA_CCR_CIRC) | - (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR)); + ao_spi_set_dma_miso(id, in, len, 1); + ao_spi_run(id, 11, len); } static void -ao_spi_disable_index(uint8_t spi_index) +ao_spi_disable_pin_config(uint8_t spi_pin_config) { /* Disable current config */ - switch (spi_index) { + switch (spi_pin_config) { case AO_SPI_1_PA5_PA6_PA7: stm_gpio_set(&stm_gpioa, 5, 1); stm_moder_set(&stm_gpioa, 5, STM_MODER_OUTPUT); @@ -350,11 +324,11 @@ ao_spi_disable_index(uint8_t spi_index) } static void -ao_spi_enable_index(uint8_t spi_index) +ao_spi_enable_pin_config(uint8_t spi_pin_config) { /* Enable new config */ - switch (spi_index) { + switch (spi_pin_config) { case AO_SPI_1_PA5_PA6_PA7: stm_afr_set(&stm_gpioa, 5, STM_AFR_AF5); stm_afr_set(&stm_gpioa, 6, STM_AFR_AF5); @@ -386,23 +360,26 @@ ao_spi_enable_index(uint8_t spi_index) static void ao_spi_config(uint8_t spi_index, uint32_t speed) { + uint8_t spi_pin_config = AO_SPI_PIN_CONFIG(spi_index); uint8_t id = AO_SPI_INDEX(spi_index); struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi; - if (spi_index != ao_spi_index[id]) { + if (spi_pin_config != ao_spi_pin_config[id]) { /* Disable old config */ - ao_spi_disable_index(ao_spi_index[id]); + ao_spi_disable_pin_config(ao_spi_pin_config[id]); /* Enable new config */ - ao_spi_enable_index(spi_index); + ao_spi_enable_pin_config(spi_pin_config); /* Remember current config */ - ao_spi_index[id] = spi_index; + ao_spi_pin_config[id] = spi_pin_config; } + + /* Turn the SPI transceiver on and set the mode */ stm_spi->cr1 = ((0 << STM_SPI_CR1_BIDIMODE) | /* Three wire mode */ (0 << STM_SPI_CR1_BIDIOE) | (0 << STM_SPI_CR1_CRCEN) | /* CRC disabled */ @@ -415,8 +392,8 @@ ao_spi_config(uint8_t spi_index, uint32_t speed) (1 << STM_SPI_CR1_SPE) | /* Enable SPI unit */ (speed << STM_SPI_CR1_BR) | /* baud rate to pclk/4 */ (1 << STM_SPI_CR1_MSTR) | - (0 << STM_SPI_CR1_CPOL) | /* Format 0 */ - (0 << STM_SPI_CR1_CPHA)); + (AO_SPI_CPOL(spi_index) << STM_SPI_CR1_CPOL) | /* Format */ + (AO_SPI_CPHA(spi_index) << STM_SPI_CR1_CPHA)); validate_spi(stm_spi, 13, 0); } @@ -456,7 +433,7 @@ ao_spi_channel_init(uint8_t spi_index) uint8_t id = AO_SPI_INDEX(spi_index); struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi; - ao_spi_disable_index(spi_index); + ao_spi_disable_pin_config(AO_SPI_PIN_CONFIG(spi_index)); stm_spi->cr1 = 0; stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) | @@ -538,7 +515,7 @@ ao_spi_init(void) stm_ospeedr_set(&stm_gpioe, 15, SPI_1_OSPEEDR); # endif stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SPI1EN); - ao_spi_index[0] = AO_SPI_CONFIG_NONE; + ao_spi_pin_config[0] = AO_SPI_CONFIG_NONE; ao_spi_channel_init(0); #endif @@ -556,7 +533,7 @@ ao_spi_init(void) stm_ospeedr_set(&stm_gpiod, 4, SPI_2_OSPEEDR); # endif stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_SPI2EN); - ao_spi_index[1] = AO_SPI_CONFIG_NONE; + ao_spi_pin_config[1] = AO_SPI_CONFIG_NONE; ao_spi_channel_init(1); #endif #if DEBUG