X-Git-Url: https://git.gag.com/?p=fw%2Faltos;a=blobdiff_plain;f=src%2Fdrivers%2Fao_cc1120_CC1120.h;h=21a31a89d16f6c261373b597d03d4cbd25769a61;hp=5376afd56225a60ad901239ab3ab23d1a14eabf6;hb=bea42e45952df85d61428662caefbb100465a585;hpb=f1ae622eff60e05c1f5d8f822a3cf6a85750c6cc diff --git a/src/drivers/ao_cc1120_CC1120.h b/src/drivers/ao_cc1120_CC1120.h index 5376afd5..21a31a89 100644 --- a/src/drivers/ao_cc1120_CC1120.h +++ b/src/drivers/ao_cc1120_CC1120.h @@ -21,26 +21,33 @@ * ***************************************************************/ +#ifndef AO_CC1120_AGC_GAIN_ADJUST +#define AO_CC1120_AGC_GAIN_ADJUST -80 +#endif + CC1120_SYNC3, 0xD3, /* Sync Word Configuration [31:24] */ CC1120_SYNC2, 0x91, /* Sync Word Configuration [23:16] */ CC1120_SYNC1, 0xD3, /* Sync Word Configuration [15:8] */ CC1120_SYNC0, 0x91, /* Sync Word Configuration [7:0] */ CC1120_SYNC_CFG1, /* Sync Word Detection Configuration */ - (CC1120_SYNC_CFG1_DEM_CFG_PQT_GATING_ENABLED << CC1120_SYNC_CFG1_DEM_CFG) | - (0x07 << CC1120_SYNC_CFG1_SYNC_THR), + (CC1120_SYNC_CFG1_DEM_CFG_PQT_GATING_DISABLED << CC1120_SYNC_CFG1_DEM_CFG) | + (0xc << CC1120_SYNC_CFG1_SYNC_THR), CC1120_SYNC_CFG0, (CC1120_SYNC_CFG0_SYNC_MODE_16_BITS << CC1120_SYNC_CFG0_SYNC_MODE) | - (CC1120_SYNC_CFG0_SYNC_NUM_ERROR_2 << CC1120_SYNC_CFG0_SYNC_NUM_ERROR), - CC1120_DCFILT_CFG, 0x1c, /* Digital DC Removal Configuration */ + (CC1120_SYNC_CFG0_SYNC_NUM_ERROR_DISABLED << CC1120_SYNC_CFG0_SYNC_NUM_ERROR), + CC1120_DCFILT_CFG, 0x15, /* Digital DC Removal Configuration */ CC1120_PREAMBLE_CFG1, /* Preamble Length Configuration */ (CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_4_BYTES << CC1120_PREAMBLE_CFG1_NUM_PREAMBLE) | (CC1120_PREAMBLE_CFG1_PREAMBLE_WORD_AA << CC1120_PREAMBLE_CFG1_PREAMBLE_WORD), CC1120_PREAMBLE_CFG0, - (1 << CC1120_PREAMBLE_CFG0_PQT_EN) | - (0x6 << CC1120_PREAMBLE_CFG0_PQT), - CC1120_FREQ_IF_CFG, 0x40, /* RX Mixer Frequency Configuration */ - CC1120_IQIC, 0x46, /* Digital Image Channel Compensation Configuration */ + (0 << CC1120_PREAMBLE_CFG0_PQT_EN) | + (0xe << CC1120_PREAMBLE_CFG0_PQT), + + /* Adjust PQT lower to accept fewer packets */ + + CC1120_FREQ_IF_CFG, 0x3a, /* RX Mixer Frequency Configuration */ + CC1120_IQIC, 0x00, /* Digital Image Channel Compensation Configuration */ CC1120_CHAN_BW, 0x02, /* Channel Filter Configuration */ CC1120_MDMCFG1, /* General Modem Parameter Configuration */ @@ -49,28 +56,53 @@ (0 << CC1120_MDMCFG1_MANCHESTER_EN) | (0 << CC1120_MDMCFG1_INVERT_DATA_EN) | (0 << CC1120_MDMCFG1_COLLISION_DETECT_EN) | - (CC1120_MDMCFG1_DVGA_GAIN_9 << CC1120_MDMCFG1_DVGA_GAIN) | + (CC1120_MDMCFG1_DVGA_GAIN_0 << CC1120_MDMCFG1_DVGA_GAIN) | (0 << CC1120_MDMCFG1_SINGLE_ADC_EN), - CC1120_MDMCFG0, 0x05, /* General Modem Parameter Configuration */ - - CC1120_AGC_REF, 0x20, /* AGC Reference Level Configuration */ - CC1120_AGC_CS_THR, 0x19, /* Carrier Sense Threshold Configuration */ - CC1120_AGC_GAIN_ADJUST, 0x00, /* RSSI Offset Configuration */ - CC1120_AGC_CFG3, 0x91, /* AGC Configuration */ - CC1120_AGC_CFG2, 0x20, /* AGC Configuration */ - CC1120_AGC_CFG1, 0xa9, /* AGC Configuration */ - CC1120_AGC_CFG0, 0xcf, /* AGC Configuration */ + CC1120_MDMCFG0, 0x0d, /* General Modem Parameter Configuration */ + + /* AGC reference = 10 * log10(receive BW) - 4 = 10 * log10(100e3) - 4 = 46 */ + CC1120_AGC_REF, 0x36, /* AGC Reference Level Configuration */ + + /* Carrier sense threshold - 25dB above the noise */ + CC1120_AGC_CS_THR, 25, /* Carrier Sense Threshold Configuration */ + CC1120_AGC_GAIN_ADJUST, /* RSSI Offset Configuration */ + AO_CC1120_AGC_GAIN_ADJUST, + + CC1120_AGC_CFG3, /* AGC Configuration */ + (1 << CC1120_AGC_CFG3_RSSI_STEP_THR) | + (17 << CC1120_AGC_CFG3_AGC_MIN_GAIN), + + CC1120_AGC_CFG2, /* AGC Configuration */ + (0 << CC1120_AGC_CFG2_START_PREVIOUS_GAIN_EN) | + (CC1120_AGC_CFG2_FE_PERFORMANCE_MODE_NORMAL << CC1120_AGC_CFG2_FE_PERFORMANCE_MODE) | + (0 << CC1120_AGC_CFG2_AGC_MAX_GAIN), + + CC1120_AGC_CFG1, /* AGC Configuration */ + (CC1120_AGC_CFG1_AGC_SYNC_BEHAVIOR_UPDATE_AGC_UPDATE_RSSI_SLOW << CC1120_AGC_CFG1_AGC_SYNC_BEHAVIOR) | + (CC1120_AGC_CFG1_AGC_WIN_SIZE_32 << CC1120_AGC_CFG1_AGC_WIN_SIZE) | + (CC1120_AGC_CFG1_AGC_SETTLE_WAIT_32 << CC1120_AGC_CFG1_AGC_SETTLE_WAIT), + + CC1120_AGC_CFG0, /* AGC Configuration */ + (CC1120_AGC_CFG0_AGC_HYST_LEVEL_10 << CC1120_AGC_CFG0_AGC_HYST_LEVEL) | + (CC1120_AGC_CFG0_AGC_SLEWRATE_LIMIT_60 << CC1120_AGC_CFG0_AGC_SLEWRATE_LIMIT) | + (CC1120_AGC_CFG0_RSSI_VALID_CNT_9 << CC1120_AGC_CFG0_RSSI_VALID_CNT) | + (CC1120_AGC_CFG0_AGC_ASK_DECAY_1_128 << CC1120_AGC_CFG0_AGC_ASK_DECAY), + CC1120_FIFO_CFG, /* FIFO Configuration */ (0 << CC1120_FIFO_CFG_CRC_AUTOFLUSH) | (0x40 << CC1120_FIFO_CFG_FIFO_THR), + CC1120_DEV_ADDR, 0x00, /* Device Address Configuration */ + CC1120_SETTLING_CFG, /* Frequency Synthesizer Calibration and Settling Configuration */ (CC1120_SETTLING_CFG_FS_AUTOCAL_IDLE_TO_ON << CC1120_SETTLING_CFG_FS_AUTOCAL) | - (CC1120_SETTLING_CFG_LOCK_TIME_50_20 << CC1120_SETTLING_CFG_LOCK_TIME) | + (CC1120_SETTLING_CFG_LOCK_TIME_75_30 << CC1120_SETTLING_CFG_LOCK_TIME) | (CC1120_SETTLING_CFG_FSREG_TIME_60 << CC1120_SETTLING_CFG_FSREG_TIME), + CC1120_FS_CFG, /* Frequency Synthesizer Configuration */ (1 << CC1120_FS_CFG_LOCK_EN) | (CC1120_FS_CFG_FSD_BANDSELECT_410_480 << CC1120_FS_CFG_FSD_BANDSELECT), + CC1120_WOR_CFG1, 0x08, /* eWOR Configuration, Reg 1 */ CC1120_WOR_CFG0, 0x21, /* eWOR Configuration, Reg 0 */ CC1120_WOR_EVENT0_MSB, 0x00, /* Event 0 Configuration */ @@ -80,16 +112,16 @@ CC1120_PKT_CFG1, 0x45, /* Packet Configuration, Reg 1 */ CC1120_PKT_CFG0, 0x00, /* Packet Configuration, Reg 0 */ #endif - CC1120_RFEND_CFG1, 0x0f, /* RFEND Configuration, Reg 1 */ + CC1120_RFEND_CFG1, 0x0e, /* RFEND Configuration, Reg 1 */ CC1120_RFEND_CFG0, 0x00, /* RFEND Configuration, Reg 0 */ // CC1120_PA_CFG2, 0x3f, /* Power Amplifier Configuration, Reg 2 */ - CC1120_PA_CFG2, 0x04, /* Power Amplifier Configuration, Reg 2 */ + CC1120_PA_CFG2, 0x3f, /* Power Amplifier Configuration, Reg 2 */ CC1120_PA_CFG1, 0x56, /* Power Amplifier Configuration, Reg 1 */ CC1120_PA_CFG0, 0x7b, /* Power Amplifier Configuration, Reg 0 */ CC1120_PKT_LEN, 0xff, /* Packet Length Configuration */ CC1120_IF_MIX_CFG, 0x00, /* IF Mix Configuration */ - CC1120_FREQOFF_CFG, 0x22, /* Frequency Offset Correction Configuration */ - CC1120_TOC_CFG, 0x0b, /* Timing Offset Correction Configuration */ + CC1120_FREQOFF_CFG, 0x20, /* Frequency Offset Correction Configuration */ + CC1120_TOC_CFG, 0x0a, /* Timing Offset Correction Configuration */ CC1120_MARC_SPARE, 0x00, /* MARC Spare */ CC1120_ECG_CFG, 0x00, /* External Clock Frequency Configuration */ CC1120_SOFT_TX_DATA_CFG, 0x00, /* Soft TX Data Configuration */ @@ -138,7 +170,7 @@ CC1120_XOSC4, 0xa0, /* Crystal Oscillator Configuration, Reg 4 */ CC1120_XOSC3, 0x03, /* Crystal Oscillator Configuration, Reg 3 */ CC1120_XOSC2, 0x04, /* Crystal Oscillator Configuration, Reg 2 */ - CC1120_XOSC1, 0x01, /* Crystal Oscillator Configuration, Reg 1 */ + CC1120_XOSC1, 0x03, /* Crystal Oscillator Configuration, Reg 1 */ CC1120_XOSC0, 0x00, /* Crystal Oscillator Configuration, Reg 0 */ CC1120_ANALOG_SPARE, 0x00, /* */ CC1120_PA_CFG3, 0x00, /* Power Amplifier Configuration, Reg 3 */ @@ -167,31 +199,10 @@ CC1120_AGC_GAIN2, 0xd1, /* AGC Gain, Reg 2 */ CC1120_AGC_GAIN1, 0x00, /* AGC Gain, Reg 1 */ CC1120_AGC_GAIN0, 0x3f, /* AGC Gain, Reg 0 */ - CC1120_SOFT_RX_DATA_OUT, 0x00, /* Soft Decision Symbol Data */ - CC1120_SOFT_TX_DATA_IN, 0x00, /* Soft TX Data Input Register */ - CC1120_ASK_SOFT_RX_DATA, 0x30, /* AGC ASK Soft Decision Output */ CC1120_RNDGEN, 0x7f, /* Random Number Value */ - CC1120_MAGN2, 0x00, /* Signal Magnitude after CORDIC [16] */ - CC1120_MAGN1, 0x00, /* Signal Magnitude after CORDIC [15:8] */ - CC1120_MAGN0, 0x00, /* Signal Magnitude after CORDIC [7:0] */ - CC1120_ANG1, 0x00, /* Signal Angular after CORDIC [9:8] */ - CC1120_ANG0, 0x00, /* Signal Angular after CORDIC [7:0] */ - CC1120_CHFILT_I2, 0x08, /* Channel Filter Data Real Part [18:16] */ - CC1120_CHFILT_I1, 0x00, /* Channel Filter Data Real Part [15:8] */ - CC1120_CHFILT_I0, 0x00, /* Channel Filter Data Real Part [7:0] */ - CC1120_CHFILT_Q2, 0x00, /* Channel Filter Data Imaginary Part [18:16] */ - CC1120_CHFILT_Q1, 0x00, /* Channel Filter Data Imaginary Part [15:8] */ - CC1120_CHFILT_Q0, 0x00, /* Channel Filter Data Imaginary Part [7:0] */ - CC1120_GPIO_STATUS, 0x00, /* GPIO Status */ CC1120_FSCAL_CTRL, 0x01, /* */ CC1120_PHASE_ADJUST, 0x00, /* */ - CC1120_PARTNUMBER, 0x00, /* Part Number */ - CC1120_PARTVERSION, 0x00, /* Part Revision */ CC1120_SERIAL_STATUS, 0x00, /* Serial Status */ - CC1120_RX_STATUS, 0x01, /* RX Status */ - CC1120_TX_STATUS, 0x00, /* TX Status */ - CC1120_MARC_STATUS1, 0x00, /* MARC Status, Reg 1 */ - CC1120_MARC_STATUS0, 0x00, /* MARC Status, Reg 0 */ CC1120_PA_IFAMP_TEST, 0x00, /* */ CC1120_FSRF_TEST, 0x00, /* */ CC1120_PRE_TEST, 0x00, /* */