X-Git-Url: https://git.gag.com/?p=fw%2Faltos;a=blobdiff_plain;f=src%2Fcc1111%2Fcc1111.h;h=7d7c3a209669447422cd1336da3b49d14ab78524;hp=11ea8bbb2eb8f3a259a92fa60634d3e31be84747;hb=1085ec5d57e0ed5d132f2bbdac1a0b6a32c0ab4a;hpb=1c344b760776cd5d8c0297d8db9bf02687381b4e diff --git a/src/cc1111/cc1111.h b/src/cc1111/cc1111.h index 11ea8bbb..7d7c3a20 100644 --- a/src/cc1111/cc1111.h +++ b/src/cc1111/cc1111.h @@ -5,7 +5,8 @@ This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - the Free Software Foundation; version 2 of the License. + the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -42,14 +43,14 @@ __sfr __at 0xA8 IEN0; /* Interrupt Enable 0 Register */ -sbit __at 0xA8 RFTXRXIE; /* RF TX/RX done interrupt enable */ -sbit __at 0xA9 ADCIE; /* ADC interrupt enable */ -sbit __at 0xAA URX0IE; /* USART0 RX interrupt enable */ -sbit __at 0xAB URX1IE; /* USART1 RX interrupt enable (shared with I2S RX) */ -sbit __at 0xAB I2SRXIE; /* I2S RX interrupt enable (shared with USART1 RX) */ -sbit __at 0xAC ENCIE; /* AES encryption/decryption interrupt enable */ -sbit __at 0xAD STIE; /* Sleep Timer interrupt enable */ -sbit __at 0xAF EA; /* Enable All */ +__sbit __at 0xA8 RFTXRXIE; /* RF TX/RX done interrupt enable */ +__sbit __at 0xA9 ADCIE; /* ADC interrupt enable */ +__sbit __at 0xAA URX0IE; /* USART0 RX interrupt enable */ +__sbit __at 0xAB URX1IE; /* USART1 RX interrupt enable (shared with I2S RX) */ +__sbit __at 0xAB I2SRXIE; /* I2S RX interrupt enable (shared with USART1 RX) */ +__sbit __at 0xAC ENCIE; /* AES encryption/decryption interrupt enable */ +__sbit __at 0xAD STIE; /* Sleep Timer interrupt enable */ +__sbit __at 0xAF EA; /* Enable All */ #define IEN0_EA (1 << 7) #define IEN0_STIE (1 << 5) @@ -135,11 +136,11 @@ __sfr __at 0x87 PCON; /* Power Mode Control Register */ */ __sfr __at 0x88 TCON; /* CPU Interrupt Flag 1 */ -sbit __at 0x8F URX1IF; /* USART1 RX interrupt flag. Automatically cleared */ -sbit __at 0x8F I2SRXIF; /* I2S RX interrupt flag. Automatically cleared */ -sbit __at 0x8D ADCIF; /* ADC interrupt flag. Automatically cleared */ -sbit __at 0x8B URX0IF; /* USART0 RX interrupt flag. Automatically cleared */ -sbit __at 0x89 RFTXRXIF; /* RF TX/RX complete interrupt flag. Automatically cleared */ +__sbit __at 0x8F URX1IF; /* USART1 RX interrupt flag. Automatically cleared */ +__sbit __at 0x8F I2SRXIF; /* I2S RX interrupt flag. Automatically cleared */ +__sbit __at 0x8D ADCIF; /* ADC interrupt flag. Automatically cleared */ +__sbit __at 0x8B URX0IF; /* USART0 RX interrupt flag. Automatically cleared */ +__sbit __at 0x89 RFTXRXIF; /* RF TX/RX complete interrupt flag. Automatically cleared */ #define TCON_URX1IF (1 << 7) #define TCON_I2SRXIF (1 << 7) @@ -152,8 +153,8 @@ sbit __at 0x89 RFTXRXIF; /* RF TX/RX complete interrupt flag. Automatically clea */ __sfr __at 0x98 S0CON; /* CPU Interrupt Flag 2 */ -sbit __at 0x98 ENCIF_0; /* AES interrupt 0. */ -sbit __at 0x99 ENCIF_1; /* AES interrupt 1. */ +__sbit __at 0x98 ENCIF_0; /* AES interrupt 0. */ +__sbit __at 0x99 ENCIF_1; /* AES interrupt 1. */ #define S0CON_ENCIF_1 (1 << 1) #define S0CON_ENCIF_0 (1 << 0) @@ -171,13 +172,13 @@ __sfr __at 0x9B S1CON; /* CPU Interrupt Flag 3 */ */ __sfr __at 0xC0 IRCON; /* CPU Interrupt Flag 4 */ -sbit __at 0xC0 DMAIF; /* DMA complete interrupt flag */ -sbit __at 0xC1 T1IF; /* Timer 1 interrupt flag. Automatically cleared */ -sbit __at 0xC2 T2IF; /* Timer 2 interrupt flag. Automatically cleared */ -sbit __at 0xC3 T3IF; /* Timer 3 interrupt flag. Automatically cleared */ -sbit __at 0xC4 T4IF; /* Timer 4 interrupt flag. Automatically cleared */ -sbit __at 0xC5 P0IF; /* Port0 interrupt flag */ -sbit __at 0xC7 STIF; /* Sleep Timer interrupt flag */ +__sbit __at 0xC0 DMAIF; /* DMA complete interrupt flag */ +__sbit __at 0xC1 T1IF; /* Timer 1 interrupt flag. Automatically cleared */ +__sbit __at 0xC2 T2IF; /* Timer 2 interrupt flag. Automatically cleared */ +__sbit __at 0xC3 T3IF; /* Timer 3 interrupt flag. Automatically cleared */ +__sbit __at 0xC4 T4IF; /* Timer 4 interrupt flag. Automatically cleared */ +__sbit __at 0xC5 P0IF; /* Port0 interrupt flag */ +__sbit __at 0xC7 STIF; /* Sleep Timer interrupt flag */ #define IRCON_DMAIF (1 << 0) /* DMA complete interrupt flag */ #define IRCON_T1IF (1 << 1) /* Timer 1 interrupt flag. Automatically cleared */ @@ -192,13 +193,13 @@ sbit __at 0xC7 STIF; /* Sleep Timer interrupt flag */ */ __sfr __at 0xE8 IRCON2; /* CPU Interrupt Flag 5 */ -sbit __at 0xE8 USBIF; /* USB interrupt flag (shared with Port2) */ -sbit __at 0xE8 P2IF; /* Port2 interrupt flag (shared with USB) */ -sbit __at 0xE9 UTX0IF; /* USART0 TX interrupt flag */ -sbit __at 0xEA UTX1IF; /* USART1 TX interrupt flag (shared with I2S TX) */ -sbit __at 0xEA I2STXIF; /* I2S TX interrupt flag (shared with USART1 TX) */ -sbit __at 0xEB P1IF; /* Port1 interrupt flag */ -sbit __at 0xEC WDTIF; /* Watchdog timer interrupt flag */ +__sbit __at 0xE8 USBIF; /* USB interrupt flag (shared with Port2) */ +__sbit __at 0xE8 P2IF; /* Port2 interrupt flag (shared with USB) */ +__sbit __at 0xE9 UTX0IF; /* USART0 TX interrupt flag */ +__sbit __at 0xEA UTX1IF; /* USART1 TX interrupt flag (shared with I2S TX) */ +__sbit __at 0xEA I2STXIF; /* I2S TX interrupt flag (shared with USART1 TX) */ +__sbit __at 0xEB P1IF; /* Port1 interrupt flag */ +__sbit __at 0xEC WDTIF; /* Watchdog timer interrupt flag */ #define IRCON2_USBIF (1 << 0) /* USB interrupt flag (shared with Port2) */ #define IRCON2_P2IF (1 << 0) /* Port2 interrupt flag (shared with USB) */ @@ -442,12 +443,12 @@ __xdata __at (0xde17) volatile uint8_t USBCNTH; __xdata __at (0xde20) volatile uint8_t USBFIFO[12]; /* ADC Data register, low and high */ -__sfr at 0xBA ADCL; -__sfr at 0xBB ADCH; +__sfr __at 0xBA ADCL; +__sfr __at 0xBB ADCH; __xdata __at (0xDFBA) volatile uint16_t ADCXDATA; /* ADC Control Register 1 */ -__sfr at 0xB4 ADCCON1; +__sfr __at 0xB4 ADCCON1; # define ADCCON1_EOC (1 << 7) /* conversion complete */ # define ADCCON1_ST (1 << 6) /* start conversion */ @@ -463,7 +464,7 @@ __sfr at 0xB4 ADCCON1; # define ADCCON1_RCTRL_CLOCK_LFSR (1 << 2) /* Clock the LFSR once */ /* ADC Control Register 2 */ -__sfr at 0xB5 ADCCON2; +__sfr __at 0xB5 ADCCON2; # define ADCCON2_SREF_MASK (3 << 6) /* reference voltage */ # define ADCCON2_SREF_1_25V (0 << 6) /* internal 1.25V */ @@ -498,7 +499,7 @@ __sfr at 0xB5 ADCCON2; /* ADC Control Register 3 */ -__sfr at 0xB6 ADCCON3; +__sfr __at 0xB6 ADCCON3; # define ADCCON3_EREF_MASK (3 << 6) /* extra conversion reference */ # define ADCCON3_EREF_1_25 (0 << 6) /* internal 1.25V */ @@ -533,13 +534,13 @@ __sfr at 0xB6 ADCCON3; * ADC configuration register, this selects which * GPIO pins are to be used as ADC inputs */ -__sfr at 0xF2 ADCCFG; +__sfr __at 0xF2 ADCCFG; /* * Watchdog timer */ -__sfr at 0xc9 WDCTL; +__sfr __at 0xc9 WDCTL; #define WDCTL_CLEAR_FIRST (0xa << 4) #define WDCTL_CLEAR_SECOND (0x5 << 4) @@ -556,9 +557,9 @@ __sfr at 0xc9 WDCTL; * Pin selectors, these set which pins are * using their peripheral function */ -__sfr at 0xF3 P0SEL; -__sfr at 0xF4 P1SEL; -__sfr at 0xF5 P2SEL; +__sfr __at 0xF3 P0SEL; +__sfr __at 0xF4 P1SEL; +__sfr __at 0xF5 P2SEL; #define P2SEL_PRI3P1_USART0 (0 << 6) #define P2SEL_PRI3P1_USART1 (1 << 6) @@ -585,9 +586,9 @@ __sfr at 0xF5 P2SEL; /* * For pins used as GPIOs, these set which are used as outputs */ -__sfr at 0xFD P0DIR; -__sfr at 0xFE P1DIR; -__sfr at 0xFF P2DIR; +__sfr __at 0xFD P0DIR; +__sfr __at 0xFE P1DIR; +__sfr __at 0xFF P2DIR; #define P2DIR_PRIP0_USART0_USART1 (0 << 6) #define P2DIR_PRIP0_USART1_USART0 (1 << 6) @@ -595,7 +596,7 @@ __sfr at 0xFF P2DIR; #define P2DIR_PRIP0_TIMER1_2_USART0 (3 << 6) #define P2DIR_PRIP0_MASK (3 << 6) -__sfr at 0x8F P0INP; +__sfr __at 0x8F P0INP; /* Select between tri-state and pull up/down * for pins P0_0 - P0_7. @@ -617,7 +618,7 @@ __sfr at 0x8F P0INP; #define P0INP_MDP0_0_PULL (0 << 0) #define P0INP_MDP0_0_TRISTATE (1 << 0) -__sfr at 0xF6 P1INP; +__sfr __at 0xF6 P1INP; /* Select between tri-state and pull up/down * for pins P1_2 - P1_7. Pins P1_0 and P1_1 are @@ -636,7 +637,7 @@ __sfr at 0xF6 P1INP; #define P1INP_MDP1_2_PULL (0 << 2) #define P1INP_MDP1_2_TRISTATE (1 << 2) -__sfr at 0xF7 P2INP; +__sfr __at 0xF7 P2INP; /* P2INP has three extra bits which are used to choose * between pull-up and pull-down when they are not tri-stated */ @@ -662,13 +663,13 @@ __sfr at 0xF7 P2INP; #define P2INP_MDP2_0_TRISTATE (1 << 0) /* GPIO interrupt status flags */ -__sfr at 0x89 P0IFG; -__sfr at 0x8A P1IFG; -__sfr at 0x8B P2IFG; +__sfr __at 0x89 P0IFG; +__sfr __at 0x8A P1IFG; +__sfr __at 0x8B P2IFG; #define P0IFG_USB_RESUME (1 << 7) -__sfr at 0x8C PICTL; +__sfr __at 0x8C PICTL; #define PICTL_P2IEN (1 << 5) #define PICTL_P0IENH (1 << 4) #define PICTL_P0IENL (1 << 3) @@ -677,35 +678,35 @@ __sfr at 0x8C PICTL; #define PICTL_P0ICON (1 << 0) /* GPIO pins */ -__sfr at 0x80 P0; - -sbit at 0x80 P0_0; -sbit at 0x81 P0_1; -sbit at 0x82 P0_2; -sbit at 0x83 P0_3; -sbit at 0x84 P0_4; -sbit at 0x85 P0_5; -sbit at 0x86 P0_6; -sbit at 0x87 P0_7; - -__sfr at 0x90 P1; - -sbit at 0x90 P1_0; -sbit at 0x91 P1_1; -sbit at 0x92 P1_2; -sbit at 0x93 P1_3; -sbit at 0x94 P1_4; -sbit at 0x95 P1_5; -sbit at 0x96 P1_6; -sbit at 0x97 P1_7; - -__sfr at 0xa0 P2; - -sbit at 0xa0 P2_0; -sbit at 0xa1 P2_1; -sbit at 0xa2 P2_2; -sbit at 0xa3 P2_3; -sbit at 0xa4 P2_4; +__sfr __at 0x80 P0; + +__sbit __at 0x80 P0_0; +__sbit __at 0x81 P0_1; +__sbit __at 0x82 P0_2; +__sbit __at 0x83 P0_3; +__sbit __at 0x84 P0_4; +__sbit __at 0x85 P0_5; +__sbit __at 0x86 P0_6; +__sbit __at 0x87 P0_7; + +__sfr __at 0x90 P1; + +__sbit __at 0x90 P1_0; +__sbit __at 0x91 P1_1; +__sbit __at 0x92 P1_2; +__sbit __at 0x93 P1_3; +__sbit __at 0x94 P1_4; +__sbit __at 0x95 P1_5; +__sbit __at 0x96 P1_6; +__sbit __at 0x97 P1_7; + +__sfr __at 0xa0 P2; + +__sbit __at 0xa0 P2_0; +__sbit __at 0xa1 P2_1; +__sbit __at 0xa2 P2_2; +__sbit __at 0xa3 P2_3; +__sbit __at 0xa4 P2_4; /* DMA controller */ struct cc_dma_channel { @@ -794,7 +795,7 @@ struct cc_dma_channel { * DMAARM - DMA Channel Arm */ -__sfr at 0xD6 DMAARM; +__sfr __at 0xD6 DMAARM; # define DMAARM_ABORT (1 << 7) # define DMAARM_DMAARM4 (1 << 4) @@ -807,7 +808,7 @@ __sfr at 0xD6 DMAARM; * DMAREQ - DMA Channel Start Request and Status */ -__sfr at 0xD7 DMAREQ; +__sfr __at 0xD7 DMAREQ; # define DMAREQ_DMAREQ4 (1 << 4) # define DMAREQ_DMAREQ3 (1 << 3) @@ -819,21 +820,21 @@ __sfr at 0xD7 DMAREQ; * DMA configuration 0 address */ -__sfr at 0xD5 DMA0CFGH; -__sfr at 0xD4 DMA0CFGL; +__sfr __at 0xD5 DMA0CFGH; +__sfr __at 0xD4 DMA0CFGL; /* * DMA configuration 1-4 address */ -__sfr at 0xD3 DMA1CFGH; -__sfr at 0xD2 DMA1CFGL; +__sfr __at 0xD3 DMA1CFGH; +__sfr __at 0xD2 DMA1CFGL; /* * DMAIRQ - DMA Interrupt Flag */ -__sfr at 0xD1 DMAIRQ; +__sfr __at 0xD1 DMAIRQ; # define DMAIRQ_DMAIF4 (1 << 4) # define DMAIRQ_DMAIF3 (1 << 3) @@ -846,8 +847,8 @@ __sfr at 0xD1 DMAIRQ; */ /* USART config/status registers */ -__sfr at 0x86 U0CSR; -__sfr at 0xF8 U1CSR; +__sfr __at 0x86 U0CSR; +__sfr __at 0xF8 U1CSR; # define UxCSR_MODE_UART (1 << 7) # define UxCSR_MODE_SPI (0 << 7) @@ -861,8 +862,8 @@ __sfr at 0xF8 U1CSR; # define UxCSR_ACTIVE (1 << 0) /* UART configuration registers */ -__sfr at 0xc4 U0UCR; -__sfr at 0xfb U1UCR; +__sfr __at 0xc4 U0UCR; +__sfr __at 0xfb U1UCR; # define UxUCR_FLUSH (1 << 7) # define UxUCR_FLOW_DISABLE (0 << 6) @@ -881,8 +882,8 @@ __sfr at 0xfb U1UCR; # define UxUCR_START_HIGH (1 << 0) /* USART General configuration registers (mostly SPI) */ -__sfr at 0xc5 U0GCR; -__sfr at 0xfc U1GCR; +__sfr __at 0xc5 U0GCR; +__sfr __at 0xfc U1GCR; # define UxGCR_CPOL_NEGATIVE (0 << 7) # define UxGCR_CPOL_POSITIVE (1 << 7) @@ -894,18 +895,18 @@ __sfr at 0xfc U1GCR; # define UxGCR_BAUD_E_SHIFT 0 /* USART data registers */ -__sfr at 0xc1 U0DBUF; +__sfr __at 0xc1 U0DBUF; __xdata __at (0xDFC1) volatile uint8_t U0DBUFXADDR; -__sfr at 0xf9 U1DBUF; +__sfr __at 0xf9 U1DBUF; __xdata __at (0xDFF9) volatile uint8_t U1DBUFXADDR; /* USART baud rate registers, M value */ -__sfr at 0xc2 U0BAUD; -__sfr at 0xfa U1BAUD; +__sfr __at 0xc2 U0BAUD; +__sfr __at 0xfa U1BAUD; /* Flash controller */ -__sfr at 0xAE FCTL; +__sfr __at 0xAE FCTL; #define FCTL_BUSY (1 << 7) #define FCTL_SWBSY (1 << 6) #define FCTL_CONTRD_ENABLE (1 << 4) @@ -913,22 +914,22 @@ __sfr at 0xAE FCTL; #define FCTL_ERASE (1 << 0) /* Flash write data. Write two bytes here */ -__sfr at 0xAF FWDATA; +__sfr __at 0xAF FWDATA; __xdata __at (0xDFAF) volatile uint8_t FWDATAXADDR; /* Flash write/erase address */ -__sfr at 0xAD FADDRH; -__sfr at 0xAC FADDRL; +__sfr __at 0xAD FADDRH; +__sfr __at 0xAC FADDRL; /* Flash timing */ -__sfr at 0xAB FWT; +__sfr __at 0xAB FWT; /* Radio */ -__sfr at 0xD9 RFD; -__xdata at (0xDFD9) volatile uint8_t RFDXADDR; +__sfr __at 0xD9 RFD; +__xdata __at (0xDFD9) volatile uint8_t RFDXADDR; -__sfr at 0xE9 RFIF; +__sfr __at 0xE9 RFIF; #define RFIF_IM_TXUNF (1 << 7) #define RFIF_IM_RXOVF (1 << 6) #define RFIF_IM_TIMEOUT (1 << 5) @@ -938,7 +939,7 @@ __sfr at 0xE9 RFIF; #define RFIF_IM_CCA (1 << 1) #define RFIF_IM_SFD (1 << 0) -__sfr at 0x91 RFIM; +__sfr __at 0x91 RFIM; #define RFIM_IM_TXUNF (1 << 7) #define RFIM_IM_RXOVF (1 << 6) #define RFIM_IM_TIMEOUT (1 << 5) @@ -948,7 +949,7 @@ __sfr at 0x91 RFIM; #define RFIM_IM_CCA (1 << 1) #define RFIM_IM_SFD (1 << 0) -__sfr at 0xE1 RFST; +__sfr __at 0xE1 RFST; #define RFST_SFSTXON 0x00 #define RFST_SCAL 0x01 @@ -1165,12 +1166,73 @@ __xdata __at (0xdf16) uint8_t RF_BSCFG; __xdata __at (0xdf17) uint8_t RF_AGCCTRL2; #define RF_AGCCTRL2_OFF 0x17 +#define RF_AGCCTRL2_MAX_DVGA_GAIN_ALL (0 << 6) +#define RF_AGCCTRL2_MAX_DVGA_GAIN_BUT_1 (1 << 6) +#define RF_AGCCTRL2_MAX_DVGA_GAIN_BUT_2 (2 << 6) +#define RF_AGCCTRL2_MAX_DVGA_GAIN_BUT_3 (3 << 6) +#define RF_AGCCTRL2_MAX_LNA_GAIN_0 (0 << 3) +#define RF_AGCCTRL2_MAX_LNA_GAIN_2_6 (1 << 3) +#define RF_AGCCTRL2_MAX_LNA_GAIN_6_1 (2 << 3) +#define RF_AGCCTRL2_MAX_LNA_GAIN_7_4 (3 << 3) +#define RF_AGCCTRL2_MAX_LNA_GAIN_9_2 (4 << 3) +#define RF_AGCCTRL2_MAX_LNA_GAIN_11_5 (5 << 3) +#define RF_AGCCTRL2_MAX_LNA_GAIN_14_6 (6 << 3) +#define RF_AGCCTRL2_MAX_LNA_GAIN_17_1 (7 << 3) +#define RF_AGCCTRL2_MAGN_TARGET_24dB (0 << 0) +#define RF_AGCCTRL2_MAGN_TARGET_27dB (1 << 0) +#define RF_AGCCTRL2_MAGN_TARGET_30dB (2 << 0) +#define RF_AGCCTRL2_MAGN_TARGET_33dB (3 << 0) +#define RF_AGCCTRL2_MAGN_TARGET_36dB (4 << 0) +#define RF_AGCCTRL2_MAGN_TARGET_38dB (5 << 0) +#define RF_AGCCTRL2_MAGN_TARGET_40dB (6 << 0) +#define RF_AGCCTRL2_MAGN_TARGET_42dB (7 << 0) + __xdata __at (0xdf18) uint8_t RF_AGCCTRL1; #define RF_AGCCTRL1_OFF 0x18 +#define RF_AGCCTRL1_AGC_LNA_PRIORITY_0 (0 << 6) +#define RF_AGCCTRL1_AGC_LNA_PRIORITY_1 (1 << 6) +#define RF_AGCCTRL1_CARRIER_SENSE_REL_THR_DISABLE (0 << 4) +#define RF_AGCCTRL1_CARRIER_SENSE_REL_THR_6DB (1 << 4) +#define RF_AGCCTRL1_CARRIER_SENSE_REL_THR_10DB (2 << 4) +#define RF_AGCCTRL1_CARRIER_SENSE_REL_THR_14DB (3 << 4) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_DISABLE (0x8 << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_7DB_BELOW (0x9 << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_6DB_BELOW (0xa << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_5DB_BELOW (0xb << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_4DB_BELOW (0xc << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_3DB_BELOW (0xd << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_2DB_BELOW (0xe << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_1DB_BELOW (0xf << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_0DB (0x0 << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_1DB_ABOVE (0x1 << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_2DB_ABOVE (0x2 << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_3DB_ABOVE (0x3 << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_4DB_ABOVE (0x4 << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_5DB_ABOVE (0x5 << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_6DB_ABOVE (0x6 << 0) +#define RF_AGCCTRL1_CARRIER_SENSE_ABS_THR_7DB_ABOVE (0x7 << 0) + __xdata __at (0xdf19) uint8_t RF_AGCCTRL0; #define RF_AGCCTRL0_OFF 0x19 +#define RF_AGCCTRL0_HYST_LEVEL_NONE (0 << 6) +#define RF_AGCCTRL0_HYST_LEVEL_LOW (1 << 6) +#define RF_AGCCTRL0_HYST_LEVEL_MEDIUM (2 << 6) +#define RF_AGCCTRL0_HYST_LEVEL_HIGH (3 << 6) +#define RF_AGCCTRL0_WAIT_TIME_8 (0 << 4) +#define RF_AGCCTRL0_WAIT_TIME_16 (1 << 4) +#define RF_AGCCTRL0_WAIT_TIME_24 (2 << 4) +#define RF_AGCCTRL0_WAIT_TIME_32 (3 << 4) +#define RF_AGCCTRL0_AGC_FREEZE_NORMAL (0 << 2) +#define RF_AGCCTRL0_AGC_FREEZE_SYNC (1 << 2) +#define RF_AGCCTRL0_AGC_FREEZE_MANUAL_ANALOG (2 << 2) +#define RF_AGCCTRL0_AGC_FREEZE_MANUAL_BOTH (3 << 2) +#define RF_AGCCTRL0_FILTER_LENGTH_8 (0 << 0) +#define RF_AGCCTRL0_FILTER_LENGTH_16 (1 << 0) +#define RF_AGCCTRL0_FILTER_LENGTH_32 (2 << 0) +#define RF_AGCCTRL0_FILTER_LENGTH_64 (3 << 0) + __xdata __at (0xdf1a) uint8_t RF_FREND1; #define RF_FREND1_OFF 0x1a @@ -1305,12 +1367,12 @@ __xdata __at (0xdf3d) uint8_t RF_VCO_VC_DAC; /* AES engine */ -__sfr at 0xB1 ENCDI; -__sfr at 0xB2 ENCDO; -__xdata at (0xDFB1) volatile uint8_t ENCDIXADDR; -__xdata at (0xDFB2) volatile uint8_t ENCDOXADDR; +__sfr __at 0xB1 ENCDI; +__sfr __at 0xB2 ENCDO; +__xdata __at (0xDFB1) volatile uint8_t ENCDIXADDR; +__xdata __at (0xDFB2) volatile uint8_t ENCDOXADDR; -__sfr at 0xB3 ENCCCS; +__sfr __at 0xB3 ENCCCS; #define ENCCCS_MODE_CBC (0 << 4) #define ENCCCS_MODE_CFB (1 << 4)