X-Git-Url: https://git.gag.com/?p=fw%2Faltos;a=blobdiff_plain;f=src%2Fao_ee.c;h=36c8a1000c2c582c5dbd2963100723566e2bafe3;hp=26cfb7fd4cb6a13451a20a529473d0213160c61b;hb=9f7296b3feab872bf51fc369ade69cc1e7cf7a3f;hpb=51c410c1c952e0e9bcf1b2c438813de63753be5f

diff --git a/src/ao_ee.c b/src/ao_ee.c
index 26cfb7fd..36c8a100 100644
--- a/src/ao_ee.c
+++ b/src/ao_ee.c
@@ -25,15 +25,8 @@
 #define EE_CS		P1_2
 #define EE_CS_INDEX	2
 
-__xdata uint8_t ao_ee_dma_in_done;
-__xdata uint8_t ao_ee_dma_out_done;
 __xdata uint8_t ao_ee_mutex;
 
-uint8_t	ao_ee_dma_out_id;
-uint8_t ao_ee_dma_in_id;
-
-static __xdata uint8_t	ao_ee_const = 0xff;
-
 #define ao_ee_delay() do { \
 	_asm nop _endasm; \
 	_asm nop _endasm; \
@@ -54,82 +47,6 @@ void ao_ee_cs_high(void)
 	ao_ee_delay();
 }
 
-/* Send bytes over SPI.
- *
- * This sets up two DMA engines, one writing the data and another reading
- * bytes coming back.  We use the bytes coming back to tell when the transfer
- * is complete, as the transmit register is double buffered and hence signals
- * completion one byte before the transfer is actually complete
- */
-static void
-ao_ee_send(void __xdata *block, uint16_t len)
-{
-	ao_dma_set_transfer(ao_ee_dma_in_id,
-			    &U0DBUFXADDR,
-			    &ao_ee_const,
-			    len,
-			    DMA_CFG0_WORDSIZE_8 |
-			    DMA_CFG0_TMODE_SINGLE |
-			    DMA_CFG0_TRIGGER_URX0,
-			    DMA_CFG1_SRCINC_0 |
-			    DMA_CFG1_DESTINC_0 |
-			    DMA_CFG1_PRIORITY_NORMAL);
-
-	ao_dma_set_transfer(ao_ee_dma_out_id,
-			    block,
-			    &U0DBUFXADDR,
-			    len,
-			    DMA_CFG0_WORDSIZE_8 |
-			    DMA_CFG0_TMODE_SINGLE |
-			    DMA_CFG0_TRIGGER_UTX0,
-			    DMA_CFG1_SRCINC_1 |
-			    DMA_CFG1_DESTINC_0 |
-			    DMA_CFG1_PRIORITY_NORMAL);
-
-	ao_dma_start(ao_ee_dma_in_id);
-	ao_dma_start(ao_ee_dma_out_id);
-	ao_dma_trigger(ao_ee_dma_out_id);
-	__critical while (!ao_ee_dma_in_done)
-		ao_sleep(&ao_ee_dma_in_done);
-}
-
-/* Receive bytes over SPI.
- *
- * This sets up tow DMA engines, one reading the data and another
- * writing constant values to the SPI transmitter as that is what
- * clocks the data coming in.
- */
-static void
-ao_ee_recv(void __xdata *block, uint16_t len)
-{
-	ao_dma_set_transfer(ao_ee_dma_in_id,
-			    &U0DBUFXADDR,
-			    block,
-			    len,
-			    DMA_CFG0_WORDSIZE_8 |
-			    DMA_CFG0_TMODE_SINGLE |
-			    DMA_CFG0_TRIGGER_URX0,
-			    DMA_CFG1_SRCINC_0 |
-			    DMA_CFG1_DESTINC_1 |
-			    DMA_CFG1_PRIORITY_NORMAL);
-
-	ao_dma_set_transfer(ao_ee_dma_out_id,
-			    &ao_ee_const,
-			    &U0DBUFXADDR,
-			    len,
-			    DMA_CFG0_WORDSIZE_8 |
-			    DMA_CFG0_TMODE_SINGLE |
-			    DMA_CFG0_TRIGGER_UTX0,
-			    DMA_CFG1_SRCINC_0 |
-			    DMA_CFG1_DESTINC_0 |
-			    DMA_CFG1_PRIORITY_NORMAL);
-
-	ao_dma_start(ao_ee_dma_in_id);
-	ao_dma_start(ao_ee_dma_out_id);
-	ao_dma_trigger(ao_ee_dma_out_id);
-	__critical while (!ao_ee_dma_in_done)
-		ao_sleep(&ao_ee_dma_in_done);
-}
 
 #define EE_BLOCK	256
 
@@ -143,7 +60,7 @@ ao_ee_write_enable(void)
 {
 	ao_ee_cs_low();
 	ao_ee_instruction.instruction = EE_WREN;
-	ao_ee_send(&ao_ee_instruction, 1);
+	ao_spi_send(&ao_ee_instruction, 1);
 	ao_ee_cs_high();
 }
 
@@ -152,8 +69,8 @@ ao_ee_rdsr(void)
 {
 	ao_ee_cs_low();
 	ao_ee_instruction.instruction = EE_RDSR;
-	ao_ee_send(&ao_ee_instruction, 1);
-	ao_ee_recv(&ao_ee_instruction, 1);
+	ao_spi_send(&ao_ee_instruction, 1);
+	ao_spi_recv(&ao_ee_instruction, 1);
 	ao_ee_cs_high();
 	return ao_ee_instruction.instruction;
 }
@@ -164,7 +81,7 @@ ao_ee_wrsr(uint8_t status)
 	ao_ee_cs_low();
 	ao_ee_instruction.instruction = EE_WRSR;
 	ao_ee_instruction.address[0] = status;
-	ao_ee_send(&ao_ee_instruction, 2);
+	ao_spi_send(&ao_ee_instruction, 2);
 	ao_ee_cs_high();
 }
 
@@ -191,8 +108,8 @@ ao_ee_write_block(void)
 	ao_ee_instruction.address[0] = ao_ee_block >> 8;
 	ao_ee_instruction.address[1] = ao_ee_block;
 	ao_ee_instruction.address[2] = 0;
-	ao_ee_send(&ao_ee_instruction, 4);
-	ao_ee_send(ao_ee_data, EE_BLOCK);
+	ao_spi_send(&ao_ee_instruction, 4);
+	ao_spi_send(ao_ee_data, EE_BLOCK);
 	ao_ee_cs_high();
 	for (;;) {
 		uint8_t	status = ao_ee_rdsr();
@@ -210,8 +127,8 @@ ao_ee_read_block(void)
 	ao_ee_instruction.address[0] = ao_ee_block >> 8;
 	ao_ee_instruction.address[1] = ao_ee_block;
 	ao_ee_instruction.address[2] = 0;
-	ao_ee_send(&ao_ee_instruction, 4);
-	ao_ee_recv(ao_ee_data, EE_BLOCK);
+	ao_spi_send(&ao_ee_instruction, 4);
+	ao_spi_recv(ao_ee_data, EE_BLOCK);
 	ao_ee_cs_high();
 }
 
@@ -423,39 +340,5 @@ ao_ee_init(void)
 	P1DIR |= (1 << EE_CS_INDEX);
 	P1SEL &= ~(1 << EE_CS_INDEX);
 
-	/* Set up the USART pin assignment */
-	PERCFG = (PERCFG & ~PERCFG_U0CFG_ALT_MASK) | PERCFG_U0CFG_ALT_2;
-
-	/* Ensure that USART0 takes precidence over USART1 for pins that
-	 * they share
-	 */
-	P2SEL = (P2SEL & ~P2SEL_PRI3P1_MASK) | P2SEL_PRI3P1_USART0;
-
-	/* Make the SPI pins be controlled by the USART peripheral */
-	P1SEL |= ((1 << 5) | (1 << 4) | (1 << 3));
-
-	/* Set up OUT DMA */
-	ao_ee_dma_out_id = ao_dma_alloc(&ao_ee_dma_out_done);
-
-	/* Set up IN DMA */
-	ao_ee_dma_in_id = ao_dma_alloc(&ao_ee_dma_in_done);
-
-	/* Set up the USART.
-	 *
-	 * SPI master mode
-	 */
-	U0CSR = (UxCSR_MODE_SPI | UxCSR_RE | UxCSR_MASTER);
-
-	/* Set the baud rate and signal parameters
-	 *
-	 * The cc1111 is limited to a 24/8 MHz SPI clock,
-	 * while the 25LC1024 is limited to 20MHz. So,
-	 * use the 3MHz clock (BAUD_E 17, BAUD_M 0)
-	 */
-	U0BAUD = 0;
-	U0GCR = (UxGCR_CPOL_NEGATIVE |
-		 UxGCR_CPHA_FIRST_EDGE |
-		 UxGCR_ORDER_MSB |
-		 (17 << UxGCR_BAUD_E_SHIFT));
 	ao_cmd_register(&ao_ee_cmds[0]);
 }