};
#define STM_MODER_SHIFT(pin) ((pin) << 1)
-#define STM_MODER_MASK 3
+#define STM_MODER_MASK 3UL
#define STM_MODER_INPUT 0
#define STM_MODER_OUTPUT 1
#define STM_MODER_ALTERNATE 2
static inline void
stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
- gpio->moder = ((gpio->moder &
- ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
- value << STM_MODER_SHIFT(pin));
+ gpio->moder = (((uint32_t) gpio->moder &
+ (uint32_t) ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
+ (value << STM_MODER_SHIFT(pin)));
}
static inline uint32_t
}
#define STM_OTYPER_SHIFT(pin) (pin)
-#define STM_OTYPER_MASK 1
+#define STM_OTYPER_MASK 1UL
#define STM_OTYPER_PUSH_PULL 0
#define STM_OTYPER_OPEN_DRAIN 1
static inline void
stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
gpio->otyper = ((gpio->otyper &
- ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
- value << STM_OTYPER_SHIFT(pin));
+ (uint32_t) ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
+ (value << STM_OTYPER_SHIFT(pin)));
}
static inline uint32_t
}
#define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
-#define STM_OSPEEDR_MASK 3
+#define STM_OSPEEDR_MASK 3UL
#define STM_OSPEEDR_LOW 0
#define STM_OSPEEDR_MEDIUM 1
#define STM_OSPEEDR_HIGH 2
static inline void
stm_ospeedr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
gpio->ospeedr = ((gpio->ospeedr &
- ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
- value << STM_OSPEEDR_SHIFT(pin));
+ (uint32_t) ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
+ (value << STM_OSPEEDR_SHIFT(pin)));
}
static inline void
}
#define STM_PUPDR_SHIFT(pin) ((pin) << 1)
-#define STM_PUPDR_MASK 3
+#define STM_PUPDR_MASK 3UL
#define STM_PUPDR_NONE 0
#define STM_PUPDR_PULL_UP 1
#define STM_PUPDR_PULL_DOWN 2
static inline void
stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
gpio->pupdr = ((gpio->pupdr &
- ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
- value << STM_PUPDR_SHIFT(pin));
+ (uint32_t) ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
+ (value << STM_PUPDR_SHIFT(pin)));
}
static inline void
}
#define STM_AFR_SHIFT(pin) ((pin) << 2)
-#define STM_AFR_MASK 0xf
+#define STM_AFR_MASK 0xfUL
#define STM_AFR_AF0 0x0
#define STM_AFR_AF1 0x1
#define STM_AFR_AF2 0x2
stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
if (pin < 8)
gpio->afrl = ((gpio->afrl &
- ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
- value << STM_AFR_SHIFT(pin));
+ (uint32_t) ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
+ (value << STM_AFR_SHIFT(pin)));
else {
pin -= 8;
gpio->afrh = ((gpio->afrh &
- ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
- value << STM_AFR_SHIFT(pin));
+ (uint32_t) ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
+ (value << STM_AFR_SHIFT(pin)));
}
}
static inline uint16_t
stm_gpio_get_all(struct stm_gpio *gpio) {
- return gpio->idr;
+ return (uint16_t) gpio->idr;
}
/*
#define STM_TIM1011_CR1_CKD_1 0
#define STM_TIM1011_CR1_CKD_2 1
#define STM_TIM1011_CR1_CKD_4 2
-#define STM_TIM1011_CR1_CKD_MASK 3
+#define STM_TIM1011_CR1_CKD_MASK 3UL
#define STM_TIM1011_CR1_ARPE 7
#define STM_TIM1011_CR1_URS 2
#define STM_TIM1011_CR1_UDIS 1
#define STM_TIM1011_SMCR_ETPS_2 1
#define STM_TIM1011_SMCR_ETPS_4 2
#define STM_TIM1011_SMCR_ETPS_8 3
-#define STM_TIM1011_SMCR_ETPS_MASK 3
+#define STM_TIM1011_SMCR_ETPS_MASK 3UL
#define STM_TIM1011_SMCR_ETF 8
#define STM_TIM1011_SMCR_ETF_NONE 0
#define STM_TIM1011_SMCR_ETF_CK_INT_2 1
#define STM_TIM1011_SMCR_ETF_DTS_32_5 13
#define STM_TIM1011_SMCR_ETF_DTS_32_6 14
#define STM_TIM1011_SMCR_ETF_DTS_32_8 15
-#define STM_TIM1011_SMCR_ETF_MASK 15
+#define STM_TIM1011_SMCR_ETF_MASK 15UL
#define STM_TIM1011_DIER_CC1E 1
#define STM_TIM1011_DIER_UIE 0
#define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5
#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6
#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7
-#define STM_TIM1011_CCMR1_OC1M_MASK 7
+#define STM_TIM1011_CCMR1_OC1M_MASK 7UL
#define STM_TIM1011_CCMR1_OC1PE 3
#define STM_TIM1011_CCMR1_OC1FE 2
#define STM_TIM1011_CCMR1_CC1S 0
#define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1
#define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2
#define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3
-#define STM_TIM1011_CCMR1_CC1S_MASK 3
+#define STM_TIM1011_CCMR1_CC1S_MASK 3UL
#define STM_TIM1011_CCMR1_IC1F_NONE 0
#define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1
#define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13
#define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14
#define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15
-#define STM_TIM1011_CCMR1_IC1F_MASK 15
+#define STM_TIM1011_CCMR1_IC1F_MASK 15UL
#define STM_TIM1011_CCMR1_IC1PSC 2
#define STM_TIM1011_CCMR1_IC1PSC_1 0
#define STM_TIM1011_CCMR1_IC1PSC_2 1
#define STM_TIM1011_CCMR1_IC1PSC_4 2
#define STM_TIM1011_CCMR1_IC1PSC_8 3
-#define STM_TIM1011_CCMR1_IC1PSC_MASK 3
+#define STM_TIM1011_CCMR1_IC1PSC_MASK 3UL
#define STM_TIM1011_CCMR1_CC1S 0
#define STM_TIM1011_CCER_CC1NP 3
#define STM_TIM1011_TI1_RMP_LSI 1
#define STM_TIM1011_TI1_RMP_LSE 2
#define STM_TIM1011_TI1_RMP_RTC 3
-#define STM_TIM1011_TI1_RMP_MASK 3
+#define STM_TIM1011_TI1_RMP_MASK 3UL
struct stm_rcc {
vuint32_t cr;
#define STM_RCC_CR_RTCPRE_HSE_DIV_4 1
#define STM_RCC_CR_RTCPRE_HSE_DIV_8 2
#define STM_RCC_CR_RTCPRE_HSE_DIV_16 3
-#define STM_RCC_CR_RTCPRE_HSE_MASK 3
+#define STM_RCC_CR_RTCPRE_HSE_MASK 3UL
#define STM_RCC_CR_CSSON (28)
#define STM_RCC_CR_PLLRDY (25)
#define STM_RCC_ICSCR_MSIRANGE_1048576 4
#define STM_RCC_ICSCR_MSIRANGE_2097152 5
#define STM_RCC_ICSCR_MSIRANGE_4194304 6
-#define STM_RCC_ICSCR_MSIRANGE_MASK 0x7
+#define STM_RCC_ICSCR_MSIRANGE_MASK 0x7UL
#define STM_RCC_ICSCR_MSICAL 16
#define STM_RCC_ICSCR_MSITRIM 24
#define STM_RCC_CFGR_MCOPRE_DIV_4 2
#define STM_RCC_CFGR_MCOPRE_DIV_8 3
#define STM_RCC_CFGR_MCOPRE_DIV_16 4
-#define STM_RCC_CFGR_MCOPRE_MASK 7
+#define STM_RCC_CFGR_MCOPRE_MASK 7UL
#define STM_RCC_CFGR_MCOSEL (24)
#define STM_RCC_CFGR_MCOSEL_DISABLE 0
#define STM_RCC_CFGR_MCOSEL_PLL 5
#define STM_RCC_CFGR_MCOSEL_LSI 6
#define STM_RCC_CFGR_MCOSEL_LSE 7
-#define STM_RCC_CFGR_MCOSEL_MASK 7
+#define STM_RCC_CFGR_MCOSEL_MASK 7UL
#define STM_RCC_CFGR_PLLDIV (22)
#define STM_RCC_CFGR_PLLDIV_2 1
#define STM_RCC_CFGR_PLLDIV_3 2
#define STM_RCC_CFGR_PLLDIV_4 3
-#define STM_RCC_CFGR_PLLDIV_MASK 3
+#define STM_RCC_CFGR_PLLDIV_MASK 3UL
#define STM_RCC_CFGR_PLLMUL (18)
#define STM_RCC_CFGR_PLLMUL_3 0
#define STM_RCC_CFGR_PLLMUL_24 6
#define STM_RCC_CFGR_PLLMUL_32 7
#define STM_RCC_CFGR_PLLMUL_48 8
-#define STM_RCC_CFGR_PLLMUL_MASK 0xf
+#define STM_RCC_CFGR_PLLMUL_MASK 0xfUL
#define STM_RCC_CFGR_PLLSRC (16)
#define STM_RCC_CFGR_PPRE2_DIV_4 5
#define STM_RCC_CFGR_PPRE2_DIV_8 6
#define STM_RCC_CFGR_PPRE2_DIV_16 7
-#define STM_RCC_CFGR_PPRE2_MASK 7
+#define STM_RCC_CFGR_PPRE2_MASK 7UL
#define STM_RCC_CFGR_PPRE1 (8)
#define STM_RCC_CFGR_PPRE1_DIV_1 0
#define STM_RCC_CFGR_PPRE1_DIV_4 5
#define STM_RCC_CFGR_PPRE1_DIV_8 6
#define STM_RCC_CFGR_PPRE1_DIV_16 7
-#define STM_RCC_CFGR_PPRE1_MASK 7
+#define STM_RCC_CFGR_PPRE1_MASK 7UL
#define STM_RCC_CFGR_HPRE (4)
#define STM_RCC_CFGR_HPRE_DIV_1 0
#define STM_RCC_CFGR_HPRE_DIV_128 0xd
#define STM_RCC_CFGR_HPRE_DIV_256 0xe
#define STM_RCC_CFGR_HPRE_DIV_512 0xf
-#define STM_RCC_CFGR_HPRE_MASK 0xf
+#define STM_RCC_CFGR_HPRE_MASK 0xfUL
#define STM_RCC_CFGR_SWS (2)
#define STM_RCC_CFGR_SWS_MSI 0
#define STM_RCC_CFGR_SWS_HSI 1
#define STM_RCC_CFGR_SWS_HSE 2
#define STM_RCC_CFGR_SWS_PLL 3
-#define STM_RCC_CFGR_SWS_MASK 3
+#define STM_RCC_CFGR_SWS_MASK 3UL
#define STM_RCC_CFGR_SW (0)
#define STM_RCC_CFGR_SW_MSI 0
#define STM_RCC_CFGR_SW_HSI 1
#define STM_RCC_CFGR_SW_HSE 2
#define STM_RCC_CFGR_SW_PLL 3
-#define STM_RCC_CFGR_SW_MASK 3
+#define STM_RCC_CFGR_SW_MASK 3UL
#define STM_RCC_IOPENR_IOPAEN 0
#define STM_RCC_IOPENR_IOPBEN 1
#define STM_RCC_CSR_RTCSEL_LSE 1
#define STM_RCC_CSR_RTCSEL_LSI 2
#define STM_RCC_CSR_RTCSEL_HSE 3
-#define STM_RCC_CSR_RTCSEL_MASK 3
+#define STM_RCC_CSR_RTCSEL_MASK 3UL
#define STM_RCC_CSR_LSEBYP (10)
#define STM_RCC_CSR_LSERDY (9)
#define STM_PWR_CR_VOS_1_8 1
#define STM_PWR_CR_VOS_1_5 2
#define STM_PWR_CR_VOS_1_2 3
-#define STM_PWR_CR_VOS_MASK 3
+#define STM_PWR_CR_VOS_MASK 3UL
#define STM_PWR_CR_FWU 10
#define STM_PWR_CR_ULP 9
#define STM_PWR_CR_DBP 8
#define STM_PWR_CR_PLS_2_9 5
#define STM_PWR_CR_PLS_3_1 6
#define STM_PWR_CR_PLS_EXT 7
-#define STM_PWR_CR_PLS_MASK 7
+#define STM_PWR_CR_PLS_MASK 7UL
#define STM_PWR_CR_PVDE 4
#define STM_PWR_CR_CSBF 3
#define STM_PWR_CR_CWUF 2
#define STM_TIM67_CR2_MMS_RESET 0
#define STM_TIM67_CR2_MMS_ENABLE 1
#define STM_TIM67_CR2_MMS_UPDATE 2
-#define STM_TIM67_CR2_MMS_MASK 7
+#define STM_TIM67_CR2_MMS_MASK 7UL
#define STM_TIM67_DIER_UDE (8)
#define STM_TIM67_DIER_UIE (0)
#define STM_LCD_CR_BIAS_1_4 0
#define STM_LCD_CR_BIAS_1_2 1
#define STM_LCD_CR_BIAS_1_3 2
-#define STM_LCD_CR_BIAS_MASK 3
+#define STM_LCD_CR_BIAS_MASK 3UL
#define STM_LCD_CR_DUTY (2)
#define STM_LCD_CR_DUTY_STATIC 0
#define STM_LCD_CR_DUTY_1_3 2
#define STM_LCD_CR_DUTY_1_4 3
#define STM_LCD_CR_DUTY_1_8 4
-#define STM_LCD_CR_DUTY_MASK 7
+#define STM_LCD_CR_DUTY_MASK 7UL
#define STM_LCD_CR_VSEL (1)
#define STM_LCD_CR_LCDEN (0)
#define STM_LCD_FCR_PS_8192 0xd
#define STM_LCD_FCR_PS_16384 0xe
#define STM_LCD_FCR_PS_32768 0xf
-#define STM_LCD_FCR_PS_MASK 0xf
+#define STM_LCD_FCR_PS_MASK 0xfUL
#define STM_LCD_FCR_DIV (18)
#define STM_LCD_FCR_DIV_16 0x0
#define STM_LCD_FCR_DIV_29 0xd
#define STM_LCD_FCR_DIV_30 0xe
#define STM_LCD_FCR_DIV_31 0xf
-#define STM_LCD_FCR_DIV_MASK 0xf
+#define STM_LCD_FCR_DIV_MASK 0xfUL
#define STM_LCD_FCR_BLINK (16)
#define STM_LCD_FCR_BLINK_DISABLE 0
#define STM_LCD_FCR_BLINK_SEG0_COM0 1
#define STM_LCD_FCR_BLINK_SEG0_COMALL 2
#define STM_LCD_FCR_BLINK_SEGALL_COMALL 3
-#define STM_LCD_FCR_BLINK_MASK 3
+#define STM_LCD_FCR_BLINK_MASK 3UL
#define STM_LCD_FCR_BLINKF (13)
#define STM_LCD_FCR_BLINKF_8 0
#define STM_LCD_FCR_BLINKF_256 5
#define STM_LCD_FCR_BLINKF_512 6
#define STM_LCD_FCR_BLINKF_1024 7
-#define STM_LCD_FCR_BLINKF_MASK 7
+#define STM_LCD_FCR_BLINKF_MASK 7UL
#define STM_LCD_FCR_CC (10)
-#define STM_LCD_FCR_CC_MASK 7
+#define STM_LCD_FCR_CC_MASK 7UL
#define STM_LCD_FCR_DEAD (7)
-#define STM_LCD_FCR_DEAD_MASK 7
+#define STM_LCD_FCR_DEAD_MASK 7UL
#define STM_LCD_FCR_PON (4)
-#define STM_LCD_FCR_PON_MASK 7
+#define STM_LCD_FCR_PON_MASK 7UL
#define STM_LCD_FCR_UDDIE (3)
#define STM_LCD_FCR_SOFIE (1)
uint32_t v;
v = stm_nvic.ipr[n];
- v &= ~IRQ_PRIO_MASK(irq);
+ v &= (uint32_t) ~IRQ_PRIO_MASK(irq);
v |= (prio) << IRQ_PRIO_BIT(irq);
stm_nvic.ipr[n] = v;
}
extern struct stm_mpu stm_mpu;
#define STM_MPU_TYPER_IREGION 16
-#define STM_MPU_TYPER_IREGION_MASK 0xff
+#define STM_MPU_TYPER_IREGION_MASK 0xffUL
#define STM_MPU_TYPER_DREGION 8
-#define STM_MPU_TYPER_DREGION_MASK 0xff
+#define STM_MPU_TYPER_DREGION_MASK 0xffUL
#define STM_MPU_TYPER_SEPARATE 0
#define STM_MPU_CR_PRIVDEFENA 2
#define STM_MPU_CR_ENABLE 0
#define STM_MPU_RNR_REGION 0
-#define STM_MPU_RNR_REGION_MASK 0xff
+#define STM_MPU_RNR_REGION_MASK 0xffUL
#define STM_MPU_RBAR_ADDR 5
-#define STM_MPU_RBAR_ADDR_MASK 0x7ffffff
+#define STM_MPU_RBAR_ADDR_MASK 0x7ffffffUL
#define STM_MPU_RBAR_VALID 4
#define STM_MPU_RBAR_REGION 0
-#define STM_MPU_RBAR_REGION_MASK 0xf
+#define STM_MPU_RBAR_REGION_MASK 0xfUL
#define STM_MPU_RASR_XN 28
#define STM_MPU_RASR_AP 24
#define STM_MPU_RASR_AP_RW_RW 3
#define STM_MPU_RASR_AP_RO_NONE 5
#define STM_MPU_RASR_AP_RO_RO 6
-#define STM_MPU_RASR_AP_MASK 7
+#define STM_MPU_RASR_AP_MASK 7UL
#define STM_MPU_RASR_TEX 19
-#define STM_MPU_RASR_TEX_MASK 7
+#define STM_MPU_RASR_TEX_MASK 7UL
#define STM_MPU_RASR_S 18
#define STM_MPU_RASR_C 17
#define STM_MPU_RASR_B 16
#define STM_MPU_RASR_SRD 8
-#define STM_MPU_RASR_SRD_MASK 0xff
+#define STM_MPU_RASR_SRD_MASK 0xffUL
#define STM_MPU_RASR_SIZE 1
-#define STM_MPU_RASR_SIZE_MASK 0x1f
+#define STM_MPU_RASR_SIZE_MASK 0x1fUL
#define STM_MPU_RASR_ENABLE 0
#define isr_decl(name) void stm_ ## name ## _isr(void)
#define STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH 0
#define STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH 1
#define STM_SYSCFG_MEMRMP_MEM_MODE_SRAM 3
-#define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3
+#define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3UL
#define STM_SYSCFG_PMC_USB_PU 0
#define STM_SYSCFG_EXTICR_PH 5
static inline void
-stm_exticr_set(struct stm_gpio *gpio, int pin) {
+stm_exticr_set(struct stm_gpio *gpio, uint8_t pin) {
uint8_t reg = pin >> 2;
uint8_t shift = (pin & 3) << 2;
uint8_t val = 0;
else if (gpio == &stm_gpioe)
val = STM_SYSCFG_EXTICR_PE;
- stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
+ stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xfUL << shift)) | val << shift;
}
struct stm_dma_channel {
#define STM_DMA_INDEX(channel) ((channel) - 1)
#define STM_DMA_ISR(index) ((index) << 2)
-#define STM_DMA_ISR_MASK 0xf
+#define STM_DMA_ISR_MASK 0xfUL
#define STM_DMA_ISR_TEIF 3
#define STM_DMA_ISR_HTIF 2
#define STM_DMA_ISR_TCIF 1
#define STM_DMA_ISR_GIF 0
#define STM_DMA_IFCR(index) ((index) << 2)
-#define STM_DMA_IFCR_MASK 0xf
+#define STM_DMA_IFCR_MASK 0xfUL
#define STM_DMA_IFCR_CTEIF 3
#define STM_DMA_IFCR_CHTIF 2
#define STM_DMA_IFCR_CTCIF 1
#define STM_SPI_CR1_BR_PCLK_64 5
#define STM_SPI_CR1_BR_PCLK_128 6
#define STM_SPI_CR1_BR_PCLK_256 7
-#define STM_SPI_CR1_BR_MASK 7
+#define STM_SPI_CR1_BR_MASK 7UL
#define STM_SPI_CR1_MSTR 2
#define STM_SPI_CR1_CPOL 1
#define STM_ADC_CFGR1_EXTEN_RISING 1
#define STM_ADC_CFGR1_EXTEN_FALLING 2
#define STM_ADC_CFGR1_EXTEN_BOTH 3
-#define STM_ADC_CFGR1_EXTEN_MASK 3
+#define STM_ADC_CFGR1_EXTEN_MASK 3UL
#define STM_ADC_CFGR1_EXTSEL 6
#define STM_ADC_CFGR1_ALIGN 5
#define STM_ADC_CFGR1_RES_10 1
#define STM_ADC_CFGR1_RES_8 2
#define STM_ADC_CFGR1_RES_6 3
-#define STM_ADC_CFGR1_RES_MASK 3
+#define STM_ADC_CFGR1_RES_MASK 3UL
#define STM_ADC_CFGR1_SCANDIR 2
#define STM_ADC_CFGR1_SCANDIR_UP 0
#define STM_ADC_CFGR1_SCANDIR_DOWN 1
#define STM_I2C_CR2_FREQ_16_MHZ 16
#define STM_I2C_CR2_FREQ_24_MHZ 24
#define STM_I2C_CR2_FREQ_32_MHZ 32
-#define STM_I2C_CR2_FREQ_MASK 0x3f
+#define STM_I2C_CR2_FREQ_MASK 0x3fUL
#define STM_I2C_SR1_SMBALERT 15
#define STM_I2C_SR1_TIMEOUT 14
#define STM_I2C_SR1_SB 0
#define STM_I2C_SR2_PEC 8
-#define STM_I2C_SR2_PEC_MASK 0xff00
+#define STM_I2C_SR2_PEC_MASK 0xff00UL
#define STM_I2C_SR2_DUALF 7
#define STM_I2C_SR2_SMBHOST 6
#define STM_I2C_SR2_SMBDEFAULT 5
#define STM_I2C_CCR_FS 15
#define STM_I2C_CCR_DUTY 14
#define STM_I2C_CCR_CCR 0
-#define STM_I2C_CCR_MASK 0x7ff
+#define STM_I2C_CCR_MASK 0x7ffUL
struct stm_tim234 {
vuint32_t cr1;
#define STM_TIM234_CR1_CKD_1 0
#define STM_TIM234_CR1_CKD_2 1
#define STM_TIM234_CR1_CKD_4 2
-#define STM_TIM234_CR1_CKD_MASK 3
+#define STM_TIM234_CR1_CKD_MASK 3UL
#define STM_TIM234_CR1_ARPE 7
#define STM_TIM234_CR1_CMS 5
#define STM_TIM234_CR1_CMS_EDGE 0
#define STM_TIM234_CR1_CMS_CENTER_1 1
#define STM_TIM234_CR1_CMS_CENTER_2 2
#define STM_TIM234_CR1_CMS_CENTER_3 3
-#define STM_TIM234_CR1_CMS_MASK 3
+#define STM_TIM234_CR1_CMS_MASK 3UL
#define STM_TIM234_CR1_DIR 4
#define STM_TIM234_CR1_DIR_UP 0
#define STM_TIM234_CR1_DIR_DOWN 1
#define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5
#define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6
#define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7
-#define STM_TIM234_CR2_MMS_MASK 7
+#define STM_TIM234_CR2_MMS_MASK 7UL
#define STM_TIM234_CR2_CCDS 3
#define STM_TIM234_SMCR_ETP 15
#define STM_TIM234_SMCR_ETPS_DIV_2 1
#define STM_TIM234_SMCR_ETPS_DIV_4 2
#define STM_TIM234_SMCR_ETPS_DIV_8 3
-#define STM_TIM234_SMCR_ETPS_MASK 3
+#define STM_TIM234_SMCR_ETPS_MASK 3UL
#define STM_TIM234_SMCR_ETF 8
#define STM_TIM234_SMCR_ETF_NONE 0
#define STM_TIM234_SMCR_ETF_INT_N_2 1
#define STM_TIM234_SMCR_ETF_DTS_32_N_5 13
#define STM_TIM234_SMCR_ETF_DTS_32_N_6 14
#define STM_TIM234_SMCR_ETF_DTS_32_N_8 15
-#define STM_TIM234_SMCR_ETF_MASK 15
+#define STM_TIM234_SMCR_ETF_MASK 15UL
#define STM_TIM234_SMCR_MSM 7
#define STM_TIM234_SMCR_TS 4
#define STM_TIM234_SMCR_TS_ITR0 0
#define STM_TIM234_SMCR_TS_TI1FP1 5
#define STM_TIM234_SMCR_TS_TI2FP2 6
#define STM_TIM234_SMCR_TS_ETRF 7
-#define STM_TIM234_SMCR_TS_MASK 7
+#define STM_TIM234_SMCR_TS_MASK 7UL
#define STM_TIM234_SMCR_OCCS 3
#define STM_TIM234_SMCR_SMS 0
#define STM_TIM234_SMCR_SMS_DISABLE 0
#define STM_TIM234_SMCR_SMS_GATED_MODE 5
#define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6
#define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7
-#define STM_TIM234_SMCR_SMS_MASK 7
+#define STM_TIM234_SMCR_SMS_MASK 7UL
#define STM_TIM234_DIER_TDE 14
#define STM_TIM234_DIER_CC4DE 12
#define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5
#define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6
#define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7
-#define STM_TIM234_CCMR1_OC2M_MASK 7
+#define STM_TIM234_CCMR1_OC2M_MASK 7UL
#define STM_TIM234_CCMR1_OC2PE 11
#define STM_TIM234_CCMR1_OC2FE 10
#define STM_TIM234_CCMR1_CC2S 8
#define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1
#define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2
#define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3
-#define STM_TIM234_CCMR1_CC2S_MASK 3
+#define STM_TIM234_CCMR1_CC2S_MASK 3UL
#define STM_TIM234_CCMR1_OC1CE 7
#define STM_TIM234_CCMR1_OC1M 4
#define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5
#define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6
#define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7
-#define STM_TIM234_CCMR1_OC1M_MASK 7
+#define STM_TIM234_CCMR1_OC1M_MASK 7UL
#define STM_TIM234_CCMR1_OC1PE 3
#define STM_TIM234_CCMR1_OC1FE 2
#define STM_TIM234_CCMR1_CC1S 0
#define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1
#define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2
#define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3
-#define STM_TIM234_CCMR1_CC1S_MASK 3
+#define STM_TIM234_CCMR1_CC1S_MASK 3UL
#define STM_TIM234_CCMR1_IC2F 12
#define STM_TIM234_CCMR1_IC2F_NONE 0
#define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5
#define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6
#define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7
-#define STM_TIM234_CCMR2_OC4M_MASK 7
+#define STM_TIM234_CCMR2_OC4M_MASK 7UL
#define STM_TIM234_CCMR2_OC4PE 11
#define STM_TIM234_CCMR2_OC4FE 10
#define STM_TIM234_CCMR2_CC4S 8
#define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1
#define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2
#define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3
-#define STM_TIM234_CCMR2_CC4S_MASK 3
+#define STM_TIM234_CCMR2_CC4S_MASK 3UL
#define STM_TIM234_CCMR2_OC3CE 7
#define STM_TIM234_CCMR2_OC3M 4
#define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5
#define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6
#define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7
-#define STM_TIM234_CCMR2_OC3M_MASK 7
+#define STM_TIM234_CCMR2_OC3M_MASK 7UL
#define STM_TIM234_CCMR2_OC3PE 3
#define STM_TIM234_CCMR2_OC3FE 2
#define STM_TIM234_CCMR2_CC3S 0
#define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1
#define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2
#define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3
-#define STM_TIM234_CCMR2_CC3S_MASK 3
+#define STM_TIM234_CCMR2_CC3S_MASK 3UL
#define STM_TIM234_CCER_CC4NP 15
#define STM_TIM234_CCER_CC4P 13
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