# # Debug mode - drive RESET_N low for two clock cycles # C D R . D . C D . . D . C D . . D R # # WR_CONFIG # C . R 0 . . R C . R 0 . . R C . R 0 . . R C D R 1 . D R C D R 1 . D R C D R 1 . D R C . R 0 . . R C D R 1 . D R C . R 0 . . R C . R 0 . . R C . R 0 . . R C . R 0 . . R C D R 1 . D R C . R 0 . . R C . R 0 . . R C . R 0 . . R # # Now read for a while # C D R . D R C D R . D R C D R . D R C D R . D R C D R . D R C D R . D R C D R . D R C D R . D R # # RD_CONFIG # C . R 0 . . R C . R 0 . . R C D R 1 . D R C . R 0 . . R C . R 0 . . R C D R 1 . D R C . R 0 . . R C . R 0 . . R # # Now read for a while # C D R . D R C D R . D R C D R . D R C D R . D R C D R . D R C D R . D R C D R . D R C D R . D R