git.gag.com Git - fw/altos/blob - src/stmf0/stm32f0.h

   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #ifndef _STM32F0_H_
  20 #define _STM32F0_H_
  21
  22 #include <stdint.h>
  23
  24 typedef volatile uint32_t       vuint32_t;
  25 typedef volatile void *         vvoid_t;
  26 typedef volatile uint16_t       vuint16_t;
  27 typedef volatile uint8_t        vuint8_t;
  28
  29 struct stm_gpio {
  30         vuint32_t       moder;
  31         vuint32_t       otyper;
  32         vuint32_t       ospeedr;
  33         vuint32_t       pupdr;
  34
  35         vuint32_t       idr;
  36         vuint32_t       odr;
  37         vuint32_t       bsrr;
  38         vuint32_t       lckr;
  39
  40         vuint32_t       afrl;
  41         vuint32_t       afrh;
  42         vuint32_t       brr;
  43 };
  44
  45 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  46 #define STM_MODER_MASK                  3
  47 #define STM_MODER_INPUT                 0
  48 #define STM_MODER_OUTPUT                1
  49 #define STM_MODER_ALTERNATE             2
  50 #define STM_MODER_ANALOG                3
  51
  52 static inline void
  53 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  54         gpio->moder = ((gpio->moder &
  55                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  56                        value << STM_MODER_SHIFT(pin));
  57 }
  58
  59 static inline uint32_t
  60 stm_moder_get(struct stm_gpio *gpio, int pin) {
  61         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  62 }
  63
  64 #define STM_OTYPER_SHIFT(pin)           (pin)
  65 #define STM_OTYPER_MASK                 1
  66 #define STM_OTYPER_PUSH_PULL            0
  67 #define STM_OTYPER_OPEN_DRAIN           1
  68
  69 static inline void
  70 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  71         gpio->otyper = ((gpio->otyper &
  72                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  73                         value << STM_OTYPER_SHIFT(pin));
  74 }
  75
  76 static inline uint32_t
  77 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  78         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  79 }
  80
  81 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  82 #define STM_OSPEEDR_MASK                3
  83 #define STM_OSPEEDR_LOW                 0       /* 2MHz */
  84 #define STM_OSPEEDR_MEDIUM              1       /* 10MHz */
  85 #define STM_OSPEEDR_HIGH                3       /* 10-50MHz */
  86
  87 static inline void
  88 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  89         gpio->ospeedr = ((gpio->ospeedr &
  90                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  91                        value << STM_OSPEEDR_SHIFT(pin));
  92 }
  93
  94 static inline uint32_t
  95 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  96         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  97 }
  98
  99 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
 100 #define STM_PUPDR_MASK                  3
 101 #define STM_PUPDR_NONE                  0
 102 #define STM_PUPDR_PULL_UP               1
 103 #define STM_PUPDR_PULL_DOWN             2
 104 #define STM_PUPDR_RESERVED              3
 105
 106 static inline void
 107 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 108         gpio->pupdr = ((gpio->pupdr &
 109                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 110                        value << STM_PUPDR_SHIFT(pin));
 111 }
 112
 113 static inline uint32_t
 114 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 115         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 116 }
 117
 118 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 119 #define STM_AFR_MASK                    0xf
 120 #define STM_AFR_NONE                    0
 121 #define STM_AFR_AF0                     0x0
 122 #define STM_AFR_AF1                     0x1
 123 #define STM_AFR_AF2                     0x2
 124 #define STM_AFR_AF3                     0x3
 125 #define STM_AFR_AF4                     0x4
 126 #define STM_AFR_AF5                     0x5
 127 #define STM_AFR_AF6                     0x6
 128 #define STM_AFR_AF7                     0x7
 129
 130 static inline void
 131 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 132         /*
 133          * Set alternate pin mode too
 134          */
 135         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 136         if (pin < 8)
 137                 gpio->afrl = ((gpio->afrl &
 138                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 139                               value << STM_AFR_SHIFT(pin));
 140         else {
 141                 pin -= 8;
 142                 gpio->afrh = ((gpio->afrh &
 143                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 144                               value << STM_AFR_SHIFT(pin));
 145         }
 146 }
 147
 148 static inline uint32_t
 149 stm_afr_get(struct stm_gpio *gpio, int pin) {
 150         if (pin < 8)
 151                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 152         else {
 153                 pin -= 8;
 154                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 155         }
 156 }
 157
 158 static inline void
 159 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 160         /* Use the bit set/reset register to do this atomically */
 161         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 162 }
 163
 164 static inline uint8_t
 165 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 166         return (gpio->idr >> pin) & 1;
 167 }
 168
 169 static inline uint16_t
 170 stm_gpio_get_all(struct stm_gpio *gpio) {
 171         return gpio->idr;
 172 }
 173
 174 /*
 175  * We can't define these in registers.ld or our fancy
 176  * ao_enable_gpio macro will expand into a huge pile of code
 177  * as the compiler won't do correct constant folding and
 178  * dead-code elimination
 179  */
 180
 181 extern struct stm_gpio stm_gpioa;
 182 extern struct stm_gpio stm_gpiob;
 183 extern struct stm_gpio stm_gpioc;
 184 extern struct stm_gpio stm_gpiof;
 185
 186 #define stm_gpiof  (*((struct stm_gpio *) 0x48001400))
 187 #define stm_gpioc  (*((struct stm_gpio *) 0x48000800))
 188 #define stm_gpiob  (*((struct stm_gpio *) 0x48000400))
 189 #define stm_gpioa  (*((struct stm_gpio *) 0x48000000))
 190
 191 /* Flash interface */
 192
 193 struct stm_flash {
 194         vuint32_t       acr;
 195         vuint32_t       keyr;
 196         vuint32_t       optkeyr;
 197         vuint32_t       sr;
 198
 199         vuint32_t       cr;
 200         vuint32_t       ar;
 201         vuint32_t       unused_0x18;
 202         vuint32_t       obr;
 203
 204         vuint32_t       wrpr;
 205 };
 206
 207 extern struct stm_flash stm_flash;
 208
 209 #define STM_FLASH_ACR_PRFTBS    (5)
 210 #define STM_FLASH_ACR_PRFTBE    (4)
 211 #define STM_FLASH_ACR_LATENCY   (0)
 212 #define  STM_FLASH_ACR_LATENCY_0                0
 213 #define  STM_FLASH_ACR_LATENCY_1                1
 214
 215 #define STM_FLASH_PECR_OBL_LAUNCH       18
 216 #define STM_FLASH_PECR_ERRIE            17
 217 #define STM_FLASH_PECR_EOPIE            16
 218 #define STM_FLASH_PECR_FPRG             10
 219 #define STM_FLASH_PECR_ERASE            9
 220 #define STM_FLASH_PECR_FTDW             8
 221 #define STM_FLASH_PECR_DATA             4
 222 #define STM_FLASH_PECR_PROG             3
 223 #define STM_FLASH_PECR_OPTLOCK          2
 224 #define STM_FLASH_PECR_PRGLOCK          1
 225 #define STM_FLASH_PECR_PELOCK           0
 226
 227 #define STM_FLASH_SR_EOP                5
 228 #define STM_FLASH_SR_WRPRTERR           4
 229 #define STM_FLASH_SR_PGERR              2
 230 #define STM_FLASH_SR_BSY                0
 231
 232 #define STM_FLASH_CR_OBL_LAUNCH         13
 233 #define STM_FLASH_CR_EOPIE              12
 234 #define STM_FLASH_CR_ERRIE              10
 235 #define STM_FLASH_CR_OPTWRE             9
 236 #define STM_FLASH_CR_LOCK               7
 237 #define STM_FLASH_CR_STRT               6
 238 #define STM_FLASH_CR_OPTER              5
 239 #define STM_FLASH_CR_OPTPG              4
 240 #define STM_FLASH_CR_MER                2
 241 #define STM_FLASH_CR_PER                1
 242 #define STM_FLASH_CR_PG                 0
 243
 244 #define STM_FLASH_OBR_DATA1             24
 245 #define STM_FLASH_OBR_DATA0             16
 246 #define STM_FLASH_OBR_BOOT_SEL          15
 247 #define STM_FLASH_OBR_RAM_PARITY_CHECK  14
 248 #define STM_FLASH_OBR_VDDA_MONITOR      13
 249 #define STM_FLASH_OBR_NBOOT1            12
 250 #define STM_FLASH_OBR_NBOOT0            11
 251 #define STM_FLASH_OBR_NRST_STDBY        10
 252 #define STM_FLASH_OBR_NRST_STOP         9
 253 #define STM_FLASH_OBR_WDG_SW            8
 254 #define STM_FLASH_OBR_RDPRT             1
 255 #define  STM_FLASH_OBR_RDPRT_LEVEL0             0
 256 #define  STM_FLASH_OBR_RDPRT_LEVEL1             1
 257 #define  STM_FLASH_OBR_RDPRT_LEVEL2             3
 258 #define STM_FLASH_OBR_OPTERR            0
 259
 260 #define STM_FLASH_KEYR_KEY1     0x45670123
 261 #define STM_FLASH_KEYR_KEY2     0xcdef89ab
 262
 263 struct stm_rcc {
 264         vuint32_t       cr;
 265         vuint32_t       cfgr;
 266         vuint32_t       cir;
 267         vuint32_t       apb2rstr;
 268
 269         vuint32_t       apb1rstr;
 270         vuint32_t       ahbenr;
 271         vuint32_t       apb2enr;
 272         vuint32_t       apb1enr;
 273
 274         vuint32_t       bdcr;
 275         vuint32_t       csr;
 276         vuint32_t       ahbrstr;
 277         vuint32_t       cfgr2;
 278
 279         vuint32_t       cfgr3;
 280         vuint32_t       cr2;
 281 };
 282
 283 extern struct stm_rcc stm_rcc;
 284
 285 /* Nominal high speed internal oscillator frequency is 8MHz */
 286 #define STM_HSI_FREQ            8000000
 287
 288 #define STM_RCC_CR_PLLRDY       (25)
 289 #define STM_RCC_CR_PLLON        (24)
 290 #define STM_RCC_CR_CSSON        (19)
 291 #define STM_RCC_CR_HSEBYP       (18)
 292 #define STM_RCC_CR_HSERDY       (17)
 293 #define STM_RCC_CR_HSEON        (16)
 294 #define STM_RCC_CR_HSICAL       (8)
 295 #define STM_RCC_CR_HSITRIM      (3)
 296 #define STM_RCC_CR_HSIRDY       (1)
 297 #define STM_RCC_CR_HSION        (0)
 298
 299 #define STM_RCC_CFGR_PLL_NODIV  (31)
 300 #define  STM_RCC_CFGR_PLL_NODIV_DIV_1   1
 301 #define  STM_RCC_CFGR_PLL_NODIV_DIV_2   0
 302
 303 #define STM_RCC_CFGR_MCOPRE     (28)
 304 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 305 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 306 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 307 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 308 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 309 #define  STM_RCC_CFGR_MCOPRE_DIV_32     5
 310 #define  STM_RCC_CFGR_MCOPRE_DIV_64     6
 311 #define  STM_RCC_CFGR_MCOPRE_DIV_128    7
 312 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7
 313
 314 #define STM_RCC_CFGR_MCO        (24)
 315 # define STM_RCC_CFGR_MCO_DISABLE       0
 316 # define STM_RCC_CFGR_MCO_RC            1
 317 # define STM_RCC_CFGR_MCO_LSI           2
 318 # define STM_RCC_CFGR_MCO_LSE           3
 319 # define STM_RCC_CFGR_MCO_SYSCLK        4
 320 # define STM_RCC_CFGR_MCO_HSI           5
 321 # define STM_RCC_CFGR_MCO_HSE           6
 322 # define STM_RCC_CFGR_MCO_PLLCLK        7
 323 # define STM_RCC_CFGR_MCO_HSI48         8
 324 # define STM_RCC_CFGR_MCO_MASK          (0xf)
 325
 326 #define STM_RCC_CFGR_PLLMUL     (18)
 327 #define  STM_RCC_CFGR_PLLMUL_2          0
 328 #define  STM_RCC_CFGR_PLLMUL_3          1
 329 #define  STM_RCC_CFGR_PLLMUL_4          2
 330 #define  STM_RCC_CFGR_PLLMUL_5          3
 331 #define  STM_RCC_CFGR_PLLMUL_6          4
 332 #define  STM_RCC_CFGR_PLLMUL_7          5
 333 #define  STM_RCC_CFGR_PLLMUL_8          6
 334 #define  STM_RCC_CFGR_PLLMUL_9          7
 335 #define  STM_RCC_CFGR_PLLMUL_10         8
 336 #define  STM_RCC_CFGR_PLLMUL_11         9
 337 #define  STM_RCC_CFGR_PLLMUL_12         10
 338 #define  STM_RCC_CFGR_PLLMUL_13         11
 339 #define  STM_RCC_CFGR_PLLMUL_14         12
 340 #define  STM_RCC_CFGR_PLLMUL_15         13
 341 #define  STM_RCC_CFGR_PLLMUL_16         14
 342 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 343
 344 #define STM_RCC_CFGR_PLLXTPRE   (17)
 345
 346 #define STM_RCC_CFGR_PLLSRC     (15)
 347 # define STM_RCC_CFGR_PLLSRC_HSI_DIV_2  0
 348 # define STM_RCC_CFGR_PLLSRC_HSI        1
 349 # define STM_RCC_CFGR_PLLSRC_HSE        2
 350 # define STM_RCC_CFGR_PLLSRC_HSI48      3
 351
 352 #define STM_RCC_CFGR_ADCPRE     (14)
 353
 354 #define STM_RCC_CFGR_PPRE       (8)
 355 #define  STM_RCC_CFGR_PPRE_DIV_1        0
 356 #define  STM_RCC_CFGR_PPRE_DIV_2        4
 357 #define  STM_RCC_CFGR_PPRE_DIV_4        5
 358 #define  STM_RCC_CFGR_PPRE_DIV_8        6
 359 #define  STM_RCC_CFGR_PPRE_DIV_16       7
 360 #define  STM_RCC_CFGR_PPRE_MASK         7
 361
 362 #define STM_RCC_CFGR_HPRE       (4)
 363 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 364 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 365 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 366 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 367 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 368 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 369 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 370 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 371 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 372 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 373
 374 #define STM_RCC_CFGR_SWS        (2)
 375 #define  STM_RCC_CFGR_SWS_HSI           0
 376 #define  STM_RCC_CFGR_SWS_HSE           1
 377 #define  STM_RCC_CFGR_SWS_PLL           2
 378 #define  STM_RCC_CFGR_SWS_HSI48         3
 379 #define  STM_RCC_CFGR_SWS_MASK          3
 380
 381 #define STM_RCC_CFGR_SW         (0)
 382 #define  STM_RCC_CFGR_SW_HSI            0
 383 #define  STM_RCC_CFGR_SW_HSE            1
 384 #define  STM_RCC_CFGR_SW_PLL            2
 385 #define  STM_RCC_CFGR_SW_HSI48          3
 386 #define  STM_RCC_CFGR_SW_MASK           3
 387
 388 #define STM_RCC_APB2RSTR_DBGMCURST      22
 389 #define STM_RCC_APB2RSTR_TIM17RST       18
 390 #define STM_RCC_APB2RSTR_TIM16RST       17
 391 #define STM_RCC_APB2RSTR_TIM15RST       16
 392 #define STM_RCC_APB2RSTR_USART1RST      14
 393 #define STM_RCC_APB2RSTR_SPI1RST        12
 394 #define STM_RCC_APB2RSTR_TIM1RST        11
 395 #define STM_RCC_APB2RSTR_ADCRST         9
 396 #define STM_RCC_APB2RSTR_USART8RST      7
 397 #define STM_RCC_APB2RSTR_USART7RST      6
 398 #define STM_RCC_APB2RSTR_USART6RST      5
 399 #define STM_RCC_APB2RSTR_SYSCFGRST      1
 400
 401 #define STM_RCC_APB1RSTR_CECRST         30
 402 #define STM_RCC_APB1RSTR_DACRST         29
 403 #define STM_RCC_APB1RSTR_PWRRST         28
 404 #define STM_RCC_APB1RSTR_CRSRST         27
 405 #define STM_RCC_APB1RSTR_CANRST         25
 406 #define STM_RCC_APB1RSTR_USBRST         23
 407 #define STM_RCC_APB1RSTR_I2C2RST        22
 408 #define STM_RCC_APB1RSTR_I1C1RST        21
 409 #define STM_RCC_APB1RSTR_USART5RST      20
 410 #define STM_RCC_APB1RSTR_USART4RST      19
 411 #define STM_RCC_APB1RSTR_USART3RST      18
 412 #define STM_RCC_APB1RSTR_USART2RST      17
 413 #define STM_RCC_APB1RSTR_SPI2RST        14
 414 #define STM_RCC_APB1RSTR_WWDGRST        11
 415 #define STM_RCC_APB1RSTR_TIM14RST       8
 416 #define STM_RCC_APB1RSTR_TIM7RST        5
 417 #define STM_RCC_APB1RSTR_TIM6RST        4
 418 #define STM_RCC_APB1RSTR_TIM3RST        1
 419 #define STM_RCC_APB1RSTR_TIM2RST        0
 420
 421 #define STM_RCC_AHBENR_TSCEN    24
 422 #define STM_RCC_AHBENR_IOPFEN   22
 423 #define STM_RCC_AHBENR_IOPEEN   21
 424 #define STM_RCC_AHBENR_IOPDEN   20
 425 #define STM_RCC_AHBENR_IOPCEN   19
 426 #define STM_RCC_AHBENR_IOPBEN   18
 427 #define STM_RCC_AHBENR_IOPAEN   17
 428 #define STM_RCC_AHBENR_CRCEN    6
 429 #define STM_RCC_AHBENR_FLITFEN  4
 430 #define STM_RCC_AHBENR_SRAMEN   2
 431 #define STM_RCC_AHBENR_DMA2EN   1
 432 #define STM_RCC_AHBENR_DMAEN    0
 433
 434 #define STM_RCC_APB2ENR_DBGMCUEN        22
 435 #define STM_RCC_APB2ENR_TIM17EN         18
 436 #define STM_RCC_APB2ENR_TIM16EN         17
 437 #define STM_RCC_APB2ENR_TIM15EN         16
 438 #define STM_RCC_APB2ENR_USART1EN        14
 439 #define STM_RCC_APB2ENR_SPI1EN          12
 440 #define STM_RCC_APB2ENR_TIM1EN          11
 441 #define STM_RCC_APB2ENR_ADCEN           9
 442 #define STM_RCC_APB2ENR_USART8EN        7
 443 #define STM_RCC_APB2ENR_USART7EN        6
 444 #define STM_RCC_APB2ENR_USART6EN        5
 445 #define STM_RCC_APB2ENR_SYSCFGCOMPEN    0
 446
 447 #define STM_RCC_APB1ENR_CECEN           30
 448 #define STM_RCC_APB1ENR_DACEN           29
 449 #define STM_RCC_APB1ENR_PWREN           28
 450 #define STM_RCC_APB1ENR_CRSEN           27
 451 #define STM_RCC_APB1ENR_CANEN           25
 452 #define STM_RCC_APB1ENR_USBEN           23
 453 #define STM_RCC_APB1ENR_I2C2EN          22
 454 #define STM_RCC_APB1ENR_IC21EN          21
 455 #define STM_RCC_APB1ENR_USART5EN        20
 456 #define STM_RCC_APB1ENR_USART4EN        19
 457 #define STM_RCC_APB1ENR_USART3EN        18
 458 #define STM_RCC_APB1ENR_USART2EN        17
 459 #define STM_RCC_APB1ENR_SPI2EN          14
 460 #define STM_RCC_APB1ENR_WWDGEN          11
 461 #define STM_RCC_APB1ENR_TIM14EN         8
 462 #define STM_RCC_APB1ENR_TIM7EN          5
 463 #define STM_RCC_APB1ENR_TIM6EN          4
 464 #define STM_RCC_APB1ENR_TIM3EN          1
 465 #define STM_RCC_APB1ENR_TIM2EN          0
 466
 467 #define STM_RCC_CSR_LPWRRSTF            (31)
 468 #define STM_RCC_CSR_WWDGRSTF            (30)
 469 #define STM_RCC_CSR_IWDGRSTF            (29)
 470 #define STM_RCC_CSR_SFTRSTF             (28)
 471 #define STM_RCC_CSR_PORRSTF             (27)
 472 #define STM_RCC_CSR_PINRSTF             (26)
 473 #define STM_RCC_CSR_OBLRSTF             (25)
 474 #define STM_RCC_CSR_RMVF                (24)
 475 #define STM_RCC_CSR_V18PWRRSTF          (23)
 476 #define STM_RCC_CSR_LSIRDY              (1)
 477 #define STM_RCC_CSR_LSION               (0)
 478
 479 #define STM_RCC_CR2_HSI48CAL            24
 480 #define STM_RCC_CR2_HSI48RDY            17
 481 #define STM_RCC_CR2_HSI48ON             16
 482 #define STM_RCC_CR2_HSI14CAL            8
 483 #define STM_RCC_CR2_HSI14TRIM           3
 484 #define STM_RCC_CR2_HSI14DIS            2
 485 #define STM_RCC_CR2_HSI14RDY            1
 486 #define STM_RCC_CR2_HSI14ON             0
 487
 488 #define STM_RCC_CFGR2_PREDIV            0
 489 #define  STM_RCC_CFGR2_PREDIV_1                 0x0
 490 #define  STM_RCC_CFGR2_PREDIV_2                 0x1
 491 #define  STM_RCC_CFGR2_PREDIV_3                 0x2
 492 #define  STM_RCC_CFGR2_PREDIV_4                 0x3
 493 #define  STM_RCC_CFGR2_PREDIV_5                 0x4
 494 #define  STM_RCC_CFGR2_PREDIV_6                 0x5
 495 #define  STM_RCC_CFGR2_PREDIV_7                 0x6
 496 #define  STM_RCC_CFGR2_PREDIV_8                 0x7
 497 #define  STM_RCC_CFGR2_PREDIV_9                 0x8
 498 #define  STM_RCC_CFGR2_PREDIV_10                0x9
 499 #define  STM_RCC_CFGR2_PREDIV_11                0xa
 500 #define  STM_RCC_CFGR2_PREDIV_12                0xb
 501 #define  STM_RCC_CFGR2_PREDIV_13                0xc
 502 #define  STM_RCC_CFGR2_PREDIV_14                0xd
 503 #define  STM_RCC_CFGR2_PREDIV_15                0xe
 504 #define  STM_RCC_CFGR2_PREDIV_16                0xf
 505
 506 #define STM_RCC_CFGR3_USART3SW          18
 507 #define STM_RCC_CFGR3_USART2SW          16
 508 #define STM_RCC_CFGR3_ADCSW             8
 509 #define STM_RCC_CFGR3_USBSW             7
 510 #define STM_RCC_CFGR3_CECSW             6
 511 #define STM_RCC_CFGR3_I2C1SW            4
 512 #define STM_RCC_CFGR3_USART1SW          0
 513
 514 struct stm_crs {
 515         vuint32_t       cr;
 516         vuint32_t       cfgr;
 517         vuint32_t       isr;
 518         vuint32_t       icr;
 519 };
 520
 521 extern struct stm_crs stm_crs;
 522
 523 #define STM_CRS_CR_TRIM         8
 524 #define STM_CRS_CR_SWSYNC       7
 525 #define STM_CRS_CR_AUTOTRIMEN   6
 526 #define STM_CRS_CR_CEN          5
 527 #define STM_CRS_CR_ESYNCIE      3
 528 #define STM_CRS_CR_ERRIE        2
 529 #define STM_CRS_CR_SYNCWARNIE   1
 530 #define STM_CRS_CR_SYNCOKIE     0
 531
 532 #define STM_CRS_CFGR_SYNCPOL    31
 533 #define STM_CRS_CFGR_SYNCSRC    28
 534 #define  STM_CRS_CFGR_SYNCSRC_GPIO      0
 535 #define  STM_CRS_CFGR_SYNCSRC_LSE       1
 536 #define  STM_CRS_CFGR_SYNCSRC_USB       2
 537 #define STM_CRS_CFGR_SYNCDIV    24
 538 #define  STM_CRS_CFGR_SYNCDIV_1         0
 539 #define  STM_CRS_CFGR_SYNCDIV_2         1
 540 #define  STM_CRS_CFGR_SYNCDIV_4         2
 541 #define  STM_CRS_CFGR_SYNCDIV_8         3
 542 #define  STM_CRS_CFGR_SYNCDIV_16        4
 543 #define  STM_CRS_CFGR_SYNCDIV_32        5
 544 #define  STM_CRS_CFGR_SYNCDIV_64        6
 545 #define  STM_CRS_CFGR_SYNCDIV_128       7
 546 #define STM_CRS_CFGR_FELIM      16
 547 #define STM_CRS_CFGR_RELOAD     0
 548
 549 #define STM_CRS_ISR_FECAP       16
 550 #define STM_CRS_ISR_FEDIR       15
 551 #define STM_CRS_ISR_TRIMOVF     10
 552 #define STM_CRS_ISR_SYNCMISS    9
 553 #define STM_CRS_ISR_SYNCERR     8
 554 #define STM_CRS_ISR_ESYNCF      3
 555 #define STM_CRS_ISR_ERRF        2
 556 #define STM_CRS_ISR_SYNCWARNF   1
 557 #define STM_CRS_ISR_SYNCOKF     0
 558
 559 #define STM_CRS_ICR_ESYNCC      3
 560 #define STM_CRS_ICR_ERRC        2
 561 #define STM_CRS_ICR_SYNCWARNC   1
 562 #define STM_CRS_ICR_SYNCOKC     0
 563
 564 struct stm_pwr {
 565         vuint32_t       cr;
 566         vuint32_t       csr;
 567 };
 568
 569 extern struct stm_pwr stm_pwr;
 570
 571 #define STM_PWR_CR_DBP          (8)
 572
 573 #define STM_PWR_CR_PLS          (5)
 574 #define  STM_PWR_CR_PLS_2_0     0
 575 #define  STM_PWR_CR_PLS_2_1     1
 576 #define  STM_PWR_CR_PLS_2_2     2
 577 #define  STM_PWR_CR_PLS_2_3     3
 578 #define  STM_PWR_CR_PLS_2_4     4
 579 #define  STM_PWR_CR_PLS_2_5     5
 580 #define  STM_PWR_CR_PLS_2_6     6
 581 #define  STM_PWR_CR_PLS_EXT     7
 582 #define  STM_PWR_CR_PLS_MASK    7
 583
 584 #define STM_PWR_CR_PVDE         (4)
 585 #define STM_PWR_CR_CSBF         (3)
 586 #define STM_PWR_CR_CWUF         (2)
 587 #define STM_PWR_CR_PDDS         (1)
 588 #define STM_PWR_CR_LPSDSR       (0)
 589
 590 #define STM_PWR_CSR_EWUP3       (10)
 591 #define STM_PWR_CSR_EWUP2       (9)
 592 #define STM_PWR_CSR_EWUP1       (8)
 593 #define STM_PWR_CSR_REGLPF      (5)
 594 #define STM_PWR_CSR_VOSF        (4)
 595 #define STM_PWR_CSR_VREFINTRDYF (3)
 596 #define STM_PWR_CSR_PVDO        (2)
 597 #define STM_PWR_CSR_SBF         (1)
 598 #define STM_PWR_CSR_WUF         (0)
 599
 600 struct stm_crc {
 601         union {
 602                 vuint32_t       u32;
 603                 vuint16_t       u16;
 604                 vuint8_t        u8;
 605         }               dr;
 606         vuint32_t       idr;
 607         vuint32_t       cr;
 608         uint32_t        _0c;
 609
 610         vuint32_t       init;
 611         vuint32_t       pol;
 612 };
 613
 614 extern struct stm_crc   stm_crc;
 615
 616 #define stm_crc (*((struct stm_crc *) 0x40023000))
 617
 618 #define STM_CRC_CR_REV_OUT      7
 619 #define STM_CRC_CR_REV_IN       5
 620 #define  STM_CRC_CR_REV_IN_NONE         0
 621 #define  STM_CRC_CR_REV_IN_BY_BYTE      1
 622 #define  STM_CRC_CR_REV_IN_BY_HALF_WORD 2
 623 #define  STM_CRC_CR_REV_IN_BY_WORD      3
 624 #define STM_CRC_CR_POLYSIZE     3
 625 #define  STM_CRC_CR_POLYSIZE_32         0
 626 #define  STM_CRC_CR_POLYSIZE_16         1
 627 #define  STM_CRC_CR_POLYSIZE_8          2
 628 #define  STM_CRC_CR_POLYSIZE_7          3
 629 #define STM_CRC_CR_RESET        0
 630
 631 /* The SYSTICK starts at 0xe000e010 */
 632
 633 struct stm_systick {
 634         vuint32_t       csr;
 635         vuint32_t       rvr;
 636         vuint32_t       cvr;
 637         vuint32_t       calib;
 638 };
 639
 640 extern struct stm_systick stm_systick;
 641
 642 #define STM_SYSTICK_CSR_ENABLE          0
 643 #define STM_SYSTICK_CSR_TICKINT         1
 644 #define STM_SYSTICK_CSR_CLKSOURCE       2
 645 #define  STM_SYSTICK_CSR_CLKSOURCE_EXTERNAL             0
 646 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               1
 647 #define STM_SYSTICK_CSR_COUNTFLAG       16
 648
 649 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 650
 651 struct stm_nvic {
 652         vuint32_t       iser;           /* 0x000 0xe000e100 Set Enable Register */
 653
 654         uint8_t         _unused020[0x080 - 0x004];
 655
 656         vuint32_t       icer;           /* 0x080 0xe000e180 Clear Enable Register */
 657
 658         uint8_t         _unused0a0[0x100 - 0x084];
 659
 660         vuint32_t       ispr;           /* 0x100 0xe000e200 Set Pending Register */
 661
 662         uint8_t         _unused120[0x180 - 0x104];
 663
 664         vuint32_t       icpr;           /* 0x180 0xe000e280 Clear Pending Register */
 665
 666         uint8_t         _unused1a0[0x300 - 0x184];
 667
 668         vuint32_t       ipr[8];         /* 0x300 0xe000e400 Priority Register */
 669 };
 670
 671 extern struct stm_nvic stm_nvic;
 672
 673 #define IRQ_MASK(irq)   (1 << (irq))
 674 #define IRQ_BOOL(v,irq) (((v) >> (irq)) & 1)
 675
 676 static inline void
 677 stm_nvic_set_enable(int irq) {
 678         stm_nvic.iser = IRQ_MASK(irq);
 679 }
 680
 681 static inline void
 682 stm_nvic_clear_enable(int irq) {
 683         stm_nvic.icer = IRQ_MASK(irq);
 684 }
 685
 686 static inline int
 687 stm_nvic_enabled(int irq) {
 688         return IRQ_BOOL(stm_nvic.iser, irq);
 689 }
 690
 691 static inline void
 692 stm_nvic_set_pending(int irq) {
 693         stm_nvic.ispr = IRQ_MASK(irq);
 694 }
 695
 696 static inline void
 697 stm_nvic_clear_pending(int irq) {
 698         stm_nvic.icpr = IRQ_MASK(irq);
 699 }
 700
 701 static inline int
 702 stm_nvic_pending(int irq) {
 703         return IRQ_BOOL(stm_nvic.ispr, irq);
 704 }
 705
 706 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 707 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 708 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 709
 710 static inline void
 711 stm_nvic_set_priority(int irq, uint8_t prio) {
 712         int             n = IRQ_PRIO_REG(irq);
 713         uint32_t        v;
 714
 715         v = stm_nvic.ipr[n];
 716         v &= ~IRQ_PRIO_MASK(irq);
 717         v |= (prio) << IRQ_PRIO_BIT(irq);
 718         stm_nvic.ipr[n] = v;
 719 }
 720
 721 static inline uint8_t
 722 stm_nvic_get_priority(int irq) {
 723         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 724 }
 725
 726 struct stm_scb {
 727         vuint32_t       cpuid;
 728         vuint32_t       icsr;
 729         vuint32_t       vtor;
 730         vuint32_t       aircr;
 731
 732         vuint32_t       scr;
 733         vuint32_t       ccr;
 734         vuint32_t       shpr1;
 735         vuint32_t       shpr2;
 736
 737         vuint32_t       shpr3;
 738         vuint32_t       shcrs;
 739         vuint32_t       cfsr;
 740         vuint32_t       hfsr;
 741
 742         uint32_t        unused_30;
 743         vuint32_t       mmfar;
 744         vuint32_t       bfar;
 745 };
 746
 747 extern struct stm_scb stm_scb;
 748
 749 #define STM_SCB_AIRCR_VECTKEY           16
 750 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
 751 #define STM_SCB_AIRCR_PRIGROUP          8
 752 #define STM_SCB_AIRCR_SYSRESETREQ       2
 753 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
 754 #define STM_SCB_AIRCR_VECTRESET         0
 755
 756 #define STM_ISR_WWDG_POS                0
 757 #define STM_ISR_PVD_VDDIO2_POS          1
 758 #define STM_ISR_RTC_POS                 2
 759 #define STM_ISR_FLASH_POS               3
 760 #define STM_ISR_RCC_CRS_POS             4
 761 #define STM_ISR_EXTI0_1_POS             5
 762 #define STM_ISR_EXTI2_3_POS             6
 763 #define STM_ISR_EXTI4_15_POS            7
 764 #define STM_ISR_TSC_POS                 8
 765 #define STM_ISR_DMA_CH1_POS             9
 766 #define STM_ISR_DMA_CH2_3_DMA2_CH1_2_POS        10
 767 #define STM_ISR_DMA_CH4_5_6_7_DMA2_CH3_4_5_POS  11
 768 #define STM_ISR_ADC_COMP_POS            12
 769 #define STM_ISR_TIM1_BRK_UP_TRG_COM_POS 13
 770 #define STM_ISR_TIM1_CC_POS             14
 771 #define STM_ISR_TIM2_POS                15
 772 #define STM_ISR_TIM3_POS                16
 773 #define STM_ISR_TIM6_DAC_POS            17
 774 #define STM_ISR_TIM7_POS                18
 775 #define STM_ISR_TIM14_POS               19
 776 #define STM_ISR_TIM15_POS               20
 777 #define STM_ISR_TIM16_POS               21
 778 #define STM_ISR_TIM17_POS               22
 779 #define STM_ISR_I2C1_POS                23
 780 #define STM_ISR_I2C2_POS                24
 781 #define STM_ISR_SPI1_POS                25
 782 #define STM_ISR_SPI2_POS                26
 783 #define STM_ISR_USART1_POS              27
 784 #define STM_ISR_USART2_POS              28
 785 #define STM_ISR_UASART3_4_5_6_7_8_POS   29
 786 #define STM_ISR_CEC_CAN_POS             30
 787 #define STM_ISR_USB_POS                 31
 788
 789 struct stm_syscfg {
 790         vuint32_t       cfgr1;
 791         uint32_t        reserved_04;
 792         vuint32_t       exticr[4];
 793         vuint32_t       cfgr2;
 794         uint8_t         reserved_1c[0x80-0x1c];
 795         vuint32_t       itline[31];
 796 };
 797
 798 extern struct stm_syscfg stm_syscfg;
 799
 800 #define STM_SYSCFG_CFGR1_TIM3_DMA_RMP   30
 801 #define STM_SYSCFG_CFGR1_TIM2_DMA_RMP   29
 802 #define STM_SYSCFG_CFGR1_TIM1_DMA_RMP   28
 803 #define STM_SYSCFG_CFGR1_I2C1_DMA_RMP   27
 804 #define STM_SYSCFG_CFGR1_USART3_DMA_RMP 26
 805 #define STM_SYSCFG_CFGR1_USART2_DMA_RMP 25
 806 #define STM_SYSCFG_CFGR1_SPI2_DMA_RMP   24
 807 #define STM_SYSCFG_CFGR1_I2C_PA10_FMP   23
 808 #define STM_SYSCFG_CFGR1_I2C_PA9_FMP    22
 809 #define STM_SYSCFG_CFGR1_I2C2_FMP       21
 810 #define STM_SYSCFG_CFGR1_I2C1_FMP       20
 811 #define STM_SYSCFG_CFGR1_I2C_PB9_FMP    19
 812 #define STM_SYSCFG_CFGR1_I2C_PB8_FMP    18
 813 #define STM_SYSCFG_CFGR1_I2C_PB7_FMP    17
 814 #define STM_SYSCFG_CFGR1_I2C_PB6_FMP    16
 815 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP2 14
 816 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP2 13
 817 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP  12
 818 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP  11
 819 #define STM_SYSCFG_CFGR1_USART1_RX_DMA_RMP      10
 820 #define STM_SYSCFG_CFGR1_USART1_TX_DMA_RMP      9
 821 #define STM_SYSCFG_CFGR1_ADC_DMA_RMP            8
 822 #define STM_SYSCFG_CFGR1_IRDA_ENV_SEL   6
 823 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_TIMER16  0
 824 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART1   1
 825 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART4   2
 826 #define STM_SYSCFG_CFGR1_PA11_PA12_RMP  4
 827 #define STM_SYSCFG_CFGR1_MEM_MODE       0
 828 #define  STM_SYSCFG_CFGR1_MEM_MODE_MAIN_FLASH   0
 829 #define  STM_SYSCFG_CFGR1_MEM_MODE_SYSTEM_FLASH 1
 830 #define  STM_SYSCFG_CFGR1_MEM_MODE_SRAM         3
 831 #define  STM_SYSCFG_CFGR1_MEM_MODE_MASK         3
 832
 833 #define STM_SYSCFG_EXTICR_PA            0
 834 #define STM_SYSCFG_EXTICR_PB            1
 835 #define STM_SYSCFG_EXTICR_PC            2
 836 #define STM_SYSCFG_EXTICR_PD            3
 837 #define STM_SYSCFG_EXTICR_PE            4
 838 #define STM_SYSCFG_EXTICR_PF            5
 839
 840 static inline void
 841 stm_exticr_set(struct stm_gpio *gpio, int pin) {
 842         uint8_t reg = pin >> 2;
 843         uint8_t shift = (pin & 3) << 2;
 844         uint8_t val = 0;
 845
 846         /* Enable SYSCFG */
 847         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
 848
 849         if (gpio == &stm_gpioa)
 850                 val = STM_SYSCFG_EXTICR_PA;
 851         else if (gpio == &stm_gpiob)
 852                 val = STM_SYSCFG_EXTICR_PB;
 853         else if (gpio == &stm_gpioc)
 854                 val = STM_SYSCFG_EXTICR_PC;
 855         else if (gpio == &stm_gpiof)
 856                 val = STM_SYSCFG_EXTICR_PF;
 857
 858         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
 859 }
 860
 861 struct stm_dma_channel {
 862         vuint32_t       ccr;
 863         vuint32_t       cndtr;
 864         vvoid_t         cpar;
 865         vvoid_t         cmar;
 866         vuint32_t       reserved;
 867 };
 868
 869 #define STM_NUM_DMA     5
 870
 871 struct stm_dma {
 872         vuint32_t               isr;
 873         vuint32_t               ifcr;
 874         struct stm_dma_channel  channel[STM_NUM_DMA];
 875 };
 876
 877 extern struct stm_dma stm_dma;
 878
 879 /* DMA channels go from 1 to 5, instead of 0 to 4 (sigh)
 880  */
 881
 882 #define STM_DMA_INDEX(channel)          ((channel) - 1)
 883
 884 #define STM_DMA_ISR(index)              ((index) << 2)
 885 #define STM_DMA_ISR_MASK                        0xf
 886 #define STM_DMA_ISR_TEIF                        3
 887 #define STM_DMA_ISR_HTIF                        2
 888 #define STM_DMA_ISR_TCIF                        1
 889 #define STM_DMA_ISR_GIF                         0
 890
 891 #define STM_DMA_IFCR(index)             ((index) << 2)
 892 #define STM_DMA_IFCR_MASK                       0xf
 893 #define STM_DMA_IFCR_CTEIF                      3
 894 #define STM_DMA_IFCR_CHTIF                      2
 895 #define STM_DMA_IFCR_CTCIF                      1
 896 #define STM_DMA_IFCR_CGIF                       0
 897
 898 #define STM_DMA_CCR_MEM2MEM             (14)
 899
 900 #define STM_DMA_CCR_PL                  (12)
 901 #define  STM_DMA_CCR_PL_LOW                     (0)
 902 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
 903 #define  STM_DMA_CCR_PL_HIGH                    (2)
 904 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
 905 #define  STM_DMA_CCR_PL_MASK                    (3)
 906
 907 #define STM_DMA_CCR_MSIZE               (10)
 908 #define  STM_DMA_CCR_MSIZE_8                    (0)
 909 #define  STM_DMA_CCR_MSIZE_16                   (1)
 910 #define  STM_DMA_CCR_MSIZE_32                   (2)
 911 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
 912
 913 #define STM_DMA_CCR_PSIZE               (8)
 914 #define  STM_DMA_CCR_PSIZE_8                    (0)
 915 #define  STM_DMA_CCR_PSIZE_16                   (1)
 916 #define  STM_DMA_CCR_PSIZE_32                   (2)
 917 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
 918
 919 #define STM_DMA_CCR_MINC                (7)
 920 #define STM_DMA_CCR_PINC                (6)
 921 #define STM_DMA_CCR_CIRC                (5)
 922 #define STM_DMA_CCR_DIR                 (4)
 923 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
 924 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
 925 #define STM_DMA_CCR_TEIE                (3)
 926 #define STM_DMA_CCR_HTIE                (2)
 927 #define STM_DMA_CCR_TCIE                (1)
 928 #define STM_DMA_CCR_EN                  (0)
 929
 930 /* DMA channel assignments. When a peripheral has multiple channels
 931  * (indicated with _<number>), then it can be configured to either
 932  * channel using syscfg.cfgr1
 933  */
 934
 935 #define STM_DMA_CHANNEL_ADC_1           1
 936 #define STM_DMA_CHANNEL_ADC_2           2
 937
 938 #define STM_DMA_CHANNEL_SPI1_RX         2
 939 #define STM_DMA_CHANNEL_SPI1_TX         3
 940
 941 #define STM_DMA_CHANNEL_SPI2_RX         4
 942 #define STM_DMA_CHANNEL_SPI2_TX         5
 943
 944 #define STM_DMA_CHANNEL_USART1_TX_1     2
 945 #define STM_DMA_CHANNEL_USART1_RX_1     3
 946 #define STM_DMA_CHANNEL_USART1_TX_2     4
 947 #define STM_DMA_CHANNEL_USART1_RX_2     5
 948
 949 #define STM_DMA_CHANNEL_USART2_RX       4
 950 #define STM_DMA_CHANNEL_USART2_TX       5
 951
 952 #define STM_DMA_CHANNEL_I2C1_TX         2
 953 #define STM_DMA_CHANNEL_I2C1_RX         3
 954
 955 #define STM_DMA_CHANNEL_I2C2_TX         4
 956 #define STM_DMA_CHANNEL_I2C2_RX         5
 957
 958 #define STM_DMA_CHANNEL_TIM1_CH1        2
 959 #define STM_DMA_CHANNEL_TIM1_CH2        3
 960 #define STM_DMA_CHANNEL_TIM1_CH4        4
 961 #define STM_DMA_CHANNEL_TIM1_TRIG       4
 962 #define STM_DMA_CHANNEL_TIM1_COM        4
 963 #define STM_DMA_CHANNEL_TIM1_CH3        5
 964 #define STM_DMA_CHANNEL_TIM1_UP         5
 965
 966 #define STM_DMA_CHANNEL_TIM2_CH3        1
 967 #define STM_DMA_CHANNEL_TIM2_UP         2
 968 #define STM_DMA_CHANNEL_TIM2_CH2        3
 969 #define STM_DMA_CHANNEL_TIM2_CH4        4
 970 #define STM_DMA_CHANNEL_TIM2_CH1        5
 971
 972 #define STM_DMA_CHANNEL_TIM3_CH3        2
 973 #define STM_DMA_CHANNEL_TIM3_CH4        3
 974 #define STM_DMA_CHANNEL_TIM3_UP         3
 975 #define STM_DMA_CHANNEL_TIM3_CH1        4
 976 #define STM_DMA_CHANNEL_TIM3_TRIG       4
 977
 978 #define STM_DMA_CHANNEL_TIM6_UP_DAC     2
 979
 980 #define STM_DMA_CHANNEL_TIM15_CH1       5
 981 #define STM_DMA_CHANNEL_TIM15_UP        5
 982 #define STM_DMA_CHANNEL_TIM15_TRIG      5
 983 #define STM_DMA_CHANNEL_TIM15_COM       5
 984
 985 #define STM_DMA_CHANNEL_TIM16_CH1_1     3
 986 #define STM_DMA_CHANNEL_TIM16_UP_1      3
 987 #define STM_DMA_CHANNEL_TIM16_CH1_2     4
 988 #define STM_DMA_CHANNEL_TIM16_UP_2      4
 989
 990 #define STM_DMA_CHANNEL_TIM17_CH1_1     1
 991 #define STM_DMA_CHANNEL_TIM17_UP_1      1
 992 #define STM_DMA_CHANNEL_TIM17_CH1_2     2
 993 #define STM_DMA_CHANNEL_TIM17_UP_2      2
 994
 995 /*
 996  * Only spi channel 1 and 2 can use DMA
 997  */
 998 #define STM_NUM_SPI     2
 999
1000 struct stm_spi {
1001         vuint32_t       cr1;
1002         vuint32_t       cr2;
1003         vuint32_t       sr;
1004         vuint32_t       dr;
1005         vuint32_t       crcpr;
1006         vuint32_t       rxcrcr;
1007         vuint32_t       txcrcr;
1008 };
1009
1010 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1011
1012 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1013  */
1014
1015 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1016
1017 #define STM_SPI_CR1_BIDIMODE            15
1018 #define STM_SPI_CR1_BIDIOE              14
1019 #define STM_SPI_CR1_CRCEN               13
1020 #define STM_SPI_CR1_CRCNEXT             12
1021 #define STM_SPI_CR1_CRCL                11
1022 #define STM_SPI_CR1_RXONLY              10
1023 #define STM_SPI_CR1_SSM                 9
1024 #define STM_SPI_CR1_SSI                 8
1025 #define STM_SPI_CR1_LSBFIRST            7
1026 #define STM_SPI_CR1_SPE                 6
1027 #define STM_SPI_CR1_BR                  3
1028 #define  STM_SPI_CR1_BR_PCLK_2                  0
1029 #define  STM_SPI_CR1_BR_PCLK_4                  1
1030 #define  STM_SPI_CR1_BR_PCLK_8                  2
1031 #define  STM_SPI_CR1_BR_PCLK_16                 3
1032 #define  STM_SPI_CR1_BR_PCLK_32                 4
1033 #define  STM_SPI_CR1_BR_PCLK_64                 5
1034 #define  STM_SPI_CR1_BR_PCLK_128                6
1035 #define  STM_SPI_CR1_BR_PCLK_256                7
1036 #define  STM_SPI_CR1_BR_MASK                    7
1037
1038 #define STM_SPI_CR1_MSTR                2
1039 #define STM_SPI_CR1_CPOL                1
1040 #define STM_SPI_CR1_CPHA                0
1041
1042 #define STM_SPI_CR2_LDMA_TX     14
1043 #define STM_SPI_CR2_LDMA_RX     13
1044 #define STM_SPI_CR2_FRXTH       12
1045 #define STM_SPI_CR2_DS          8
1046 #define  STM_SPI_CR2_DS_4               0x3
1047 #define  STM_SPI_CR2_DS_5               0x4
1048 #define  STM_SPI_CR2_DS_6               0x5
1049 #define  STM_SPI_CR2_DS_7               0x6
1050 #define  STM_SPI_CR2_DS_8               0x7
1051 #define  STM_SPI_CR2_DS_9               0x8
1052 #define  STM_SPI_CR2_DS_10              0x9
1053 #define  STM_SPI_CR2_DS_11              0xa
1054 #define  STM_SPI_CR2_DS_12              0xb
1055 #define  STM_SPI_CR2_DS_13              0xc
1056 #define  STM_SPI_CR2_DS_14              0xd
1057 #define  STM_SPI_CR2_DS_15              0xe
1058 #define  STM_SPI_CR2_DS_16              0xf
1059 #define STM_SPI_CR2_TXEIE       7
1060 #define STM_SPI_CR2_RXNEIE      6
1061 #define STM_SPI_CR2_ERRIE       5
1062 #define STM_SPI_CR2_FRF         4
1063 # define STM_SPI_CR2_FRF_MOTOROLA       0
1064 # define STM_SPI_CR2_FRF_TI             1
1065 #define STM_SPI_CR2_NSSP        3
1066 #define STM_SPI_CR2_SSOE        2
1067 #define STM_SPI_CR2_TXDMAEN     1
1068 #define STM_SPI_CR2_RXDMAEN     0
1069
1070 #define STM_SPI_SR_FTLVL        11
1071 #define STM_SPI_SR_FRLVL        9
1072 #define STM_SPI_SR_FRE          8
1073 #define STM_SPI_SR_BSY          7
1074 #define STM_SPI_SR_OVR          6
1075 #define STM_SPI_SR_MODF         5
1076 #define STM_SPI_SR_CRCERR       4
1077 #define STM_SPI_SR_UDR          3
1078 #define STM_SPI_SR_CHSIDE       2
1079 #define STM_SPI_SR_TXE          1
1080 #define STM_SPI_SR_RXNE         0
1081
1082 struct stm_adc {
1083         vuint32_t       isr;
1084         vuint32_t       ier;
1085         vuint32_t       cr;
1086         vuint32_t       cfgr1;
1087
1088         vuint32_t       cfgr2;
1089         vuint32_t       smpr;
1090         vuint32_t       r_18;
1091         vuint32_t       r_1c;
1092
1093         vuint32_t       tr;
1094         vuint32_t       r_24;
1095         vuint32_t       chselr;
1096         vuint32_t       r_2c;
1097
1098         vuint32_t       r_30[4];
1099
1100         vuint32_t       dr;
1101
1102         uint8_t         r_44[0x308 - 0x44];
1103         vuint32_t       ccr;
1104 };
1105
1106 extern struct stm_adc stm_adc;
1107
1108 #define STM_ADC_ISR_AWD         7
1109 #define STM_ADC_ISR_OVR         4
1110 #define STM_ADC_ISR_EOSEQ       3
1111 #define STM_ADC_ISR_EOC         2
1112 #define STM_ADC_ISR_EOSMP       1
1113 #define STM_ADC_ISR_ADRDY       0
1114
1115 #define STM_ADC_IER_AWDIE       7
1116 #define STM_ADC_IER_OVRIE       4
1117 #define STM_ADC_IER_EOSEQIE     3
1118 #define STM_ADC_IER_EOCIE       2
1119 #define STM_ADC_IER_EOSMPIE     1
1120 #define STM_ADC_IER_ADRDYIE     0
1121
1122 #define STM_ADC_CR_ADCAL        31
1123 #define STM_ADC_CR_ADSTP        4
1124 #define STM_ADC_CR_ADSTART      2
1125 #define STM_ADC_CR_ADDIS        1
1126 #define STM_ADC_CR_ADEN         0
1127
1128 #define STM_ADC_CFGR1_AWDCH     26
1129 #define STM_ADC_CFGR1_AWDEN     23
1130 #define STM_ADC_CFGR1_AWDSGL    22
1131 #define STM_ADC_CFGR1_DISCEN    16
1132 #define STM_ADC_CFGR1_AUTOOFF   15
1133 #define STM_ADC_CFGR1_WAIT      14
1134 #define STM_ADC_CFGR1_CONT      13
1135 #define STM_ADC_CFGR1_OVRMOD    12
1136 #define STM_ADC_CFGR1_EXTEN     10
1137 #define  STM_ADC_CFGR1_EXTEN_DISABLE    0
1138 #define  STM_ADC_CFGR1_EXTEN_RISING     1
1139 #define  STM_ADC_CFGR1_EXTEN_FALLING    2
1140 #define  STM_ADC_CFGR1_EXTEN_BOTH       3
1141 #define  STM_ADC_CFGR1_EXTEN_MASK       3
1142
1143 #define STM_ADC_CFGR1_EXTSEL    6
1144 #define STM_ADC_CFGR1_ALIGN     5
1145 #define STM_ADC_CFGR1_RES       3
1146 #define  STM_ADC_CFGR1_RES_12           0
1147 #define  STM_ADC_CFGR1_RES_10           1
1148 #define  STM_ADC_CFGR1_RES_8            2
1149 #define  STM_ADC_CFGR1_RES_6            3
1150 #define  STM_ADC_CFGR1_RES_MASK         3
1151 #define STM_ADC_CFGR1_SCANDIR   2
1152 #define  STM_ADC_CFGR1_SCANDIR_UP       0
1153 #define  STM_ADC_CFGR1_SCANDIR_DOWN     1
1154 #define STM_ADC_CFGR1_DMACFG    1
1155 #define  STM_ADC_CFGR1_DMACFG_ONESHOT   0
1156 #define  STM_ADC_CFGR1_DMACFG_CIRCULAR  1
1157 #define STM_ADC_CFGR1_DMAEN     0
1158
1159 #define STM_ADC_CFGR2_CKMODE    30
1160 #define  STM_ADC_CFGR2_CKMODE_ADCCLK    0
1161 #define  STM_ADC_CFGR2_CKMODE_PCLK_2    1
1162 #define  STM_ADC_CFGR2_CKMODE_PCLK_4    2
1163
1164 #define STM_ADC_SMPR_SMP        0
1165 #define  STM_ADC_SMPR_SMP_1_5           0
1166 #define  STM_ADC_SMPR_SMP_7_5           1
1167 #define  STM_ADC_SMPR_SMP_13_5          2
1168 #define  STM_ADC_SMPR_SMP_28_5          3
1169 #define  STM_ADC_SMPR_SMP_41_5          4
1170 #define  STM_ADC_SMPR_SMP_55_5          5
1171 #define  STM_ADC_SMPR_SMP_71_5          6
1172 #define  STM_ADC_SMPR_SMP_239_5         7
1173
1174 #define STM_ADC_TR_HT           16
1175 #define STM_ADC_TR_LT           0
1176
1177 #define STM_ADC_CCR_VBATEN      24
1178 #define STM_ADC_CCR_TSEN        23
1179 #define STM_ADC_CCR_VREFEN      22
1180
1181 struct stm_cal {
1182         uint16_t        ts_cal_cold;    /* 30°C */
1183         uint16_t        vrefint_cal;
1184         uint16_t        unused_c0;
1185         uint16_t        ts_cal_hot;     /* 110°C */
1186 };
1187
1188 extern struct stm_cal   stm_cal;
1189
1190 #define stm_temp_cal_cold       30
1191 #define stm_temp_cal_hot        110
1192
1193 struct stm_dbgmcu {
1194         uint32_t        idcode;
1195 };
1196
1197 extern struct stm_dbgmcu        stm_dbgmcu;
1198
1199 static inline uint16_t
1200 stm_dev_id(void) {
1201         return stm_dbgmcu.idcode & 0xfff;
1202 }
1203
1204 struct stm_flash_size {
1205         uint16_t        f_size;
1206 };
1207
1208 extern struct stm_flash_size    stm_flash_size_04x;
1209
1210 /* Returns flash size in bytes */
1211 extern uint32_t
1212 stm_flash_size(void);
1213
1214 struct stm_device_id {
1215         uint32_t        u_id0;
1216         uint32_t        u_id1;
1217         uint32_t        u_id2;
1218 };
1219
1220 extern struct stm_device_id     stm_device_id;
1221
1222 #define STM_NUM_I2C     2
1223
1224 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1225
1226 struct stm_i2c {
1227         vuint32_t       cr1;
1228         vuint32_t       cr2;
1229         vuint32_t       oar1;
1230         vuint32_t       oar2;
1231         vuint32_t       dr;
1232         vuint32_t       sr1;
1233         vuint32_t       sr2;
1234         vuint32_t       ccr;
1235         vuint32_t       trise;
1236 };
1237
1238 extern struct stm_i2c stm_i2c1, stm_i2c2;
1239
1240 #define STM_I2C_CR1_SWRST       15
1241 #define STM_I2C_CR1_ALERT       13
1242 #define STM_I2C_CR1_PEC         12
1243 #define STM_I2C_CR1_POS         11
1244 #define STM_I2C_CR1_ACK         10
1245 #define STM_I2C_CR1_STOP        9
1246 #define STM_I2C_CR1_START       8
1247 #define STM_I2C_CR1_NOSTRETCH   7
1248 #define STM_I2C_CR1_ENGC        6
1249 #define STM_I2C_CR1_ENPEC       5
1250 #define STM_I2C_CR1_ENARP       4
1251 #define STM_I2C_CR1_SMBTYPE     3
1252 #define STM_I2C_CR1_SMBUS       1
1253 #define STM_I2C_CR1_PE          0
1254
1255 #define STM_I2C_CR2_LAST        12
1256 #define STM_I2C_CR2_DMAEN       11
1257 #define STM_I2C_CR2_ITBUFEN     10
1258 #define STM_I2C_CR2_ITEVTEN     9
1259 #define STM_I2C_CR2_ITERREN     8
1260 #define STM_I2C_CR2_FREQ        0
1261 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1262 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1263 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1264 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1265 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1266 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1267
1268 #define STM_I2C_SR1_SMBALERT    15
1269 #define STM_I2C_SR1_TIMEOUT     14
1270 #define STM_I2C_SR1_PECERR      12
1271 #define STM_I2C_SR1_OVR         11
1272 #define STM_I2C_SR1_AF          10
1273 #define STM_I2C_SR1_ARLO        9
1274 #define STM_I2C_SR1_BERR        8
1275 #define STM_I2C_SR1_TXE         7
1276 #define STM_I2C_SR1_RXNE        6
1277 #define STM_I2C_SR1_STOPF       4
1278 #define STM_I2C_SR1_ADD10       3
1279 #define STM_I2C_SR1_BTF         2
1280 #define STM_I2C_SR1_ADDR        1
1281 #define STM_I2C_SR1_SB          0
1282
1283 #define STM_I2C_SR2_PEC         8
1284 #define  STM_I2C_SR2_PEC_MASK   0xff00
1285 #define STM_I2C_SR2_DUALF       7
1286 #define STM_I2C_SR2_SMBHOST     6
1287 #define STM_I2C_SR2_SMBDEFAULT  5
1288 #define STM_I2C_SR2_GENCALL     4
1289 #define STM_I2C_SR2_TRA         2
1290 #define STM_I2C_SR2_BUSY        1
1291 #define STM_I2C_SR2_MSL         0
1292
1293 #define STM_I2C_CCR_FS          15
1294 #define STM_I2C_CCR_DUTY        14
1295 #define STM_I2C_CCR_CCR         0
1296 #define  STM_I2C_CCR_MASK       0x7ff
1297
1298 struct stm_tim1 {
1299         vuint32_t       cr1;
1300         vuint32_t       cr2;
1301         vuint32_t       smcr;
1302         vuint32_t       dier;
1303
1304         vuint32_t       sr;
1305         vuint32_t       egr;
1306         vuint32_t       ccmr1;
1307         vuint32_t       ccmr2;
1308
1309         vuint32_t       ccer;
1310         vuint32_t       cnt;
1311         vuint32_t       psc;
1312         vuint32_t       arr;
1313
1314         vuint32_t       rcr;
1315         vuint32_t       ccr1;
1316         vuint32_t       ccr2;
1317         vuint32_t       ccr3;
1318
1319         vuint32_t       ccr4;
1320         vuint32_t       bdtr;
1321         vuint32_t       dcr;
1322         vuint32_t       dmar;
1323 };
1324
1325 #define STM_TIM1_CR1_CKD        8
1326 #define  STM_TIM1_CR1_CKD_1             0
1327 #define  STM_TIM1_CR1_CKD_2             1
1328 #define  STM_TIM1_CR1_CKD_4             2
1329
1330 #define STM_TIM1_CR1_ARPE       7
1331
1332 #define STM_TIM1_CR1_CMS        5
1333 #define  STM_TIM1_CR1_CMS_EDGE          0
1334 #define  STM_TIM1_CR1_CMS_CENTER_1      1
1335 #define  STM_TIM1_CR1_CMS_CENTER_2      2
1336 #define  STM_TIM1_CR1_CMS_CENTER_3      3
1337
1338 #define STM_TIM1_CR1_DIR        4
1339 #define  STM_TIM1_CR1_DIR_UP            0
1340 #define  STM_TIM1_CR1_DIR_DOWn          1
1341 #define STM_TIM1_CR1_OPM        3
1342 #define STM_TIM1_CR1_URS        2
1343 #define STM_TIM1_CR1_UDIS       1
1344 #define STM_TIM1_CR1_CEN        0
1345
1346 #define STM_TIM1_CR2_OIS4       14
1347 #define STM_TIM1_CR2_OIS3N      13
1348 #define STM_TIM1_CR2_OIS3       12
1349 #define STM_TIM1_CR2_OIS2N      11
1350 #define STM_TIM1_CR2_OIS2       10
1351 #define STM_TIM1_CR2_OIS1N      9
1352 #define STM_TIM1_CR2_OSI1       8
1353 #define STM_TIM1_CR2_TI1S       7
1354 #define STM_TIM1_CR2_MMS        4
1355 #define  STM_TIM1_CR2_MMS_RESET                 0
1356 #define  STM_TIM1_CR2_MMS_ENABLE                1
1357 #define  STM_TIM1_CR2_MMS_UPDATE                2
1358 #define  STM_TIM1_CR2_MMS_COMPARE_PULSE         3
1359 #define  STM_TIM1_CR2_MMS_COMPARE_OC1REF        4
1360 #define  STM_TIM1_CR2_MMS_COMPARE_OC2REF        5
1361 #define  STM_TIM1_CR2_MMS_COMPARE_OC3REF        6
1362 #define  STM_TIM1_CR2_MMS_COMPARE_OC4REF        7
1363 #define STM_TIM1_CR2_CCDS       3
1364 #define STM_TIM1_CR2_CCUS       2
1365 #define STM_TIM1_CR2_CCPC       0
1366
1367 #define STM_TIM1_SMCR_ETP       15
1368 #define STM_TIM1_SMCR_ECE       14
1369 #define STM_TIM1_SMCR_ETPS      12
1370 #define  STM_TIM1_SMCR_ETPS_OFF         0
1371 #define  STM_TIM1_SMCR_ETPS_DIV_2       1
1372 #define  STM_TIM1_SMCR_ETPS_DIV_4       2
1373 #define  STM_TIM1_SMCR_ETPS_DIV_8       3
1374
1375 #define STM_TIM1_SMCR_ETF       8
1376 #define  STM_TIM1_SMCR_ETF_NONE         0
1377 #define  STM_TIM1_SMCR_ETF_DIV_1_N_2    1
1378 #define  STM_TIM1_SMCR_ETF_DIV_1_N_4    2
1379 #define  STM_TIM1_SMCR_ETF_DIV_1_N_8    3
1380 #define  STM_TIM1_SMCR_ETF_DIV_2_N_6    4
1381 #define  STM_TIM1_SMCR_ETF_DIV_2_N_8    5
1382 #define  STM_TIM1_SMCR_ETF_DIV_4_N_6    6
1383 #define  STM_TIM1_SMCR_ETF_DIV_4_N_8    7
1384 #define  STM_TIM1_SMCR_ETF_DIV_8_N_6    8
1385 #define  STM_TIM1_SMCR_ETF_DIV_8_N_8    9
1386 #define  STM_TIM1_SMCR_ETF_DIV_16_N_5   10
1387 #define  STM_TIM1_SMCR_ETF_DIV_16_N_6   11
1388 #define  STM_TIM1_SMCR_ETF_DIV_16_N_8   12
1389 #define  STM_TIM1_SMCR_ETF_DIV_32_N_5   13
1390 #define  STM_TIM1_SMCR_ETF_DIV_32_N_6   14
1391 #define  STM_TIM1_SMCR_ETF_DIV_32_N_8   15
1392
1393 #define STM_TIM1_SMCR_MSM       7
1394 #define STM_TIM1_SMCR_TS        4
1395 #define  STM_TIM1_SMCR_TS_ITR0          0
1396 #define  STM_TIM1_SMCR_TS_ITR1          1
1397 #define  STM_TIM1_SMCR_TS_ITR2          2
1398 #define  STM_TIM1_SMCR_TS_ITR3          3
1399 #define  STM_TIM1_SMCR_TS_TI1F_ED       4
1400 #define  STM_TIM1_SMCR_TS_TI1FP1        5
1401 #define  STM_TIM1_SMCR_TS_TI2FP2        6
1402 #define  STM_TIM1_SMCR_TS_ETRF          7
1403
1404 #define STM_TIM1_SMCR_OCCS      3
1405 #define STM_TIM1_SMCR_SMS       0
1406 #define  STM_TIM1_SMCR_SMS_DISABLE      0
1407 #define  STM_TIM1_SMCR_SMS_ENCODER_1    1
1408 #define  STM_TIM1_SMCR_SMS_ENCODER_2    2
1409 #define  STM_TIM1_SMCR_SMS_ENCODER_3    3
1410 #define  STM_TIM1_SMCR_SMS_RESET        4
1411 #define  STM_TIM1_SMCR_SMS_GATED        5
1412 #define  STM_TIM1_SMCR_SMS_TRIGGER      6
1413 #define  STM_TIM1_SMCR_SMS_EXTERNAL     7
1414
1415 #define STM_TIM1_DIER_TDE       14
1416 #define STM_TIM1_DIER_COMDE     13
1417 #define STM_TIM1_DIER_CC4DE     12
1418 #define STM_TIM1_DIER_CC3DE     11
1419 #define STM_TIM1_DIER_CC2DE     10
1420 #define STM_TIM1_DIER_CC1DE     9
1421 #define STM_TIM1_DIER_UDE       8
1422 #define STM_TIM1_DIER_BIE       7
1423 #define STM_TIM1_DIER_TIE       6
1424 #define STM_TIM1_DIER_COMIE     5
1425 #define STM_TIM1_DIER_CC4IE     4
1426 #define STM_TIM1_DIER_CC3IE     3
1427 #define STM_TIM1_DIER_CC2IE     2
1428 #define STM_TIM1_DIER_CC1IE     1
1429 #define STM_TIM1_DIER_UIE       0
1430
1431 #define STM_TIM1_SR_CC4OF       12
1432 #define STM_TIM1_SR_CC3OF       11
1433 #define STM_TIM1_SR_CC2OF       10
1434 #define STM_TIM1_SR_CC1OF       9
1435 #define STM_TIM1_SR_BIF         7
1436 #define STM_TIM1_SR_TIF         6
1437 #define STM_TIM1_SR_COMIF       5
1438 #define STM_TIM1_SR_CC4IF       4
1439 #define STM_TIM1_SR_CC3IF       3
1440 #define STM_TIM1_SR_CC2IF       2
1441 #define STM_TIM1_SR_CC1IF       1
1442 #define STM_TIM1_SR_UIF         0
1443
1444 #define STM_TIM1_EGR_BG         7
1445 #define STM_TIM1_EGR_TG         6
1446 #define STM_TIM1_EGR_COMG       5
1447 #define STM_TIM1_EGR_CC4G       4
1448 #define STM_TIM1_EGR_CC3G       3
1449 #define STM_TIM1_EGR_CC2G       2
1450 #define STM_TIM1_EGR_CC1G       1
1451 #define STM_TIM1_EGR_UG         0
1452
1453 #define STM_TIM1_CCMR1_OC2CE    15
1454 #define STM_TIM1_CCMR1_OC2M     12
1455 #define STM_TIM1_CCMR1_OC2PE    11
1456 #define STM_TIM1_CCMR1_OC2FE    10
1457 #define STM_TIM1_CCMR1_CC2S     8
1458 #define STM_TIM1_CCMR1_OC1CE    7
1459 #define STM_TIM1_CCMR1_OC1M     4
1460 #define  STM_TIM1_CCMR_OCM_FROZEN               0
1461 #define  STM_TIM1_CCMR_OCM_1_HIGH_MATCH         1
1462 #define  STM_TIM1_CCMR_OCM_1_LOW_MATCH          2
1463 #define  STM_TIM1_CCMR_OCM_TOGGLE               3
1464 #define  STM_TIM1_CCMR_OCM_FORCE_LOW            4
1465 #define  STM_TIM1_CCMR_OCM_FORCE_HIGH           5
1466 #define  STM_TIM1_CCMR_OCM_PWM_MODE_1           6
1467 #define  STM_TIM1_CCMR_OCM_PWM_MODE_2           7
1468
1469 #define STM_TIM1_CCMR1_OC1PE    3
1470 #define STM_TIM1_CCMR1_OC1FE    2
1471 #define STM_TIM1_CCMR1_CC1S     0
1472 #define  STM_TIM1_CCMR_CCS_OUTPUT       0
1473 #define  STM_TIM1_CCMR_CCS_INPUT_TI1    1
1474 #define  STM_TIM1_CCMR_CCS_INPUT_TI2    2
1475 #define  STM_TIM1_CCMR_CCS_INPUT_TRC    3
1476
1477 #define STM_TIM1_CCMR1_IC2F     12
1478 #define STM_TIM1_CCMR1_IC2PSC   10
1479 #define STM_TIM1_CCMR1_CC2S     8
1480 #define STM_TIM1_CCMR1_IC1F     4
1481 #define  STM_TIM1_CCMR1_IC1F_NONE       0
1482 #define  STM_TIM1_CCMR1_IC1F_DIV_1_N_2  1
1483 #define  STM_TIM1_CCMR1_IC1F_DIV_1_N_4  2
1484 #define  STM_TIM1_CCMR1_IC1F_DIV_1_N_8  3
1485 #define  STM_TIM1_CCMR1_IC1F_DIV_2_N_6  4
1486 #define  STM_TIM1_CCMR1_IC1F_DIV_2_N_8  5
1487 #define  STM_TIM1_CCMR1_IC1F_DIV_4_N_6  6
1488 #define  STM_TIM1_CCMR1_IC1F_DIV_4_N_8  7
1489 #define  STM_TIM1_CCMR1_IC1F_DIV_8_N_6  8
1490 #define  STM_TIM1_CCMR1_IC1F_DIV_8_N_8  9
1491 #define  STM_TIM1_CCMR1_IC1F_DIV_16_N_5 10
1492 #define  STM_TIM1_CCMR1_IC1F_DIV_16_N_6 11
1493 #define  STM_TIM1_CCMR1_IC1F_DIV_16_N_8 12
1494 #define  STM_TIM1_CCMR1_IC1F_DIV_32_N_5 13
1495 #define  STM_TIM1_CCMR1_IC1F_DIV_32_N_6 14
1496 #define  STM_TIM1_CCMR1_IC1F_DIV_32_N_8 15
1497
1498 #define STM_TIM1_CCMR1_IC1PSC   2
1499 #define  STM_TIM1_CCMR1_IC1PSC_NONE     0
1500 #define  STM_TIM1_CCMR1_IC1PSC_2        1
1501 #define  STM_TIM1_CCMR1_IC1PSC_4        2
1502 #define  STM_TIM1_CCMR1_IC1PSC_8        3
1503
1504 #define STM_TIM1_CCMR1_CC1S     0
1505 #define  STM_TIM1_CCMR1_CC1S_OUTPUT     0
1506 #define  STM_TIM1_CCMR1_CC1S_TI1        1
1507 #define  STM_TIM1_CCMR1_CC1S_TI2        2
1508 #define  STM_TIM1_CCMR1_CC1S_TRC        3
1509
1510 #define STM_TIM1_CCMR2_OC4CE    15
1511 #define STM_TIM1_CCMR2_OC4M     12
1512 #define STM_TIM1_CCMR2_OC4PE    11
1513 #define STM_TIM1_CCMR2_OC4FE    10
1514 #define STM_TIM1_CCMR2_CC4S     8
1515 #define  STM_TIM1_CCMR2_CCS_OUTPUT      0
1516 #define  STM_TIM1_CCMR2_CCS_INPUT_TI3   1
1517 #define  STM_TIM1_CCMR2_CCS_INPUT_TI4   2
1518 #define  STM_TIM1_CCMR2_CCS_INPUT_TRC   3
1519 #define STM_TIM1_CCMR2_OC3CE    7
1520 #define STM_TIM1_CCMR2_OC3M     4
1521 #define STM_TIM1_CCMR2_OC3PE    3
1522 #define STM_TIM1_CCMR2_OC3FE    2
1523 #define STM_TIM1_CCMR2_CC3S     0
1524
1525 #define STM_TIM1_CCMR2_IC4F     12
1526 #define STM_TIM1_CCMR2_IC2PSC   10
1527 #define STM_TIM1_CCMR2_CC4S     8
1528 #define STM_TIM1_CCMR2_IC3F     4
1529 #define  STM_TIM1_CCMR2_IC1F_NONE       0
1530 #define  STM_TIM1_CCMR2_IC1F_DIV_1_N_2  1
1531 #define  STM_TIM1_CCMR2_IC1F_DIV_1_N_4  2
1532 #define  STM_TIM1_CCMR2_IC1F_DIV_1_N_8  3
1533 #define  STM_TIM1_CCMR2_IC1F_DIV_2_N_6  4
1534 #define  STM_TIM1_CCMR2_IC1F_DIV_2_N_8  5
1535 #define  STM_TIM1_CCMR2_IC1F_DIV_4_N_6  6
1536 #define  STM_TIM1_CCMR2_IC1F_DIV_4_N_8  7
1537 #define  STM_TIM1_CCMR2_IC1F_DIV_8_N_6  8
1538 #define  STM_TIM1_CCMR2_IC1F_DIV_8_N_8  9
1539 #define  STM_TIM1_CCMR2_IC1F_DIV_16_N_5 10
1540 #define  STM_TIM1_CCMR2_IC1F_DIV_16_N_6 11
1541 #define  STM_TIM1_CCMR2_IC1F_DIV_16_N_8 12
1542 #define  STM_TIM1_CCMR2_IC1F_DIV_32_N_5 13
1543 #define  STM_TIM1_CCMR2_IC1F_DIV_32_N_6 14
1544 #define  STM_TIM1_CCMR2_IC1F_DIV_32_N_8 15
1545
1546 #define STM_TIM1_CCER_CC4P      13
1547 #define STM_TIM1_CCER_CC4E      12
1548 #define STM_TIM1_CCER_CC3NP     11
1549 #define STM_TIM1_CCER_CC3NE     10
1550 #define STM_TIM1_CCER_CC3P      9
1551 #define STM_TIM1_CCER_CC3E      8
1552 #define STM_TIM1_CCER_CC2NP     7
1553 #define STM_TIM1_CCER_CC2NE     6
1554 #define STM_TIM1_CCER_CC2P      5
1555 #define STM_TIM1_CCER_CC2E      4
1556 #define STM_TIM1_CCER_CC1BP     3
1557 #define STM_TIM1_CCER_CC1NE     2
1558 #define STM_TIM1_CCER_CC1P      1
1559 #define STM_TIM1_CCER_CC1E      0
1560
1561 #define STM_TIM1_BDTR_MOE       15
1562 #define STM_TIM1_BDTR_AOE       14
1563 #define STM_TIM1_BDTR_BKP       13
1564 #define STM_TIM1_BDTR_BKE       12
1565 #define STM_TIM1_BDTR_OSSR      11
1566 #define STM_TIM1_BDTR_OSSI      10
1567 #define STM_TIM1_BDTR_LOCK      8
1568 #define  STM_TIM1_BDTR_LOCK_OFF         0
1569 #define  STM_TIM1_BDTR_LOCK_LEVEL_1     1
1570 #define  STM_TIM1_BDTR_LOCK_LEVEL_2     2
1571 #define  STM_TIM1_BDTR_LOCK_LEVEL_3     3
1572
1573 #define STM_TIM1_BDTR_DTG       0
1574
1575 #define STM_TIM1_DCR_DBL        8
1576 #define STM_TIM1_DCR_DBA        0
1577
1578 extern struct stm_tim1 stm_tim1;
1579
1580 #define stm_tim1        (*(struct stm_tim1 *)0x40012c00)
1581
1582 struct stm_tim23 {
1583         vuint32_t       cr1;
1584         vuint32_t       cr2;
1585         vuint32_t       smcr;
1586         vuint32_t       dier;
1587
1588         vuint32_t       sr;
1589         vuint32_t       egr;
1590         vuint32_t       ccmr1;
1591         vuint32_t       ccmr2;
1592
1593         vuint32_t       ccer;
1594         vuint32_t       cnt;
1595         vuint32_t       psc;
1596         vuint32_t       arr;
1597
1598         uint32_t        reserved_30;
1599         vuint32_t       ccr1;
1600         vuint32_t       ccr2;
1601         vuint32_t       ccr3;
1602
1603         vuint32_t       ccr4;
1604         uint32_t        reserved_44;
1605         vuint32_t       dcr;
1606         vuint32_t       dmar;
1607 };
1608
1609 extern struct stm_tim23 stm_tim2, stm_tim3;
1610
1611 #define stm_tim3        (*(struct stm_tim23 *) 0x40000400)
1612 #define stm_tim2        (*(struct stm_tim23 *) 0x40000000)
1613
1614 #define STM_TIM23_CR1_CKD       8
1615 #define  STM_TIM23_CR1_CKD_1            0
1616 #define  STM_TIM23_CR1_CKD_2            1
1617 #define  STM_TIM23_CR1_CKD_4            2
1618 #define  STM_TIM23_CR1_CKD_MASK 3
1619 #define STM_TIM23_CR1_ARPE      7
1620 #define STM_TIM23_CR1_CMS       5
1621 #define  STM_TIM23_CR1_CMS_EDGE         0
1622 #define  STM_TIM23_CR1_CMS_CENTER_1     1
1623 #define  STM_TIM23_CR1_CMS_CENTER_2     2
1624 #define  STM_TIM23_CR1_CMS_CENTER_3     3
1625 #define  STM_TIM23_CR1_CMS_MASK         3
1626 #define STM_TIM23_CR1_DIR       4
1627 #define  STM_TIM23_CR1_DIR_UP           0
1628 #define  STM_TIM23_CR1_DIR_DOWN         1
1629 #define STM_TIM23_CR1_OPM       3
1630 #define STM_TIM23_CR1_URS       2
1631 #define STM_TIM23_CR1_UDIS      1
1632 #define STM_TIM23_CR1_CEN       0
1633
1634 #define STM_TIM23_CR2_TI1S      7
1635 #define STM_TIM23_CR2_MMS       4
1636 #define  STM_TIM23_CR2_MMS_RESET                0
1637 #define  STM_TIM23_CR2_MMS_ENABLE               1
1638 #define  STM_TIM23_CR2_MMS_UPDATE               2
1639 #define  STM_TIM23_CR2_MMS_COMPARE_PULSE        3
1640 #define  STM_TIM23_CR2_MMS_COMPARE_OC1REF       4
1641 #define  STM_TIM23_CR2_MMS_COMPARE_OC2REF       5
1642 #define  STM_TIM23_CR2_MMS_COMPARE_OC3REF       6
1643 #define  STM_TIM23_CR2_MMS_COMPARE_OC4REF       7
1644 #define  STM_TIM23_CR2_MMS_MASK                 7
1645 #define STM_TIM23_CR2_CCDS      3
1646
1647 #define STM_TIM23_SMCR_ETP      15
1648 #define STM_TIM23_SMCR_ECE      14
1649 #define STM_TIM23_SMCR_ETPS     12
1650 #define  STM_TIM23_SMCR_ETPS_OFF                0
1651 #define  STM_TIM23_SMCR_ETPS_DIV_2              1
1652 #define  STM_TIM23_SMCR_ETPS_DIV_4              2
1653 #define  STM_TIM23_SMCR_ETPS_DIV_8              3
1654 #define  STM_TIM23_SMCR_ETPS_MASK               3
1655 #define STM_TIM23_SMCR_ETF      8
1656 #define  STM_TIM23_SMCR_ETF_NONE                0
1657 #define  STM_TIM23_SMCR_ETF_INT_N_2             1
1658 #define  STM_TIM23_SMCR_ETF_INT_N_4             2
1659 #define  STM_TIM23_SMCR_ETF_INT_N_8             3
1660 #define  STM_TIM23_SMCR_ETF_DTS_2_N_6           4
1661 #define  STM_TIM23_SMCR_ETF_DTS_2_N_8           5
1662 #define  STM_TIM23_SMCR_ETF_DTS_4_N_6           6
1663 #define  STM_TIM23_SMCR_ETF_DTS_4_N_8           7
1664 #define  STM_TIM23_SMCR_ETF_DTS_8_N_6           8
1665 #define  STM_TIM23_SMCR_ETF_DTS_8_N_8           9
1666 #define  STM_TIM23_SMCR_ETF_DTS_16_N_5          10
1667 #define  STM_TIM23_SMCR_ETF_DTS_16_N_6          11
1668 #define  STM_TIM23_SMCR_ETF_DTS_16_N_8          12
1669 #define  STM_TIM23_SMCR_ETF_DTS_32_N_5          13
1670 #define  STM_TIM23_SMCR_ETF_DTS_32_N_6          14
1671 #define  STM_TIM23_SMCR_ETF_DTS_32_N_8          15
1672 #define  STM_TIM23_SMCR_ETF_MASK                15
1673 #define STM_TIM23_SMCR_MSM      7
1674 #define STM_TIM23_SMCR_TS       4
1675 #define  STM_TIM23_SMCR_TS_ITR0                 0
1676 #define  STM_TIM23_SMCR_TS_ITR1                 1
1677 #define  STM_TIM23_SMCR_TS_ITR2                 2
1678 #define  STM_TIM23_SMCR_TS_ITR3                 3
1679 #define  STM_TIM23_SMCR_TS_TI1F_ED              4
1680 #define  STM_TIM23_SMCR_TS_TI1FP1               5
1681 #define  STM_TIM23_SMCR_TS_TI2FP2               6
1682 #define  STM_TIM23_SMCR_TS_ETRF                 7
1683 #define  STM_TIM23_SMCR_TS_MASK                 7
1684 #define STM_TIM23_SMCR_OCCS     3
1685 #define STM_TIM23_SMCR_SMS      0
1686 #define  STM_TIM23_SMCR_SMS_DISABLE             0
1687 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_1      1
1688 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_2      2
1689 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_3      3
1690 #define  STM_TIM23_SMCR_SMS_RESET_MODE          4
1691 #define  STM_TIM23_SMCR_SMS_GATED_MODE          5
1692 #define  STM_TIM23_SMCR_SMS_TRIGGER_MODE        6
1693 #define  STM_TIM23_SMCR_SMS_EXTERNAL_CLOCK      7
1694 #define  STM_TIM23_SMCR_SMS_MASK                7
1695
1696 #define STM_TIM23_SR_CC4OF      12
1697 #define STM_TIM23_SR_CC3OF      11
1698 #define STM_TIM23_SR_CC2OF      10
1699 #define STM_TIM23_SR_CC1OF      9
1700 #define STM_TIM23_SR_TIF        6
1701 #define STM_TIM23_SR_CC4IF      4
1702 #define STM_TIM23_SR_CC3IF      3
1703 #define STM_TIM23_SR_CC2IF      2
1704 #define STM_TIM23_SR_CC1IF      1
1705 #define STM_TIM23_SR_UIF        0
1706
1707 #define STM_TIM23_EGR_TG        6
1708 #define STM_TIM23_EGR_CC4G      4
1709 #define STM_TIM23_EGR_CC3G      3
1710 #define STM_TIM23_EGR_CC2G      2
1711 #define STM_TIM23_EGR_CC1G      1
1712 #define STM_TIM23_EGR_UG        0
1713
1714 #define STM_TIM23_CCMR1_OC2CE   15
1715 #define STM_TIM23_CCMR1_OC2M    12
1716 #define  STM_TIM23_CCMR1_OC2M_FROZEN                    0
1717 #define  STM_TIM23_CCMR1_OC2M_SET_HIGH_ON_MATCH         1
1718 #define  STM_TIM23_CCMR1_OC2M_SET_LOW_ON_MATCH          2
1719 #define  STM_TIM23_CCMR1_OC2M_TOGGLE                    3
1720 #define  STM_TIM23_CCMR1_OC2M_FORCE_LOW                 4
1721 #define  STM_TIM23_CCMR1_OC2M_FORCE_HIGH                5
1722 #define  STM_TIM23_CCMR1_OC2M_PWM_MODE_1                6
1723 #define  STM_TIM23_CCMR1_OC2M_PWM_MODE_2                7
1724 #define  STM_TIM23_CCMR1_OC2M_MASK                      7
1725 #define STM_TIM23_CCMR1_OC2PE   11
1726 #define STM_TIM23_CCMR1_OC2FE   10
1727 #define STM_TIM23_CCMR1_CC2S    8
1728 #define  STM_TIM23_CCMR1_CC2S_OUTPUT                    0
1729 #define  STM_TIM23_CCMR1_CC2S_INPUT_TI2                 1
1730 #define  STM_TIM23_CCMR1_CC2S_INPUT_TI1                 2
1731 #define  STM_TIM23_CCMR1_CC2S_INPUT_TRC                 3
1732 #define  STM_TIM23_CCMR1_CC2S_MASK                      3
1733
1734 #define STM_TIM23_CCMR1_OC1CE   7
1735 #define STM_TIM23_CCMR1_OC1M    4
1736 #define  STM_TIM23_CCMR1_OC1M_FROZEN                    0
1737 #define  STM_TIM23_CCMR1_OC1M_SET_HIGH_ON_MATCH         1
1738 #define  STM_TIM23_CCMR1_OC1M_SET_LOW_ON_MATCH          2
1739 #define  STM_TIM23_CCMR1_OC1M_TOGGLE                    3
1740 #define  STM_TIM23_CCMR1_OC1M_FORCE_LOW                 4
1741 #define  STM_TIM23_CCMR1_OC1M_FORCE_HIGH                5
1742 #define  STM_TIM23_CCMR1_OC1M_PWM_MODE_1                6
1743 #define  STM_TIM23_CCMR1_OC1M_PWM_MODE_2                7
1744 #define  STM_TIM23_CCMR1_OC1M_MASK                      7
1745 #define STM_TIM23_CCMR1_OC1PE   11
1746 #define STM_TIM23_CCMR1_OC1FE   2
1747 #define STM_TIM23_CCMR1_CC1S    0
1748 #define  STM_TIM23_CCMR1_CC1S_OUTPUT                    0
1749 #define  STM_TIM23_CCMR1_CC1S_INPUT_TI1                 1
1750 #define  STM_TIM23_CCMR1_CC1S_INPUT_TI2                 2
1751 #define  STM_TIM23_CCMR1_CC1S_INPUT_TRC                 3
1752 #define  STM_TIM23_CCMR1_CC1S_MASK                      3
1753
1754 #define STM_TIM23_CCMR2_OC4CE   15
1755 #define STM_TIM23_CCMR2_OC4M    12
1756 #define  STM_TIM23_CCMR2_OC4M_FROZEN                    0
1757 #define  STM_TIM23_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1758 #define  STM_TIM23_CCMR2_OC4M_SET_LOW_ON_MATCH          2
1759 #define  STM_TIM23_CCMR2_OC4M_TOGGLE                    3
1760 #define  STM_TIM23_CCMR2_OC4M_FORCE_LOW                 4
1761 #define  STM_TIM23_CCMR2_OC4M_FORCE_HIGH                5
1762 #define  STM_TIM23_CCMR2_OC4M_PWM_MODE_1                6
1763 #define  STM_TIM23_CCMR2_OC4M_PWM_MODE_2                7
1764 #define  STM_TIM23_CCMR2_OC4M_MASK                      7
1765 #define STM_TIM23_CCMR2_OC4PE   11
1766 #define STM_TIM23_CCMR2_OC4FE   10
1767 #define STM_TIM23_CCMR2_CC4S    8
1768 #define  STM_TIM23_CCMR2_CC4S_OUTPUT                    0
1769 #define  STM_TIM23_CCMR2_CC4S_INPUT_TI4                 1
1770 #define  STM_TIM23_CCMR2_CC4S_INPUT_TI3                 2
1771 #define  STM_TIM23_CCMR2_CC4S_INPUT_TRC                 3
1772 #define  STM_TIM23_CCMR2_CC4S_MASK                      3
1773
1774 #define STM_TIM23_CCMR2_OC3CE   7
1775 #define STM_TIM23_CCMR2_OC3M    4
1776 #define  STM_TIM23_CCMR2_OC3M_FROZEN                    0
1777 #define  STM_TIM23_CCMR2_OC3M_SET_HIGH_ON_MATCH         1
1778 #define  STM_TIM23_CCMR2_OC3M_SET_LOW_ON_MATCH          2
1779 #define  STM_TIM23_CCMR2_OC3M_TOGGLE                    3
1780 #define  STM_TIM23_CCMR2_OC3M_FORCE_LOW                 4
1781 #define  STM_TIM23_CCMR2_OC3M_FORCE_HIGH                5
1782 #define  STM_TIM23_CCMR2_OC3M_PWM_MODE_1                6
1783 #define  STM_TIM23_CCMR2_OC3M_PWM_MODE_2                7
1784 #define  STM_TIM23_CCMR2_OC3M_MASK                      7
1785 #define STM_TIM23_CCMR2_OC3PE   11
1786 #define STM_TIM23_CCMR2_OC3FE   2
1787 #define STM_TIM23_CCMR2_CC3S    0
1788 #define  STM_TIM23_CCMR2_CC3S_OUTPUT                    0
1789 #define  STM_TIM23_CCMR2_CC3S_INPUT_TI3                 1
1790 #define  STM_TIM23_CCMR2_CC3S_INPUT_TI4                 2
1791 #define  STM_TIM23_CCMR2_CC3S_INPUT_TRC                 3
1792 #define  STM_TIM23_CCMR2_CC3S_MASK                      3
1793
1794 #define STM_TIM23_CCER_CC4NP    15
1795 #define STM_TIM23_CCER_CC4P     13
1796 #define STM_TIM23_CCER_CC4E     12
1797 #define STM_TIM23_CCER_CC3NP    11
1798 #define STM_TIM23_CCER_CC3P     9
1799 #define STM_TIM23_CCER_CC3E     8
1800 #define STM_TIM23_CCER_CC2NP    7
1801 #define STM_TIM23_CCER_CC2P     5
1802 #define STM_TIM23_CCER_CC2E     4
1803 #define STM_TIM23_CCER_CC1NP    3
1804 #define STM_TIM23_CCER_CC1P     1
1805 #define STM_TIM23_CCER_CC1E     0
1806
1807 struct stm_usb {
1808         struct {
1809                 vuint16_t       r;
1810                 uint16_t        _;
1811         } epr[8];
1812         uint8_t         reserved_20[0x40 - 0x20];
1813         vuint16_t       cntr;
1814         uint16_t        reserved_42;
1815         vuint16_t       istr;
1816         uint16_t        reserved_46;
1817         vuint16_t       fnr;
1818         uint16_t        reserved_4a;
1819         vuint16_t       daddr;
1820         uint16_t        reserved_4e;
1821         vuint16_t       btable;
1822         uint16_t        reserved_52;
1823         vuint16_t       lpmcsr;
1824         uint16_t        reserved_56;
1825         vuint16_t       bcdr;
1826         uint16_t        reserved_5a;
1827 };
1828
1829 extern struct stm_usb stm_usb;
1830
1831 #define STM_USB_EPR_CTR_RX      15
1832 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1833 #define STM_USB_EPR_DTOG_RX     14
1834 #define STM_USB_EPR_SW_BUF_TX   14
1835 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1836 #define STM_USB_EPR_STAT_RX     12
1837 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1838 #define  STM_USB_EPR_STAT_RX_STALL                      1
1839 #define  STM_USB_EPR_STAT_RX_NAK                        2
1840 #define  STM_USB_EPR_STAT_RX_VALID                      3
1841 #define  STM_USB_EPR_STAT_RX_MASK                       3
1842 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1843 #define STM_USB_EPR_SETUP       11
1844 #define STM_USB_EPR_EP_TYPE     9
1845 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1846 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1847 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1848 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1849 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1850 #define STM_USB_EPR_EP_KIND     8
1851 #define  STM_USB_EPR_EP_KIND_SNGL_BUF                   0       /* Bulk */
1852 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1853 #define  STM_USB_EPR_EP_KIND_NO_STATUS_OUT              0       /* Control */
1854 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1855 #define STM_USB_EPR_CTR_TX      7
1856 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1857 #define STM_USB_EPR_DTOG_TX     6
1858 #define STM_USB_EPR_SW_BUF_RX   6
1859 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1860 #define STM_USB_EPR_STAT_TX     4
1861 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1862 #define  STM_USB_EPR_STAT_TX_STALL                      1
1863 #define  STM_USB_EPR_STAT_TX_NAK                        2
1864 #define  STM_USB_EPR_STAT_TX_VALID                      3
1865 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1866 #define  STM_USB_EPR_STAT_TX_MASK                       3
1867 #define STM_USB_EPR_EA          0
1868 #define  STM_USB_EPR_EA_MASK                            0xf
1869
1870 #define STM_USB_CNTR_CTRM       15
1871 #define STM_USB_CNTR_PMAOVRM    14
1872 #define STM_USB_CNTR_ERRM       13
1873 #define STM_USB_CNTR_WKUPM      12
1874 #define STM_USB_CNTR_SUSPM      11
1875 #define STM_USB_CNTR_RESETM     10
1876 #define STM_USB_CNTR_SOFM       9
1877 #define STM_USB_CNTR_ESOFM      8
1878 #define STM_USB_CNTR_RESUME     4
1879 #define STM_USB_CNTR_FSUSP      3
1880 #define STM_USB_CNTR_LP_MODE    2
1881 #define STM_USB_CNTR_PDWN       1
1882 #define STM_USB_CNTR_FRES       0
1883
1884 #define STM_USB_ISTR_CTR        15
1885 #define STM_USB_ISTR_PMAOVR     14
1886 #define STM_USB_ISTR_ERR        13
1887 #define STM_USB_ISTR_WKUP       12
1888 #define STM_USB_ISTR_SUSP       11
1889 #define STM_USB_ISTR_RESET      10
1890 #define STM_USB_ISTR_SOF        9
1891 #define STM_USB_ISTR_ESOF       8
1892 #define STM_USB_L1REQ           7
1893 #define STM_USB_ISTR_DIR        4
1894 #define STM_USB_ISTR_EP_ID      0
1895 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1896
1897 #define STM_USB_FNR_RXDP        15
1898 #define STM_USB_FNR_RXDM        14
1899 #define STM_USB_FNR_LCK         13
1900 #define STM_USB_FNR_LSOF        11
1901 #define  STM_USB_FNR_LSOF_MASK                  0x3
1902 #define STM_USB_FNR_FN          0
1903 #define  STM_USB_FNR_FN_MASK                    0x7ff
1904
1905 #define STM_USB_DADDR_EF        7
1906 #define STM_USB_DADDR_ADD       0
1907 #define  STM_USB_DADDR_ADD_MASK                 0x7f
1908
1909 #define STM_USB_BCDR_DPPU       15
1910 #define STM_USB_BCDR_PS2DET     7
1911 #define STM_USB_BCDR_SDET       6
1912 #define STM_USB_BCDR_PDET       5
1913 #define STM_USB_BCDR_DCDET      4
1914 #define STM_USB_BCDR_SDEN       3
1915 #define STM_USB_BCDR_PDEN       2
1916 #define STM_USB_BCDR_DCDEN      1
1917 #define STM_USB_BCDR_BCDEN      0
1918
1919 union stm_usb_bdt {
1920         struct {
1921                 vuint16_t       addr_tx;
1922                 vuint16_t       count_tx;
1923                 vuint16_t       addr_rx;
1924                 vuint16_t       count_rx;
1925         } single;
1926         struct {
1927                 vuint16_t       addr;
1928                 vuint16_t       count;
1929         } double_tx[2];
1930         struct {
1931                 vuint16_t       addr;
1932                 vuint16_t       count;
1933         } double_rx[2];
1934 };
1935
1936 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
1937 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
1938 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
1939 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
1940 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
1941
1942 #define STM_USB_BDT_SIZE        8
1943
1944 /* We'll use the first block of usb SRAM for the BDT */
1945 extern uint8_t stm_usb_sram[] __attribute__((aligned(4)));
1946 extern union stm_usb_bdt stm_usb_bdt[STM_USB_BDT_SIZE] __attribute__((aligned(4)));
1947
1948 #define stm_usb_sram    ((uint8_t *) 0x40006000)
1949 #define stm_usb_bdt     ((union stm_usb_bdt *) 0x40006000)
1950
1951 struct stm_exti {
1952         vuint32_t       imr;
1953         vuint32_t       emr;
1954         vuint32_t       rtsr;
1955         vuint32_t       ftsr;
1956
1957         vuint32_t       swier;
1958         vuint32_t       pr;
1959 };
1960
1961 extern struct stm_exti stm_exti;
1962
1963 struct stm_usart {
1964         vuint32_t       cr1;    /* control register 1 */
1965         vuint32_t       cr2;    /* control register 2 */
1966         vuint32_t       cr3;    /* control register 3 */
1967         vuint32_t       brr;    /* baud rate register */
1968
1969         vuint32_t       gtpr;   /* guard time and prescaler */
1970         vuint32_t       rtor;   /* receiver timeout register */
1971         vuint32_t       rqr;    /* request register */
1972         vuint32_t       isr;    /* interrupt and status register */
1973
1974         vuint32_t       icr;    /* interrupt flag clear register */
1975         vuint32_t       rdr;    /* receive data register */
1976         vuint32_t       tdr;    /* transmit data register */
1977 };
1978
1979 #define STM_USART_CR1_M1        28
1980 #define STM_USART_CR1_EOBIE     27
1981 #define STM_USART_CR1_RTOIE     26
1982 #define STM_USART_CR1_DEAT      21
1983 #define STM_USART_CR1_DEDT      16
1984 #define STM_USART_CR1_OVER8     15
1985 #define STM_USART_CR1_CMIE      14
1986 #define STM_USART_CR1_MME       13
1987 #define STM_USART_CR1_M0        12
1988 #define STM_USART_CR1_WAKE      11
1989 #define STM_USART_CR1_PCE       10
1990 #define STM_USART_CR1_PS        9
1991 #define STM_USART_CR1_PEIE      8
1992 #define STM_USART_CR1_TXEIE     7
1993 #define STM_USART_CR1_TCIE      6
1994 #define STM_USART_CR1_RXNEIE    5
1995 #define STM_USART_CR1_IDLEIE    4
1996 #define STM_USART_CR1_TE        3
1997 #define STM_USART_CR1_RE        2
1998 #define STM_USART_CR1_UESM      1
1999 #define STM_USART_CR1_UE        0
2000
2001 #define STM_USART_CR2_ADD       24
2002 #define STM_USART_CR2_RTOEN     23
2003 #define STM_USART_CR2_ABRMOD    21
2004 #define STM_USART_CR2_ABREN     20
2005 #define STM_USART_CR2_MSBFIRST  19
2006 #define STM_USART_CR2_DATAINV   18
2007 #define STM_USART_CR2_TXINV     17
2008 #define STM_USART_CR2_RXINV     16
2009 #define STM_USART_CR2_SWAP      15
2010 #define STM_USART_CR2_LINEN     14
2011 #define STM_USART_CR2_STOP      12
2012 #define STM_USART_CR2_CLKEN     11
2013 #define STM_USART_CR2_CPOL      10
2014 #define STM_USART_CR2_CHPA      9
2015 #define STM_USART_CR2_LBCL      8
2016 #define STM_USART_CR2_LBDIE     6
2017 #define STM_USART_CR2_LBDL      5
2018 #define STM_USART_CR2_ADDM7     4
2019
2020 #define STM_USART_CR3_WUFIE     22
2021 #define STM_USART_CR3_WUS       20
2022 #define STM_USART_CR3_SCARCNT   17
2023 #define STM_USART_CR3_DEP       15
2024 #define STM_USART_CR3_DEM       14
2025 #define STM_USART_CR3_DDRE      13
2026 #define STM_USART_CR3_OVRDIS    12
2027 #define STM_USART_CR3_ONEBIT    11
2028 #define STM_USART_CR3_CTIIE     10
2029 #define STM_USART_CR3_CTSE      9
2030 #define STM_USART_CR3_RTSE      8
2031 #define STM_USART_CR3_DMAT      7
2032 #define STM_USART_CR3_DMAR      6
2033 #define STM_USART_CR3_SCEN      5
2034 #define STM_USART_CR3_NACK      4
2035 #define STM_USART_CR3_HDSEL     3
2036 #define STM_USART_CR3_IRLP      2
2037 #define STM_USART_CR3_IREN      1
2038 #define STM_USART_CR3_EIE       0
2039
2040 #define STM_USART_GTPR_GT       8
2041 #define STM_USART_GTPR_PSC      0
2042
2043 #define STM_USART_RQR_TXFRQ     4
2044 #define STM_USART_RQR_RXFRQ     3
2045 #define STM_USART_RQR_MMRQ      2
2046 #define STM_USART_RQR_SBKRQ     1
2047 #define STM_USART_RQR_ABRRQ     0
2048
2049 #define STM_USART_ISR_REACK     22
2050 #define STM_USART_ISR_TEACK     21
2051 #define STM_USART_ISR_WUF       20
2052 #define STM_USART_ISR_RWU       19
2053 #define STM_USART_ISR_SBKF      18
2054 #define STM_USART_ISR_CMF       17
2055 #define STM_USART_ISR_BUSY      16
2056 #define STM_USART_ISR_ABRF      15
2057 #define STM_USART_ISR_ABRE      14
2058 #define STM_USART_ISR_EOBF      12
2059 #define STM_USART_ISR_RTOF      11
2060 #define STM_USART_ISR_CTS       10
2061 #define STM_USART_ISR_CTSIF     9
2062 #define STM_USART_ISR_LBDF      8
2063 #define STM_USART_ISR_TXE       7
2064 #define STM_USART_ISR_TC        6
2065 #define STM_USART_ISR_RXNE      5
2066 #define STM_USART_ISR_IDLE      4
2067 #define STM_USART_ISR_ORE       3
2068 #define STM_USART_ISR_NF        2
2069 #define STM_USART_ISR_FE        1
2070 #define STM_USART_ISR_PE        0
2071
2072 #define STM_USART_ICR_WUCF      20
2073 #define STM_USART_ICR_CMCF      17
2074 #define STM_USART_ICR_EOBCF     12
2075 #define STM_USART_ICR_RTOCF     11
2076 #define STM_USART_ICR_CTSCF     9
2077 #define STM_USART_ICR_LBDCF     8
2078 #define STM_USART_ICR_TCCF      6
2079 #define STM_USART_ICR_IDLECF    4
2080 #define STM_USART_ICR_ORECF     3
2081 #define STM_USART_ICR_NCF       2
2082 #define STM_USART_ICR_FECF      1
2083 #define STM_USART_ICR_PECF      0
2084
2085 extern struct stm_usart stm_usart1;
2086 extern struct stm_usart stm_usart2;
2087
2088 #define isr_decl(name) \
2089         void stm_ ## name ## _isr(void)
2090
2091 isr_decl(halt);
2092 isr_decl(ignore);
2093 isr_decl(nmi);
2094 isr_decl(hardfault);
2095 isr_decl(memmanage);
2096 isr_decl(busfault);
2097 isr_decl(usagefault);
2098 isr_decl(svc);
2099 isr_decl(debugmon);
2100 isr_decl(pendsv);
2101 isr_decl(systick);
2102 isr_decl(wwdg);
2103 isr_decl(pvd);
2104 isr_decl(rtc);
2105 isr_decl(flash);
2106 isr_decl(rcc_crs);
2107 isr_decl(exti0_1);
2108 isr_decl(exti2_3);
2109 isr_decl(exti4_15);
2110 isr_decl(tsc);
2111 isr_decl(dma_ch1);
2112 isr_decl(dma_ch2_3);
2113 isr_decl(dma_ch4_5_6);
2114 isr_decl(adc_comp);
2115 isr_decl(tim1_brk_up_trg_com);
2116 isr_decl(tim1_cc);
2117 isr_decl(tim2);
2118 isr_decl(tim3);
2119 isr_decl(tim6_dac);
2120 isr_decl(tim7);
2121 isr_decl(tim14);
2122 isr_decl(tim15);
2123 isr_decl(tim16);
2124 isr_decl(tim17);
2125 isr_decl(i2c1);
2126 isr_decl(i2c2);
2127 isr_decl(spi1);
2128 isr_decl(spi2);
2129 isr_decl(usart1);
2130 isr_decl(usart2);
2131 isr_decl(usart3_4_5_6_7_8);
2132 isr_decl(cec_can);
2133 isr_decl(usb);
2134
2135 #endif /* _STM32F0_H_ */