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   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #ifndef _STM32F0_H_
  20 #define _STM32F0_H_
  21
  22 #include <stdint.h>
  23
  24 typedef volatile uint32_t       vuint32_t;
  25 typedef volatile void *         vvoid_t;
  26 typedef volatile uint16_t       vuint16_t;
  27 typedef volatile uint8_t        vuint8_t;
  28
  29 struct stm_gpio {
  30         vuint32_t       moder;
  31         vuint32_t       otyper;
  32         vuint32_t       ospeedr;
  33         vuint32_t       pupdr;
  34
  35         vuint32_t       idr;
  36         vuint32_t       odr;
  37         vuint32_t       bsrr;
  38         vuint32_t       lckr;
  39
  40         vuint32_t       afrl;
  41         vuint32_t       afrh;
  42         vuint32_t       brr;
  43 };
  44
  45 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  46 #define STM_MODER_MASK                  3
  47 #define STM_MODER_INPUT                 0
  48 #define STM_MODER_OUTPUT                1
  49 #define STM_MODER_ALTERNATE             2
  50 #define STM_MODER_ANALOG                3
  51
  52 static inline void
  53 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  54         gpio->moder = ((gpio->moder &
  55                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  56                        value << STM_MODER_SHIFT(pin));
  57 }
  58
  59 static inline uint32_t
  60 stm_moder_get(struct stm_gpio *gpio, int pin) {
  61         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  62 }
  63
  64 #define STM_OTYPER_SHIFT(pin)           (pin)
  65 #define STM_OTYPER_MASK                 1
  66 #define STM_OTYPER_PUSH_PULL            0
  67 #define STM_OTYPER_OPEN_DRAIN           1
  68
  69 static inline void
  70 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  71         gpio->otyper = ((gpio->otyper &
  72                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  73                         value << STM_OTYPER_SHIFT(pin));
  74 }
  75
  76 static inline uint32_t
  77 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  78         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  79 }
  80
  81 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  82 #define STM_OSPEEDR_MASK                3
  83 #define STM_OSPEEDR_LOW                 0       /* 2MHz */
  84 #define STM_OSPEEDR_MEDIUM              1       /* 10MHz */
  85 #define STM_OSPEEDR_HIGH                3       /* 10-50MHz */
  86
  87 static inline void
  88 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  89         gpio->ospeedr = ((gpio->ospeedr &
  90                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  91                        value << STM_OSPEEDR_SHIFT(pin));
  92 }
  93
  94 static inline uint32_t
  95 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  96         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  97 }
  98
  99 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
 100 #define STM_PUPDR_MASK                  3
 101 #define STM_PUPDR_NONE                  0
 102 #define STM_PUPDR_PULL_UP               1
 103 #define STM_PUPDR_PULL_DOWN             2
 104 #define STM_PUPDR_RESERVED              3
 105
 106 static inline void
 107 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 108         gpio->pupdr = ((gpio->pupdr &
 109                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 110                        value << STM_PUPDR_SHIFT(pin));
 111 }
 112
 113 static inline uint32_t
 114 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 115         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 116 }
 117
 118 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 119 #define STM_AFR_MASK                    0xf
 120 #define STM_AFR_NONE                    0
 121 #define STM_AFR_AF0                     0x0
 122 #define STM_AFR_AF1                     0x1
 123 #define STM_AFR_AF2                     0x2
 124 #define STM_AFR_AF3                     0x3
 125 #define STM_AFR_AF4                     0x4
 126 #define STM_AFR_AF5                     0x5
 127 #define STM_AFR_AF6                     0x6
 128 #define STM_AFR_AF7                     0x7
 129
 130 static inline void
 131 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 132         /*
 133          * Set alternate pin mode too
 134          */
 135         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 136         if (pin < 8)
 137                 gpio->afrl = ((gpio->afrl &
 138                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 139                               value << STM_AFR_SHIFT(pin));
 140         else {
 141                 pin -= 8;
 142                 gpio->afrh = ((gpio->afrh &
 143                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 144                               value << STM_AFR_SHIFT(pin));
 145         }
 146 }
 147
 148 static inline uint32_t
 149 stm_afr_get(struct stm_gpio *gpio, int pin) {
 150         if (pin < 8)
 151                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 152         else {
 153                 pin -= 8;
 154                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 155         }
 156 }
 157
 158 static inline void
 159 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 160         /* Use the bit set/reset register to do this atomically */
 161         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 162 }
 163
 164 static inline uint8_t
 165 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 166         return (gpio->idr >> pin) & 1;
 167 }
 168
 169 static inline uint16_t
 170 stm_gpio_get_all(struct stm_gpio *gpio) {
 171         return gpio->idr;
 172 }
 173
 174 /*
 175  * We can't define these in registers.ld or our fancy
 176  * ao_enable_gpio macro will expand into a huge pile of code
 177  * as the compiler won't do correct constant folding and
 178  * dead-code elimination
 179  */
 180
 181 extern struct stm_gpio stm_gpioa;
 182 extern struct stm_gpio stm_gpiob;
 183 extern struct stm_gpio stm_gpioc;
 184 extern struct stm_gpio stm_gpiof;
 185
 186 #define stm_gpiof  (*((struct stm_gpio *) 0x48001400))
 187 #define stm_gpioc  (*((struct stm_gpio *) 0x48000800))
 188 #define stm_gpiob  (*((struct stm_gpio *) 0x48000400))
 189 #define stm_gpioa  (*((struct stm_gpio *) 0x48000000))
 190
 191 /* Flash interface */
 192
 193 struct stm_flash {
 194         vuint32_t       acr;
 195         vuint32_t       keyr;
 196         vuint32_t       optkeyr;
 197         vuint32_t       sr;
 198
 199         vuint32_t       cr;
 200         vuint32_t       ar;
 201         vuint32_t       unused_0x18;
 202         vuint32_t       obr;
 203
 204         vuint32_t       wrpr;
 205 };
 206
 207 extern struct stm_flash stm_flash;
 208
 209 #define STM_FLASH_ACR_PRFTBS    (5)
 210 #define STM_FLASH_ACR_PRFTBE    (4)
 211 #define STM_FLASH_ACR_LATENCY   (0)
 212 #define  STM_FLASH_ACR_LATENCY_0                0
 213 #define  STM_FLASH_ACR_LATENCY_1                1
 214
 215 #define STM_FLASH_PECR_OBL_LAUNCH       18
 216 #define STM_FLASH_PECR_ERRIE            17
 217 #define STM_FLASH_PECR_EOPIE            16
 218 #define STM_FLASH_PECR_FPRG             10
 219 #define STM_FLASH_PECR_ERASE            9
 220 #define STM_FLASH_PECR_FTDW             8
 221 #define STM_FLASH_PECR_DATA             4
 222 #define STM_FLASH_PECR_PROG             3
 223 #define STM_FLASH_PECR_OPTLOCK          2
 224 #define STM_FLASH_PECR_PRGLOCK          1
 225 #define STM_FLASH_PECR_PELOCK           0
 226
 227 #define STM_FLASH_SR_EOP                5
 228 #define STM_FLASH_SR_WRPRTERR           4
 229 #define STM_FLASH_SR_PGERR              2
 230 #define STM_FLASH_SR_BSY                0
 231
 232 #define STM_FLASH_CR_OBL_LAUNCH         13
 233 #define STM_FLASH_CR_EOPIE              12
 234 #define STM_FLASH_CR_ERRIE              10
 235 #define STM_FLASH_CR_OPTWRE             9
 236 #define STM_FLASH_CR_LOCK               7
 237 #define STM_FLASH_CR_STRT               6
 238 #define STM_FLASH_CR_OPTER              5
 239 #define STM_FLASH_CR_OPTPG              4
 240 #define STM_FLASH_CR_MER                2
 241 #define STM_FLASH_CR_PER                1
 242 #define STM_FLASH_CR_PG                 0
 243
 244 #define STM_FLASH_OBR_DATA1             24
 245 #define STM_FLASH_OBR_DATA0             16
 246 #define STM_FLASH_OBR_BOOT_SEL          15
 247 #define STM_FLASH_OBR_RAM_PARITY_CHECK  14
 248 #define STM_FLASH_OBR_VDDA_MONITOR      13
 249 #define STM_FLASH_OBR_NBOOT1            12
 250 #define STM_FLASH_OBR_NBOOT0            11
 251 #define STM_FLASH_OBR_NRST_STDBY        10
 252 #define STM_FLASH_OBR_NRST_STOP         9
 253 #define STM_FLASH_OBR_WDG_SW            8
 254 #define STM_FLASH_OBR_RDPRT             1
 255 #define  STM_FLASH_OBR_RDPRT_LEVEL0             0
 256 #define  STM_FLASH_OBR_RDPRT_LEVEL1             1
 257 #define  STM_FLASH_OBR_RDPRT_LEVEL2             3
 258 #define STM_FLASH_OBR_OPTERR            0
 259
 260 #define STM_FLASH_KEYR_KEY1     0x45670123
 261 #define STM_FLASH_KEYR_KEY2     0xcdef89ab
 262
 263 struct stm_rcc {
 264         vuint32_t       cr;
 265         vuint32_t       cfgr;
 266         vuint32_t       cir;
 267         vuint32_t       apb2rstr;
 268
 269         vuint32_t       apb1rstr;
 270         vuint32_t       ahbenr;
 271         vuint32_t       apb2enr;
 272         vuint32_t       apb1enr;
 273
 274         vuint32_t       bdcr;
 275         vuint32_t       csr;
 276         vuint32_t       ahbrstr;
 277         vuint32_t       cfgr2;
 278
 279         vuint32_t       cfgr3;
 280         vuint32_t       cr2;
 281 };
 282
 283 extern struct stm_rcc stm_rcc;
 284
 285 /* Nominal high speed internal oscillator frequency is 16MHz */
 286 #define STM_HSI_FREQ            16000000
 287
 288 #define STM_RCC_CR_PLLRDY       (25)
 289 #define STM_RCC_CR_PLLON        (24)
 290 #define STM_RCC_CR_CSSON        (19)
 291 #define STM_RCC_CR_HSEBYP       (18)
 292 #define STM_RCC_CR_HSERDY       (17)
 293 #define STM_RCC_CR_HSEON        (16)
 294 #define STM_RCC_CR_HSICAL       (8)
 295 #define STM_RCC_CR_HSITRIM      (3)
 296 #define STM_RCC_CR_HSIRDY       (1)
 297 #define STM_RCC_CR_HSION        (0)
 298
 299 #define STM_RCC_CFGR_PLL_NODIV  (31)
 300 #define  STM_RCC_CFGR_PLL_NODIV_DIV_1   1
 301 #define  STM_RCC_CFGR_PLL_NODIV_DIV_2   0
 302
 303 #define STM_RCC_CFGR_MCOPRE     (28)
 304 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 305 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 306 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 307 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 308 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 309 #define  STM_RCC_CFGR_MCOPRE_DIV_32     5
 310 #define  STM_RCC_CFGR_MCOPRE_DIV_64     6
 311 #define  STM_RCC_CFGR_MCOPRE_DIV_128    7
 312 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7
 313
 314 #define STM_RCC_CFGR_MCO        (24)
 315 # define STM_RCC_CFGR_MCO_DISABLE       0
 316
 317 #define STM_RCC_CFGR_PLLMUL     (18)
 318 #define  STM_RCC_CFGR_PLLMUL_2          0
 319 #define  STM_RCC_CFGR_PLLMUL_3          1
 320 #define  STM_RCC_CFGR_PLLMUL_4          2
 321 #define  STM_RCC_CFGR_PLLMUL_5          3
 322 #define  STM_RCC_CFGR_PLLMUL_6          4
 323 #define  STM_RCC_CFGR_PLLMUL_7          5
 324 #define  STM_RCC_CFGR_PLLMUL_8          6
 325 #define  STM_RCC_CFGR_PLLMUL_9          7
 326 #define  STM_RCC_CFGR_PLLMUL_10         8
 327 #define  STM_RCC_CFGR_PLLMUL_11         9
 328 #define  STM_RCC_CFGR_PLLMUL_12         10
 329 #define  STM_RCC_CFGR_PLLMUL_13         11
 330 #define  STM_RCC_CFGR_PLLMUL_14         12
 331 #define  STM_RCC_CFGR_PLLMUL_15         13
 332 #define  STM_RCC_CFGR_PLLMUL_16         14
 333 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 334
 335 #define STM_RCC_CFGR_PLLXTPRE   (17)
 336
 337 #define STM_RCC_CFGR_PLLSRC     (15)
 338 # define STM_RCC_CFGR_PLLSRC_HSI_DIV_2  0
 339 # define STM_RCC_CFGR_PLLSRC_HSI        1
 340 # define STM_RCC_CFGR_PLLSRC_HSE        2
 341 # define STM_RCC_CFGR_PLLSRC_HSI48      3
 342
 343 #define STM_RCC_CFGR_ADCPRE     (14)
 344
 345 #define STM_RCC_CFGR_PPRE       (8)
 346 #define  STM_RCC_CFGR_PPRE_DIV_1        0
 347 #define  STM_RCC_CFGR_PPRE_DIV_2        4
 348 #define  STM_RCC_CFGR_PPRE_DIV_4        5
 349 #define  STM_RCC_CFGR_PPRE_DIV_8        6
 350 #define  STM_RCC_CFGR_PPRE_DIV_16       7
 351 #define  STM_RCC_CFGR_PPRE_MASK         7
 352
 353 #define STM_RCC_CFGR_HPRE       (4)
 354 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 355 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 356 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 357 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 358 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 359 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 360 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 361 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 362 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 363 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 364
 365 #define STM_RCC_CFGR_SWS        (2)
 366 #define  STM_RCC_CFGR_SWS_HSI           0
 367 #define  STM_RCC_CFGR_SWS_HSE           1
 368 #define  STM_RCC_CFGR_SWS_PLL           2
 369 #define  STM_RCC_CFGR_SWS_HSI48         3
 370 #define  STM_RCC_CFGR_SWS_MASK          3
 371
 372 #define STM_RCC_CFGR_SW         (0)
 373 #define  STM_RCC_CFGR_SW_HSI            0
 374 #define  STM_RCC_CFGR_SW_HSE            1
 375 #define  STM_RCC_CFGR_SW_PLL            2
 376 #define  STM_RCC_CFGR_SW_HSI48          3
 377 #define  STM_RCC_CFGR_SW_MASK           3
 378
 379 #define STM_RCC_APB2RSTR_DBGMCURST      22
 380 #define STM_RCC_APB2RSTR_TIM17RST       18
 381 #define STM_RCC_APB2RSTR_TIM16RST       17
 382 #define STM_RCC_APB2RSTR_TIM15RST       16
 383 #define STM_RCC_APB2RSTR_USART1RST      14
 384 #define STM_RCC_APB2RSTR_SPI1RST        12
 385 #define STM_RCC_APB2RSTR_TIM1RST        11
 386 #define STM_RCC_APB2RSTR_ADCRST         9
 387 #define STM_RCC_APB2RSTR_USART8RST      7
 388 #define STM_RCC_APB2RSTR_USART7RST      6
 389 #define STM_RCC_APB2RSTR_USART6RST      5
 390 #define STM_RCC_APB2RSTR_SYSCFGRST      1
 391
 392 #define STM_RCC_APB1RSTR_CECRST         30
 393 #define STM_RCC_APB1RSTR_DACRST         29
 394 #define STM_RCC_APB1RSTR_PWRRST         28
 395 #define STM_RCC_APB1RSTR_CRSRST         27
 396 #define STM_RCC_APB1RSTR_CANRST         25
 397 #define STM_RCC_APB1RSTR_USBRST         23
 398 #define STM_RCC_APB1RSTR_I2C2RST        22
 399 #define STM_RCC_APB1RSTR_I1C1RST        21
 400 #define STM_RCC_APB1RSTR_USART5RST      20
 401 #define STM_RCC_APB1RSTR_USART4RST      19
 402 #define STM_RCC_APB1RSTR_USART3RST      18
 403 #define STM_RCC_APB1RSTR_USART2RST      17
 404 #define STM_RCC_APB1RSTR_SPI2RST        14
 405 #define STM_RCC_APB1RSTR_WWDGRST        11
 406 #define STM_RCC_APB1RSTR_TIM14RST       8
 407 #define STM_RCC_APB1RSTR_TIM7RST        5
 408 #define STM_RCC_APB1RSTR_TIM6RST        4
 409 #define STM_RCC_APB1RSTR_TIM3RST        1
 410 #define STM_RCC_APB1RSTR_TIM2RST        0
 411
 412 #define STM_RCC_AHBENR_TSCEN    24
 413 #define STM_RCC_AHBENR_IOPFEN   22
 414 #define STM_RCC_AHBENR_IOPEEN   21
 415 #define STM_RCC_AHBENR_IOPDEN   20
 416 #define STM_RCC_AHBENR_IOPCEN   19
 417 #define STM_RCC_AHBENR_IOPBEN   18
 418 #define STM_RCC_AHBENR_IOPAEN   17
 419 #define STM_RCC_AHBENR_CRCEN    6
 420 #define STM_RCC_AHBENR_FLITFEN  4
 421 #define STM_RCC_AHBENR_SRAMEN   2
 422 #define STM_RCC_AHBENR_DMA2EN   1
 423 #define STM_RCC_AHBENR_DMAEN    0
 424
 425 #define STM_RCC_APB2ENR_DBGMCUEN        22
 426 #define STM_RCC_APB2ENR_TIM17EN         18
 427 #define STM_RCC_APB2ENR_TIM16EN         17
 428 #define STM_RCC_APB2ENR_TIM15EN         16
 429 #define STM_RCC_APB2ENR_USART1EN        14
 430 #define STM_RCC_APB2ENR_SPI1EN          12
 431 #define STM_RCC_APB2ENR_TIM1EN          11
 432 #define STM_RCC_APB2ENR_ADCEN           9
 433 #define STM_RCC_APB2ENR_USART8EN        7
 434 #define STM_RCC_APB2ENR_USART7EN        6
 435 #define STM_RCC_APB2ENR_USART6EN        5
 436 #define STM_RCC_APB2ENR_SYSCFGCOMPEN    0
 437
 438 #define STM_RCC_APB1ENR_CECEN           30
 439 #define STM_RCC_APB1ENR_DACEN           29
 440 #define STM_RCC_APB1ENR_PWREN           28
 441 #define STM_RCC_APB1ENR_CRSEN           27
 442 #define STM_RCC_APB1ENR_CANEN           25
 443 #define STM_RCC_APB1ENR_USBEN           23
 444 #define STM_RCC_APB1ENR_I2C2EN          22
 445 #define STM_RCC_APB1ENR_IC21EN          21
 446 #define STM_RCC_APB1ENR_USART5EN        20
 447 #define STM_RCC_APB1ENR_USART4EN        19
 448 #define STM_RCC_APB1ENR_USART3EN        18
 449 #define STM_RCC_APB1ENR_USART2EN        17
 450 #define STM_RCC_APB1ENR_SPI2EN          14
 451 #define STM_RCC_APB1ENR_WWDGEN          11
 452 #define STM_RCC_APB1ENR_TIM14EN         8
 453 #define STM_RCC_APB1ENR_TIM7EN          5
 454 #define STM_RCC_APB1ENR_TIM6EN          4
 455 #define STM_RCC_APB1ENR_TIM3EN          1
 456 #define STM_RCC_APB1ENR_TIM2EN          0
 457
 458 #define STM_RCC_CSR_LPWRRSTF            (31)
 459 #define STM_RCC_CSR_WWDGRSTF            (30)
 460 #define STM_RCC_CSR_IWDGRSTF            (29)
 461 #define STM_RCC_CSR_SFTRSTF             (28)
 462 #define STM_RCC_CSR_PORRSTF             (27)
 463 #define STM_RCC_CSR_PINRSTF             (26)
 464 #define STM_RCC_CSR_OBLRSTF             (25)
 465 #define STM_RCC_CSR_RMVF                (24)
 466 #define STM_RCC_CSR_V18PWRRSTF          (23)
 467 #define STM_RCC_CSR_LSIRDY              (1)
 468 #define STM_RCC_CSR_LSION               (0)
 469
 470 #define STM_RCC_CR2_HSI48CAL            24
 471 #define STM_RCC_CR2_HSI48RDY            17
 472 #define STM_RCC_CR2_HSI48ON             16
 473 #define STM_RCC_CR2_HSI14CAL            8
 474 #define STM_RCC_CR2_HSI14TRIM           3
 475 #define STM_RCC_CR2_HSI14DIS            2
 476 #define STM_RCC_CR2_HSI14RDY            1
 477 #define STM_RCC_CR2_HSI14ON             0
 478
 479 #define STM_RCC_CFGR2_PREDIV            0
 480 #define  STM_RCC_CFGR2_PREDIV_1                 0x0
 481 #define  STM_RCC_CFGR2_PREDIV_2                 0x1
 482 #define  STM_RCC_CFGR2_PREDIV_3                 0x2
 483 #define  STM_RCC_CFGR2_PREDIV_4                 0x3
 484 #define  STM_RCC_CFGR2_PREDIV_5                 0x4
 485 #define  STM_RCC_CFGR2_PREDIV_6                 0x5
 486 #define  STM_RCC_CFGR2_PREDIV_7                 0x6
 487 #define  STM_RCC_CFGR2_PREDIV_8                 0x7
 488 #define  STM_RCC_CFGR2_PREDIV_9                 0x8
 489 #define  STM_RCC_CFGR2_PREDIV_10                0x9
 490 #define  STM_RCC_CFGR2_PREDIV_11                0xa
 491 #define  STM_RCC_CFGR2_PREDIV_12                0xb
 492 #define  STM_RCC_CFGR2_PREDIV_13                0xc
 493 #define  STM_RCC_CFGR2_PREDIV_14                0xd
 494 #define  STM_RCC_CFGR2_PREDIV_15                0xe
 495 #define  STM_RCC_CFGR2_PREDIV_16                0xf
 496
 497 #define STM_RCC_CFGR3_USART3SW          18
 498 #define STM_RCC_CFGR3_USART2SW          16
 499 #define STM_RCC_CFGR3_ADCSW             8
 500 #define STM_RCC_CFGR3_USBSW             7
 501 #define STM_RCC_CFGR3_CECSW             6
 502 #define STM_RCC_CFGR3_I2C1SW            4
 503 #define STM_RCC_CFGR3_USART1SW          0
 504
 505 struct stm_crs {
 506         vuint32_t       cr;
 507         vuint32_t       cfgr;
 508         vuint32_t       isr;
 509         vuint32_t       icr;
 510 };
 511
 512 extern struct stm_crs stm_crs;
 513
 514 #define STM_CRS_CR_TRIM         8
 515 #define STM_CRS_CR_SWSYNC       7
 516 #define STM_CRS_CR_AUTOTRIMEN   6
 517 #define STM_CRS_CR_CEN          5
 518 #define STM_CRS_CR_ESYNCIE      3
 519 #define STM_CRS_CR_ERRIE        2
 520 #define STM_CRS_CR_SYNCWARNIE   1
 521 #define STM_CRS_CR_SYNCOKIE     0
 522
 523 #define STM_CRS_CFGR_SYNCPOL    31
 524 #define STM_CRS_CFGR_SYNCSRC    28
 525 #define  STM_CRS_CFGR_SYNCSRC_GPIO      0
 526 #define  STM_CRS_CFGR_SYNCSRC_LSE       1
 527 #define  STM_CRS_CFGR_SYNCSRC_USB       2
 528 #define STM_CRS_CFGR_SYNCDIV    24
 529 #define  STM_CRS_CFGR_SYNCDIV_1         0
 530 #define  STM_CRS_CFGR_SYNCDIV_2         1
 531 #define  STM_CRS_CFGR_SYNCDIV_4         2
 532 #define  STM_CRS_CFGR_SYNCDIV_8         3
 533 #define  STM_CRS_CFGR_SYNCDIV_16        4
 534 #define  STM_CRS_CFGR_SYNCDIV_32        5
 535 #define  STM_CRS_CFGR_SYNCDIV_64        6
 536 #define  STM_CRS_CFGR_SYNCDIV_128       7
 537 #define STM_CRS_CFGR_FELIM      16
 538 #define STM_CRS_CFGR_RELOAD     0
 539
 540 #define STM_CRS_ISR_FECAP       16
 541 #define STM_CRS_ISR_FEDIR       15
 542 #define STM_CRS_ISR_TRIMOVF     10
 543 #define STM_CRS_ISR_SYNCMISS    9
 544 #define STM_CRS_ISR_SYNCERR     8
 545 #define STM_CRS_ISR_ESYNCF      3
 546 #define STM_CRS_ISR_ERRF        2
 547 #define STM_CRS_ISR_SYNCWARNF   1
 548 #define STM_CRS_ISR_SYNCOKF     0
 549
 550 #define STM_CRS_ICR_ESYNCC      3
 551 #define STM_CRS_ICR_ERRC        2
 552 #define STM_CRS_ICR_SYNCWARNC   1
 553 #define STM_CRS_ICR_SYNCOKC     0
 554
 555 struct stm_pwr {
 556         vuint32_t       cr;
 557         vuint32_t       csr;
 558 };
 559
 560 extern struct stm_pwr stm_pwr;
 561
 562 #define STM_PWR_CR_DBP          (8)
 563
 564 #define STM_PWR_CR_PLS          (5)
 565 #define  STM_PWR_CR_PLS_2_0     0
 566 #define  STM_PWR_CR_PLS_2_1     1
 567 #define  STM_PWR_CR_PLS_2_2     2
 568 #define  STM_PWR_CR_PLS_2_3     3
 569 #define  STM_PWR_CR_PLS_2_4     4
 570 #define  STM_PWR_CR_PLS_2_5     5
 571 #define  STM_PWR_CR_PLS_2_6     6
 572 #define  STM_PWR_CR_PLS_EXT     7
 573 #define  STM_PWR_CR_PLS_MASK    7
 574
 575 #define STM_PWR_CR_PVDE         (4)
 576 #define STM_PWR_CR_CSBF         (3)
 577 #define STM_PWR_CR_CWUF         (2)
 578 #define STM_PWR_CR_PDDS         (1)
 579 #define STM_PWR_CR_LPSDSR       (0)
 580
 581 #define STM_PWR_CSR_EWUP3       (10)
 582 #define STM_PWR_CSR_EWUP2       (9)
 583 #define STM_PWR_CSR_EWUP1       (8)
 584 #define STM_PWR_CSR_REGLPF      (5)
 585 #define STM_PWR_CSR_VOSF        (4)
 586 #define STM_PWR_CSR_VREFINTRDYF (3)
 587 #define STM_PWR_CSR_PVDO        (2)
 588 #define STM_PWR_CSR_SBF         (1)
 589 #define STM_PWR_CSR_WUF         (0)
 590
 591 struct stm_crc {
 592         union {
 593                 vuint32_t       u32;
 594                 vuint16_t       u16;
 595                 vuint8_t        u8;
 596         }               dr;
 597         vuint32_t       idr;
 598         vuint32_t       cr;
 599         uint32_t        _0c;
 600
 601         vuint32_t       init;
 602         vuint32_t       pol;
 603 };
 604
 605 extern struct stm_crc   stm_crc;
 606
 607 #define stm_crc (*((struct stm_crc *) 0x40023000))
 608
 609 #define STM_CRC_CR_REV_OUT      7
 610 #define STM_CRC_CR_REV_IN       5
 611 #define  STM_CRC_CR_REV_IN_NONE         0
 612 #define  STM_CRC_CR_REV_IN_BY_BYTE      1
 613 #define  STM_CRC_CR_REV_IN_BY_HALF_WORD 2
 614 #define  STM_CRC_CR_REV_IN_BY_WORD      3
 615 #define STM_CRC_CR_POLYSIZE     3
 616 #define  STM_CRC_CR_POLYSIZE_32         0
 617 #define  STM_CRC_CR_POLYSIZE_16         1
 618 #define  STM_CRC_CR_POLYSIZE_8          2
 619 #define  STM_CRC_CR_POLYSIZE_7          3
 620 #define STM_CRC_CR_RESET        0
 621
 622 /* The SYSTICK starts at 0xe000e010 */
 623
 624 struct stm_systick {
 625         vuint32_t       csr;
 626         vuint32_t       rvr;
 627         vuint32_t       cvr;
 628         vuint32_t       calib;
 629 };
 630
 631 extern struct stm_systick stm_systick;
 632
 633 #define STM_SYSTICK_CSR_ENABLE          0
 634 #define STM_SYSTICK_CSR_TICKINT         1
 635 #define STM_SYSTICK_CSR_CLKSOURCE       2
 636 #define  STM_SYSTICK_CSR_CLKSOURCE_EXTERNAL             0
 637 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               1
 638 #define STM_SYSTICK_CSR_COUNTFLAG       16
 639
 640 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 641
 642 struct stm_nvic {
 643         vuint32_t       iser;           /* 0x000 0xe000e100 Set Enable Register */
 644
 645         uint8_t         _unused020[0x080 - 0x004];
 646
 647         vuint32_t       icer;           /* 0x080 0xe000e180 Clear Enable Register */
 648
 649         uint8_t         _unused0a0[0x100 - 0x084];
 650
 651         vuint32_t       ispr;           /* 0x100 0xe000e200 Set Pending Register */
 652
 653         uint8_t         _unused120[0x180 - 0x104];
 654
 655         vuint32_t       icpr;           /* 0x180 0xe000e280 Clear Pending Register */
 656
 657         uint8_t         _unused1a0[0x300 - 0x184];
 658
 659         vuint32_t       ipr[8];         /* 0x300 0xe000e400 Priority Register */
 660 };
 661
 662 extern struct stm_nvic stm_nvic;
 663
 664 #define IRQ_MASK(irq)   (1 << (irq))
 665 #define IRQ_BOOL(v,irq) (((v) >> (irq)) & 1)
 666
 667 static inline void
 668 stm_nvic_set_enable(int irq) {
 669         stm_nvic.iser = IRQ_MASK(irq);
 670 }
 671
 672 static inline void
 673 stm_nvic_clear_enable(int irq) {
 674         stm_nvic.icer = IRQ_MASK(irq);
 675 }
 676
 677 static inline int
 678 stm_nvic_enabled(int irq) {
 679         return IRQ_BOOL(stm_nvic.iser, irq);
 680 }
 681
 682 static inline void
 683 stm_nvic_set_pending(int irq) {
 684         stm_nvic.ispr = IRQ_MASK(irq);
 685 }
 686
 687 static inline void
 688 stm_nvic_clear_pending(int irq) {
 689         stm_nvic.icpr = IRQ_MASK(irq);
 690 }
 691
 692 static inline int
 693 stm_nvic_pending(int irq) {
 694         return IRQ_BOOL(stm_nvic.ispr, irq);
 695 }
 696
 697 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 698 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 699 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 700
 701 static inline void
 702 stm_nvic_set_priority(int irq, uint8_t prio) {
 703         int             n = IRQ_PRIO_REG(irq);
 704         uint32_t        v;
 705
 706         v = stm_nvic.ipr[n];
 707         v &= ~IRQ_PRIO_MASK(irq);
 708         v |= (prio) << IRQ_PRIO_BIT(irq);
 709         stm_nvic.ipr[n] = v;
 710 }
 711
 712 static inline uint8_t
 713 stm_nvic_get_priority(int irq) {
 714         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 715 }
 716
 717 struct stm_scb {
 718         vuint32_t       cpuid;
 719         vuint32_t       icsr;
 720         vuint32_t       vtor;
 721         vuint32_t       aircr;
 722
 723         vuint32_t       scr;
 724         vuint32_t       ccr;
 725         vuint32_t       shpr1;
 726         vuint32_t       shpr2;
 727
 728         vuint32_t       shpr3;
 729         vuint32_t       shcrs;
 730         vuint32_t       cfsr;
 731         vuint32_t       hfsr;
 732
 733         uint32_t        unused_30;
 734         vuint32_t       mmfar;
 735         vuint32_t       bfar;
 736 };
 737
 738 extern struct stm_scb stm_scb;
 739
 740 #define STM_SCB_AIRCR_VECTKEY           16
 741 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
 742 #define STM_SCB_AIRCR_PRIGROUP          8
 743 #define STM_SCB_AIRCR_SYSRESETREQ       2
 744 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
 745 #define STM_SCB_AIRCR_VECTRESET         0
 746
 747 #define isr(name) void stm_ ## name ## _isr(void);
 748
 749 isr(nmi)
 750 isr(hardfault)
 751 isr(memmanage)
 752 isr(busfault)
 753 isr(usagefault)
 754 isr(svc)
 755 isr(debugmon)
 756 isr(pendsv)
 757 isr(systick)
 758 isr(wwdg)
 759 isr(pvd)
 760 isr(tamper_stamp)
 761 isr(rtc_wkup)
 762 isr(flash)
 763 isr(rcc)
 764 isr(exti0)
 765 isr(exti1)
 766 isr(exti2)
 767 isr(exti3)
 768 isr(exti4)
 769 isr(dma1_channel1)
 770 isr(dma1_channel2)
 771 isr(dma1_channel3)
 772 isr(dma1_channel4)
 773 isr(dma1_channel5)
 774 isr(dma1_channel6)
 775 isr(dma1_channel7)
 776 isr(adc1)
 777 isr(usb_hp)
 778 isr(usb_lp)
 779 isr(dac)
 780 isr(comp)
 781 isr(exti9_5)
 782 isr(lcd)
 783 isr(tim9)
 784 isr(tim10)
 785 isr(tim11)
 786 isr(tim2)
 787 isr(tim3)
 788 isr(tim4)
 789 isr(i2c1_ev)
 790 isr(i2c1_er)
 791 isr(i2c2_ev)
 792 isr(i2c2_er)
 793 isr(spi1)
 794 isr(spi2)
 795 isr(usart1)
 796 isr(usart2)
 797 isr(usart3)
 798 isr(exti15_10)
 799 isr(rtc_alarm)
 800 isr(usb_fs_wkup)
 801 isr(tim6)
 802 isr(tim7)
 803
 804 #undef isr
 805
 806 #define STM_ISR_WWDG_POS                0
 807 #define STM_ISR_PVD_VDDIO2_POS          1
 808 #define STM_ISR_RTC_POS                 2
 809 #define STM_ISR_FLASH_POS               3
 810 #define STM_ISR_RCC_CRS_POS             4
 811 #define STM_ISR_EXTI0_1_POS             5
 812 #define STM_ISR_EXTI2_3_POS             6
 813 #define STM_ISR_EXTI4_15_POS            7
 814 #define STM_ISR_TSC_POS                 8
 815 #define STM_ISR_DMA_CH1_POS             9
 816 #define STM_ISR_DMA_CH2_3_DMA2_CH1_2_POS        10
 817 #define STM_ISR_DMA_CH4_5_6_7_DMA2_CH3_4_5_POS  11
 818 #define STM_ISR_ADC_COMP_POS            12
 819 #define STM_ISR_TIM1_BRK_UP_TRG_COM_POS 13
 820 #define STM_ISR_TIM1_CC_POS             14
 821 #define STM_ISR_TIM2_POS                15
 822 #define STM_ISR_TIM3_POS                16
 823 #define STM_ISR_TIM6_DAC_POS            17
 824 #define STM_ISR_TIM7_POS                18
 825 #define STM_ISR_TIM14_POS               19
 826 #define STM_ISR_TIM15_POS               20
 827 #define STM_ISR_TIM16_POS               21
 828 #define STM_ISR_TIM17_POS               22
 829 #define STM_ISR_I2C1_POS                23
 830 #define STM_ISR_I2C2_POS                24
 831 #define STM_ISR_SPI1_POS                25
 832 #define STM_ISR_SPI2_POS                26
 833 #define STM_ISR_USART1_POS              27
 834 #define STM_ISR_USART2_POS              28
 835 #define STM_ISR_UASART3_4_5_6_7_8_POS   29
 836 #define STM_ISR_CEC_CAN_POS             30
 837 #define STM_ISR_USB_POS                 31
 838
 839 struct stm_syscfg {
 840         vuint32_t       cfgr1;
 841         uint32_t        reserved_04;
 842         vuint32_t       exticr[4];
 843         vuint32_t       cfgr2;
 844         uint8_t         reserved_1c[0x80-0x1c];
 845         vuint32_t       itline[31];
 846 };
 847
 848 extern struct stm_syscfg stm_syscfg;
 849
 850 #define STM_SYSCFG_CFGR1_TIM3_DMA_RMP   30
 851 #define STM_SYSCFG_CFGR1_TIM2_DMA_RMP   29
 852 #define STM_SYSCFG_CFGR1_TIM1_DMA_RMP   28
 853 #define STM_SYSCFG_CFGR1_I2C1_DMA_RMP   27
 854 #define STM_SYSCFG_CFGR1_USART3_DMA_RMP 26
 855 #define STM_SYSCFG_CFGR1_USART2_DMA_RMP 25
 856 #define STM_SYSCFG_CFGR1_SPI2_DMA_RMP   24
 857 #define STM_SYSCFG_CFGR1_I2C_PA10_FMP   23
 858 #define STM_SYSCFG_CFGR1_I2C_PA9_FMP    22
 859 #define STM_SYSCFG_CFGR1_I2C2_FMP       21
 860 #define STM_SYSCFG_CFGR1_I2C1_FMP       20
 861 #define STM_SYSCFG_CFGR1_I2C_PB9_FMP    19
 862 #define STM_SYSCFG_CFGR1_I2C_PB8_FMP    18
 863 #define STM_SYSCFG_CFGR1_I2C_PB7_FMP    17
 864 #define STM_SYSCFG_CFGR1_I2C_PB6_FMP    16
 865 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP2 14
 866 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP2 13
 867 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP  12
 868 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP  11
 869 #define STM_SYSCFG_CFGR1_USART1_RX_DMA_RMP      10
 870 #define STM_SYSCFG_CFGR1_USART1_TX_DMA_RMP      9
 871 #define STM_SYSCFG_CFGR1_ADC_DMA_RMP            8
 872 #define STM_SYSCFG_CFGR1_IRDA_ENV_SEL   6
 873 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_TIMER16  0
 874 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART1   1
 875 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART4   2
 876 #define STM_SYSCFG_CFGR1_PA11_PA12_RMP  4
 877 #define STM_SYSCFG_CFGR1_MEM_MODE       0
 878 #define  STM_SYSCFG_CFGR1_MEM_MODE_MAIN_FLASH   0
 879 #define  STM_SYSCFG_CFGR1_MEM_MODE_SYSTEM_FLASH 1
 880 #define  STM_SYSCFG_CFGR1_MEM_MODE_SRAM         3
 881 #define  STM_SYSCFG_CFGR1_MEM_MODE_MASK         3
 882
 883 #define STM_SYSCFG_EXTICR_PA            0
 884 #define STM_SYSCFG_EXTICR_PB            1
 885 #define STM_SYSCFG_EXTICR_PC            2
 886 #define STM_SYSCFG_EXTICR_PD            3
 887 #define STM_SYSCFG_EXTICR_PE            4
 888 #define STM_SYSCFG_EXTICR_PF            5
 889
 890 static inline void
 891 stm_exticr_set(struct stm_gpio *gpio, int pin) {
 892         uint8_t reg = pin >> 2;
 893         uint8_t shift = (pin & 3) << 2;
 894         uint8_t val = 0;
 895
 896         /* Enable SYSCFG */
 897         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
 898
 899         if (gpio == &stm_gpioa)
 900                 val = STM_SYSCFG_EXTICR_PA;
 901         else if (gpio == &stm_gpiob)
 902                 val = STM_SYSCFG_EXTICR_PB;
 903         else if (gpio == &stm_gpioc)
 904                 val = STM_SYSCFG_EXTICR_PC;
 905         else if (gpio == &stm_gpiof)
 906                 val = STM_SYSCFG_EXTICR_PF;
 907
 908         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
 909 }
 910
 911 struct stm_dma_channel {
 912         vuint32_t       ccr;
 913         vuint32_t       cndtr;
 914         vvoid_t         cpar;
 915         vvoid_t         cmar;
 916         vuint32_t       reserved;
 917 };
 918
 919 #define STM_NUM_DMA     5
 920
 921 struct stm_dma {
 922         vuint32_t               isr;
 923         vuint32_t               ifcr;
 924         struct stm_dma_channel  channel[STM_NUM_DMA];
 925 };
 926
 927 extern struct stm_dma stm_dma;
 928
 929 /* DMA channels go from 1 to 5, instead of 0 to 4 (sigh)
 930  */
 931
 932 #define STM_DMA_INDEX(channel)          ((channel) - 1)
 933
 934 #define STM_DMA_ISR(index)              ((index) << 2)
 935 #define STM_DMA_ISR_MASK                        0xf
 936 #define STM_DMA_ISR_TEIF                        3
 937 #define STM_DMA_ISR_HTIF                        2
 938 #define STM_DMA_ISR_TCIF                        1
 939 #define STM_DMA_ISR_GIF                         0
 940
 941 #define STM_DMA_IFCR(index)             ((index) << 2)
 942 #define STM_DMA_IFCR_MASK                       0xf
 943 #define STM_DMA_IFCR_CTEIF                      3
 944 #define STM_DMA_IFCR_CHTIF                      2
 945 #define STM_DMA_IFCR_CTCIF                      1
 946 #define STM_DMA_IFCR_CGIF                       0
 947
 948 #define STM_DMA_CCR_MEM2MEM             (14)
 949
 950 #define STM_DMA_CCR_PL                  (12)
 951 #define  STM_DMA_CCR_PL_LOW                     (0)
 952 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
 953 #define  STM_DMA_CCR_PL_HIGH                    (2)
 954 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
 955 #define  STM_DMA_CCR_PL_MASK                    (3)
 956
 957 #define STM_DMA_CCR_MSIZE               (10)
 958 #define  STM_DMA_CCR_MSIZE_8                    (0)
 959 #define  STM_DMA_CCR_MSIZE_16                   (1)
 960 #define  STM_DMA_CCR_MSIZE_32                   (2)
 961 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
 962
 963 #define STM_DMA_CCR_PSIZE               (8)
 964 #define  STM_DMA_CCR_PSIZE_8                    (0)
 965 #define  STM_DMA_CCR_PSIZE_16                   (1)
 966 #define  STM_DMA_CCR_PSIZE_32                   (2)
 967 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
 968
 969 #define STM_DMA_CCR_MINC                (7)
 970 #define STM_DMA_CCR_PINC                (6)
 971 #define STM_DMA_CCR_CIRC                (5)
 972 #define STM_DMA_CCR_DIR                 (4)
 973 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
 974 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
 975 #define STM_DMA_CCR_TEIE                (3)
 976 #define STM_DMA_CCR_HTIE                (2)
 977 #define STM_DMA_CCR_TCIE                (1)
 978 #define STM_DMA_CCR_EN                  (0)
 979
 980 /* DMA channel assignments. When a peripheral has multiple channels
 981  * (indicated with _<number>), then it can be configured to either
 982  * channel using syscfg.cfgr1
 983  */
 984
 985 #define STM_DMA_CHANNEL_ADC_1           1
 986 #define STM_DMA_CHANNEL_ADC_2           2
 987
 988 #define STM_DMA_CHANNEL_SPI1_RX         2
 989 #define STM_DMA_CHANNEL_SPI1_TX         3
 990
 991 #define STM_DMA_CHANNEL_SPI2_RX         4
 992 #define STM_DMA_CHANNEL_SPI2_TX         5
 993
 994 #define STM_DMA_CHANNEL_USART1_TX_1     2
 995 #define STM_DMA_CHANNEL_USART1_RX_1     3
 996 #define STM_DMA_CHANNEL_USART1_TX_2     4
 997 #define STM_DMA_CHANNEL_USART1_RX_2     5
 998
 999 #define STM_DMA_CHANNEL_USART2_RX       4
1000 #define STM_DMA_CHANNEL_USART2_TX       5
1001
1002 #define STM_DMA_CHANNEL_I2C1_TX         2
1003 #define STM_DMA_CHANNEL_I2C1_RX         3
1004
1005 #define STM_DMA_CHANNEL_I2C2_TX         4
1006 #define STM_DMA_CHANNEL_I2C2_RX         5
1007
1008 #define STM_DMA_CHANNEL_TIM1_CH1        2
1009 #define STM_DMA_CHANNEL_TIM1_CH2        3
1010 #define STM_DMA_CHANNEL_TIM1_CH4        4
1011 #define STM_DMA_CHANNEL_TIM1_TRIG       4
1012 #define STM_DMA_CHANNEL_TIM1_COM        4
1013 #define STM_DMA_CHANNEL_TIM1_CH3        5
1014 #define STM_DMA_CHANNEL_TIM1_UP         5
1015
1016 #define STM_DMA_CHANNEL_TIM2_CH3        1
1017 #define STM_DMA_CHANNEL_TIM2_UP         2
1018 #define STM_DMA_CHANNEL_TIM2_CH2        3
1019 #define STM_DMA_CHANNEL_TIM2_CH4        4
1020 #define STM_DMA_CHANNEL_TIM2_CH1        5
1021
1022 #define STM_DMA_CHANNEL_TIM3_CH3        2
1023 #define STM_DMA_CHANNEL_TIM3_CH4        3
1024 #define STM_DMA_CHANNEL_TIM3_UP         3
1025 #define STM_DMA_CHANNEL_TIM3_CH1        4
1026 #define STM_DMA_CHANNEL_TIM3_TRIG       4
1027
1028 #define STM_DMA_CHANNEL_TIM6_UP_DAC     2
1029
1030 #define STM_DMA_CHANNEL_TIM15_CH1       5
1031 #define STM_DMA_CHANNEL_TIM15_UP        5
1032 #define STM_DMA_CHANNEL_TIM15_TRIG      5
1033 #define STM_DMA_CHANNEL_TIM15_COM       5
1034
1035 #define STM_DMA_CHANNEL_TIM16_CH1_1     3
1036 #define STM_DMA_CHANNEL_TIM16_UP_1      3
1037 #define STM_DMA_CHANNEL_TIM16_CH1_2     4
1038 #define STM_DMA_CHANNEL_TIM16_UP_2      4
1039
1040 #define STM_DMA_CHANNEL_TIM17_CH1_1     1
1041 #define STM_DMA_CHANNEL_TIM17_UP_1      1
1042 #define STM_DMA_CHANNEL_TIM17_CH1_2     2
1043 #define STM_DMA_CHANNEL_TIM17_UP_2      2
1044
1045 /*
1046  * Only spi channel 1 and 2 can use DMA
1047  */
1048 #define STM_NUM_SPI     2
1049
1050 struct stm_spi {
1051         vuint32_t       cr1;
1052         vuint32_t       cr2;
1053         vuint32_t       sr;
1054         vuint32_t       dr;
1055         vuint32_t       crcpr;
1056         vuint32_t       rxcrcr;
1057         vuint32_t       txcrcr;
1058 };
1059
1060 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1061
1062 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1063  */
1064
1065 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1066
1067 #define STM_SPI_CR1_BIDIMODE            15
1068 #define STM_SPI_CR1_BIDIOE              14
1069 #define STM_SPI_CR1_CRCEN               13
1070 #define STM_SPI_CR1_CRCNEXT             12
1071 #define STM_SPI_CR1_CRCL                11
1072 #define STM_SPI_CR1_RXONLY              10
1073 #define STM_SPI_CR1_SSM                 9
1074 #define STM_SPI_CR1_SSI                 8
1075 #define STM_SPI_CR1_LSBFIRST            7
1076 #define STM_SPI_CR1_SPE                 6
1077 #define STM_SPI_CR1_BR                  3
1078 #define  STM_SPI_CR1_BR_PCLK_2                  0
1079 #define  STM_SPI_CR1_BR_PCLK_4                  1
1080 #define  STM_SPI_CR1_BR_PCLK_8                  2
1081 #define  STM_SPI_CR1_BR_PCLK_16                 3
1082 #define  STM_SPI_CR1_BR_PCLK_32                 4
1083 #define  STM_SPI_CR1_BR_PCLK_64                 5
1084 #define  STM_SPI_CR1_BR_PCLK_128                6
1085 #define  STM_SPI_CR1_BR_PCLK_256                7
1086 #define  STM_SPI_CR1_BR_MASK                    7
1087
1088 #define STM_SPI_CR1_MSTR                2
1089 #define STM_SPI_CR1_CPOL                1
1090 #define STM_SPI_CR1_CPHA                0
1091
1092 #define STM_SPI_CR2_LDMA_TX     14
1093 #define STM_SPI_CR2_LDMA_RX     13
1094 #define STM_SPI_CR2_FRXTH       12
1095 #define STM_SPI_CR2_DS          8
1096 #define  STM_SPI_CR2_DS_4               0x3
1097 #define  STM_SPI_CR2_DS_5               0x4
1098 #define  STM_SPI_CR2_DS_6               0x5
1099 #define  STM_SPI_CR2_DS_7               0x6
1100 #define  STM_SPI_CR2_DS_8               0x7
1101 #define  STM_SPI_CR2_DS_9               0x8
1102 #define  STM_SPI_CR2_DS_10              0x9
1103 #define  STM_SPI_CR2_DS_11              0xa
1104 #define  STM_SPI_CR2_DS_12              0xb
1105 #define  STM_SPI_CR2_DS_13              0xc
1106 #define  STM_SPI_CR2_DS_14              0xd
1107 #define  STM_SPI_CR2_DS_15              0xe
1108 #define  STM_SPI_CR2_DS_16              0xf
1109 #define STM_SPI_CR2_TXEIE       7
1110 #define STM_SPI_CR2_RXNEIE      6
1111 #define STM_SPI_CR2_ERRIE       5
1112 #define STM_SPI_CR2_FRF         4
1113 # define STM_SPI_CR2_FRF_MOTOROLA       0
1114 # define STM_SPI_CR2_FRF_TI             1
1115 #define STM_SPI_CR2_NSSP        3
1116 #define STM_SPI_CR2_SSOE        2
1117 #define STM_SPI_CR2_TXDMAEN     1
1118 #define STM_SPI_CR2_RXDMAEN     0
1119
1120 #define STM_SPI_SR_FTLVL        11
1121 #define STM_SPI_SR_FRLVL        9
1122 #define STM_SPI_SR_FRE          8
1123 #define STM_SPI_SR_BSY          7
1124 #define STM_SPI_SR_OVR          6
1125 #define STM_SPI_SR_MODF         5
1126 #define STM_SPI_SR_CRCERR       4
1127 #define STM_SPI_SR_UDR          3
1128 #define STM_SPI_SR_CHSIDE       2
1129 #define STM_SPI_SR_TXE          1
1130 #define STM_SPI_SR_RXNE         0
1131
1132 struct stm_adc {
1133         vuint32_t       isr;
1134         vuint32_t       ier;
1135         vuint32_t       cr;
1136         vuint32_t       cfgr1;
1137
1138         vuint32_t       cfgr2;
1139         vuint32_t       smpr;
1140         vuint32_t       r_18;
1141         vuint32_t       r_1c;
1142
1143         vuint32_t       tr;
1144         vuint32_t       r_24;
1145         vuint32_t       chselr;
1146         vuint32_t       r_2c;
1147
1148         vuint32_t       r_30[4];
1149
1150         vuint32_t       dr;
1151
1152         uint8_t         r_44[0x308 - 0x44];
1153         vuint32_t       ccr;
1154 };
1155
1156 extern struct stm_adc stm_adc;
1157
1158 #define STM_ADC_ISR_AWD         7
1159 #define STM_ADC_ISR_OVR         4
1160 #define STM_ADC_ISR_EOSEQ       3
1161 #define STM_ADC_ISR_EOC         2
1162 #define STM_ADC_ISR_EOSMP       1
1163 #define STM_ADC_ISR_ADRDY       0
1164
1165 #define STM_ADC_IER_AWDIE       7
1166 #define STM_ADC_IER_OVRIE       4
1167 #define STM_ADC_IER_EOSEQIE     3
1168 #define STM_ADC_IER_EOCIE       2
1169 #define STM_ADC_IER_EOSMPIE     1
1170 #define STM_ADC_IER_ADRDYIE     0
1171
1172 #define STM_ADC_CR_ADCAL        31
1173 #define STM_ADC_CR_ADSTP        4
1174 #define STM_ADC_CR_ADSTART      2
1175 #define STM_ADC_CR_ADDIS        1
1176 #define STM_ADC_CR_ADEN         0
1177
1178 #define STM_ADC_CFGR1_AWDCH     26
1179 #define STM_ADC_CFGR1_AWDEN     23
1180 #define STM_ADC_CFGR1_AWDSGL    22
1181 #define STM_ADC_CFGR1_DISCEN    16
1182 #define STM_ADC_CFGR1_AUTOOFF   15
1183 #define STM_ADC_CFGR1_WAIT      14
1184 #define STM_ADC_CFGR1_CONT      13
1185 #define STM_ADC_CFGR1_OVRMOD    12
1186 #define STM_ADC_CFGR1_EXTEN     10
1187 #define  STM_ADC_CFGR1_EXTEN_DISABLE    0
1188 #define  STM_ADC_CFGR1_EXTEN_RISING     1
1189 #define  STM_ADC_CFGR1_EXTEN_FALLING    2
1190 #define  STM_ADC_CFGR1_EXTEN_BOTH       3
1191 #define  STM_ADC_CFGR1_EXTEN_MASK       3
1192
1193 #define STM_ADC_CFGR1_EXTSEL    6
1194 #define STM_ADC_CFGR1_ALIGN     5
1195 #define STM_ADC_CFGR1_RES       3
1196 #define  STM_ADC_CFGR1_RES_12           0
1197 #define  STM_ADC_CFGR1_RES_10           1
1198 #define  STM_ADC_CFGR1_RES_8            2
1199 #define  STM_ADC_CFGR1_RES_6            3
1200 #define  STM_ADC_CFGR1_RES_MASK         3
1201 #define STM_ADC_CFGR1_SCANDIR   2
1202 #define  STM_ADC_CFGR1_SCANDIR_UP       0
1203 #define  STM_ADC_CFGR1_SCANDIR_DOWN     1
1204 #define STM_ADC_CFGR1_DMACFG    1
1205 #define  STM_ADC_CFGR1_DMACFG_ONESHOT   0
1206 #define  STM_ADC_CFGR1_DMACFG_CIRCULAR  1
1207 #define STM_ADC_CFGR1_DMAEN     0
1208
1209 #define STM_ADC_CFGR2_CKMODE    30
1210 #define  STM_ADC_CFGR2_CKMODE_ADCCLK    0
1211 #define  STM_ADC_CFGR2_CKMODE_PCLK_2    1
1212 #define  STM_ADC_CFGR2_CKMODE_PCLK_4    2
1213
1214 #define STM_ADC_SMPR_SMP        0
1215 #define  STM_ADC_SMPR_SMP_1_5           0
1216 #define  STM_ADC_SMPR_SMP_7_5           1
1217 #define  STM_ADC_SMPR_SMP_13_5          2
1218 #define  STM_ADC_SMPR_SMP_28_5          3
1219 #define  STM_ADC_SMPR_SMP_41_5          4
1220 #define  STM_ADC_SMPR_SMP_55_5          5
1221 #define  STM_ADC_SMPR_SMP_71_5          6
1222 #define  STM_ADC_SMPR_SMP_239_5         7
1223
1224 #define STM_ADC_TR_HT           16
1225 #define STM_ADC_TR_LT           0
1226
1227 #define STM_ADC_CCR_VBATEN      24
1228 #define STM_ADC_CCR_TSEN        23
1229 #define STM_ADC_CCR_VREFEN      22
1230
1231 struct stm_cal {
1232         uint16_t        ts_cal_cold;    /* 30°C */
1233         uint16_t        vrefint_cal;
1234         uint16_t        unused_c0;
1235         uint16_t        ts_cal_hot;     /* 110°C */
1236 };
1237
1238 extern struct stm_cal   stm_cal;
1239
1240 #define stm_temp_cal_cold       30
1241 #define stm_temp_cal_hot        110
1242
1243 struct stm_dbgmcu {
1244         uint32_t        idcode;
1245 };
1246
1247 extern struct stm_dbgmcu        stm_dbgmcu;
1248
1249 static inline uint16_t
1250 stm_dev_id(void) {
1251         return stm_dbgmcu.idcode & 0xfff;
1252 }
1253
1254 struct stm_flash_size {
1255         uint16_t        f_size;
1256 };
1257
1258 extern struct stm_flash_size    stm_flash_size_04x;
1259
1260 /* Returns flash size in bytes */
1261 extern uint32_t
1262 stm_flash_size(void);
1263
1264 struct stm_device_id {
1265         uint32_t        u_id0;
1266         uint32_t        u_id1;
1267         uint32_t        u_id2;
1268 };
1269
1270 extern struct stm_device_id     stm_device_id;
1271
1272 #define STM_NUM_I2C     2
1273
1274 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1275
1276 struct stm_i2c {
1277         vuint32_t       cr1;
1278         vuint32_t       cr2;
1279         vuint32_t       oar1;
1280         vuint32_t       oar2;
1281         vuint32_t       dr;
1282         vuint32_t       sr1;
1283         vuint32_t       sr2;
1284         vuint32_t       ccr;
1285         vuint32_t       trise;
1286 };
1287
1288 extern struct stm_i2c stm_i2c1, stm_i2c2;
1289
1290 #define STM_I2C_CR1_SWRST       15
1291 #define STM_I2C_CR1_ALERT       13
1292 #define STM_I2C_CR1_PEC         12
1293 #define STM_I2C_CR1_POS         11
1294 #define STM_I2C_CR1_ACK         10
1295 #define STM_I2C_CR1_STOP        9
1296 #define STM_I2C_CR1_START       8
1297 #define STM_I2C_CR1_NOSTRETCH   7
1298 #define STM_I2C_CR1_ENGC        6
1299 #define STM_I2C_CR1_ENPEC       5
1300 #define STM_I2C_CR1_ENARP       4
1301 #define STM_I2C_CR1_SMBTYPE     3
1302 #define STM_I2C_CR1_SMBUS       1
1303 #define STM_I2C_CR1_PE          0
1304
1305 #define STM_I2C_CR2_LAST        12
1306 #define STM_I2C_CR2_DMAEN       11
1307 #define STM_I2C_CR2_ITBUFEN     10
1308 #define STM_I2C_CR2_ITEVTEN     9
1309 #define STM_I2C_CR2_ITERREN     8
1310 #define STM_I2C_CR2_FREQ        0
1311 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1312 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1313 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1314 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1315 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1316 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1317
1318 #define STM_I2C_SR1_SMBALERT    15
1319 #define STM_I2C_SR1_TIMEOUT     14
1320 #define STM_I2C_SR1_PECERR      12
1321 #define STM_I2C_SR1_OVR         11
1322 #define STM_I2C_SR1_AF          10
1323 #define STM_I2C_SR1_ARLO        9
1324 #define STM_I2C_SR1_BERR        8
1325 #define STM_I2C_SR1_TXE         7
1326 #define STM_I2C_SR1_RXNE        6
1327 #define STM_I2C_SR1_STOPF       4
1328 #define STM_I2C_SR1_ADD10       3
1329 #define STM_I2C_SR1_BTF         2
1330 #define STM_I2C_SR1_ADDR        1
1331 #define STM_I2C_SR1_SB          0
1332
1333 #define STM_I2C_SR2_PEC         8
1334 #define  STM_I2C_SR2_PEC_MASK   0xff00
1335 #define STM_I2C_SR2_DUALF       7
1336 #define STM_I2C_SR2_SMBHOST     6
1337 #define STM_I2C_SR2_SMBDEFAULT  5
1338 #define STM_I2C_SR2_GENCALL     4
1339 #define STM_I2C_SR2_TRA         2
1340 #define STM_I2C_SR2_BUSY        1
1341 #define STM_I2C_SR2_MSL         0
1342
1343 #define STM_I2C_CCR_FS          15
1344 #define STM_I2C_CCR_DUTY        14
1345 #define STM_I2C_CCR_CCR         0
1346 #define  STM_I2C_CCR_MASK       0x7ff
1347
1348 struct stm_tim23 {
1349         vuint32_t       cr1;
1350         vuint32_t       cr2;
1351         vuint32_t       smcr;
1352         vuint32_t       dier;
1353
1354         vuint32_t       sr;
1355         vuint32_t       egr;
1356         vuint32_t       ccmr1;
1357         vuint32_t       ccmr2;
1358
1359         vuint32_t       ccer;
1360         vuint32_t       cnt;
1361         vuint32_t       psc;
1362         vuint32_t       arr;
1363
1364         uint32_t        reserved_30;
1365         vuint32_t       ccr1;
1366         vuint32_t       ccr2;
1367         vuint32_t       ccr3;
1368
1369         vuint32_t       ccr4;
1370         uint32_t        reserved_44;
1371         vuint32_t       dcr;
1372         vuint32_t       dmar;
1373 };
1374
1375 extern struct stm_tim23 stm_tim2, stm_tim3;
1376
1377 #define stm_tim3        (*(struct stm_tim23 *) 0x40000400)
1378 #define stm_tim2        (*(struct stm_tim23 *) 0x40000000)
1379
1380 #define STM_TIM23_CR1_CKD       8
1381 #define  STM_TIM23_CR1_CKD_1            0
1382 #define  STM_TIM23_CR1_CKD_2            1
1383 #define  STM_TIM23_CR1_CKD_4            2
1384 #define  STM_TIM23_CR1_CKD_MASK 3
1385 #define STM_TIM23_CR1_ARPE      7
1386 #define STM_TIM23_CR1_CMS       5
1387 #define  STM_TIM23_CR1_CMS_EDGE         0
1388 #define  STM_TIM23_CR1_CMS_CENTER_1     1
1389 #define  STM_TIM23_CR1_CMS_CENTER_2     2
1390 #define  STM_TIM23_CR1_CMS_CENTER_3     3
1391 #define  STM_TIM23_CR1_CMS_MASK         3
1392 #define STM_TIM23_CR1_DIR       4
1393 #define  STM_TIM23_CR1_DIR_UP           0
1394 #define  STM_TIM23_CR1_DIR_DOWN         1
1395 #define STM_TIM23_CR1_OPM       3
1396 #define STM_TIM23_CR1_URS       2
1397 #define STM_TIM23_CR1_UDIS      1
1398 #define STM_TIM23_CR1_CEN       0
1399
1400 #define STM_TIM23_CR2_TI1S      7
1401 #define STM_TIM23_CR2_MMS       4
1402 #define  STM_TIM23_CR2_MMS_RESET                0
1403 #define  STM_TIM23_CR2_MMS_ENABLE               1
1404 #define  STM_TIM23_CR2_MMS_UPDATE               2
1405 #define  STM_TIM23_CR2_MMS_COMPARE_PULSE        3
1406 #define  STM_TIM23_CR2_MMS_COMPARE_OC1REF       4
1407 #define  STM_TIM23_CR2_MMS_COMPARE_OC2REF       5
1408 #define  STM_TIM23_CR2_MMS_COMPARE_OC3REF       6
1409 #define  STM_TIM23_CR2_MMS_COMPARE_OC4REF       7
1410 #define  STM_TIM23_CR2_MMS_MASK                 7
1411 #define STM_TIM23_CR2_CCDS      3
1412
1413 #define STM_TIM23_SMCR_ETP      15
1414 #define STM_TIM23_SMCR_ECE      14
1415 #define STM_TIM23_SMCR_ETPS     12
1416 #define  STM_TIM23_SMCR_ETPS_OFF                0
1417 #define  STM_TIM23_SMCR_ETPS_DIV_2              1
1418 #define  STM_TIM23_SMCR_ETPS_DIV_4              2
1419 #define  STM_TIM23_SMCR_ETPS_DIV_8              3
1420 #define  STM_TIM23_SMCR_ETPS_MASK               3
1421 #define STM_TIM23_SMCR_ETF      8
1422 #define  STM_TIM23_SMCR_ETF_NONE                0
1423 #define  STM_TIM23_SMCR_ETF_INT_N_2             1
1424 #define  STM_TIM23_SMCR_ETF_INT_N_4             2
1425 #define  STM_TIM23_SMCR_ETF_INT_N_8             3
1426 #define  STM_TIM23_SMCR_ETF_DTS_2_N_6           4
1427 #define  STM_TIM23_SMCR_ETF_DTS_2_N_8           5
1428 #define  STM_TIM23_SMCR_ETF_DTS_4_N_6           6
1429 #define  STM_TIM23_SMCR_ETF_DTS_4_N_8           7
1430 #define  STM_TIM23_SMCR_ETF_DTS_8_N_6           8
1431 #define  STM_TIM23_SMCR_ETF_DTS_8_N_8           9
1432 #define  STM_TIM23_SMCR_ETF_DTS_16_N_5          10
1433 #define  STM_TIM23_SMCR_ETF_DTS_16_N_6          11
1434 #define  STM_TIM23_SMCR_ETF_DTS_16_N_8          12
1435 #define  STM_TIM23_SMCR_ETF_DTS_32_N_5          13
1436 #define  STM_TIM23_SMCR_ETF_DTS_32_N_6          14
1437 #define  STM_TIM23_SMCR_ETF_DTS_32_N_8          15
1438 #define  STM_TIM23_SMCR_ETF_MASK                15
1439 #define STM_TIM23_SMCR_MSM      7
1440 #define STM_TIM23_SMCR_TS       4
1441 #define  STM_TIM23_SMCR_TS_ITR0                 0
1442 #define  STM_TIM23_SMCR_TS_ITR1                 1
1443 #define  STM_TIM23_SMCR_TS_ITR2                 2
1444 #define  STM_TIM23_SMCR_TS_ITR3                 3
1445 #define  STM_TIM23_SMCR_TS_TI1F_ED              4
1446 #define  STM_TIM23_SMCR_TS_TI1FP1               5
1447 #define  STM_TIM23_SMCR_TS_TI2FP2               6
1448 #define  STM_TIM23_SMCR_TS_ETRF                 7
1449 #define  STM_TIM23_SMCR_TS_MASK                 7
1450 #define STM_TIM23_SMCR_OCCS     3
1451 #define STM_TIM23_SMCR_SMS      0
1452 #define  STM_TIM23_SMCR_SMS_DISABLE             0
1453 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_1      1
1454 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_2      2
1455 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_3      3
1456 #define  STM_TIM23_SMCR_SMS_RESET_MODE          4
1457 #define  STM_TIM23_SMCR_SMS_GATED_MODE          5
1458 #define  STM_TIM23_SMCR_SMS_TRIGGER_MODE        6
1459 #define  STM_TIM23_SMCR_SMS_EXTERNAL_CLOCK      7
1460 #define  STM_TIM23_SMCR_SMS_MASK                7
1461
1462 #define STM_TIM23_SR_CC4OF      12
1463 #define STM_TIM23_SR_CC3OF      11
1464 #define STM_TIM23_SR_CC2OF      10
1465 #define STM_TIM23_SR_CC1OF      9
1466 #define STM_TIM23_SR_TIF        6
1467 #define STM_TIM23_SR_CC4IF      4
1468 #define STM_TIM23_SR_CC3IF      3
1469 #define STM_TIM23_SR_CC2IF      2
1470 #define STM_TIM23_SR_CC1IF      1
1471 #define STM_TIM23_SR_UIF        0
1472
1473 #define STM_TIM23_EGR_TG        6
1474 #define STM_TIM23_EGR_CC4G      4
1475 #define STM_TIM23_EGR_CC3G      3
1476 #define STM_TIM23_EGR_CC2G      2
1477 #define STM_TIM23_EGR_CC1G      1
1478 #define STM_TIM23_EGR_UG        0
1479
1480 #define STM_TIM23_CCMR1_OC2CE   15
1481 #define STM_TIM23_CCMR1_OC2M    12
1482 #define  STM_TIM23_CCMR1_OC2M_FROZEN                    0
1483 #define  STM_TIM23_CCMR1_OC2M_SET_HIGH_ON_MATCH         1
1484 #define  STM_TIM23_CCMR1_OC2M_SET_LOW_ON_MATCH          2
1485 #define  STM_TIM23_CCMR1_OC2M_TOGGLE                    3
1486 #define  STM_TIM23_CCMR1_OC2M_FORCE_LOW                 4
1487 #define  STM_TIM23_CCMR1_OC2M_FORCE_HIGH                5
1488 #define  STM_TIM23_CCMR1_OC2M_PWM_MODE_1                6
1489 #define  STM_TIM23_CCMR1_OC2M_PWM_MODE_2                7
1490 #define  STM_TIM23_CCMR1_OC2M_MASK                      7
1491 #define STM_TIM23_CCMR1_OC2PE   11
1492 #define STM_TIM23_CCMR1_OC2FE   10
1493 #define STM_TIM23_CCMR1_CC2S    8
1494 #define  STM_TIM23_CCMR1_CC2S_OUTPUT                    0
1495 #define  STM_TIM23_CCMR1_CC2S_INPUT_TI2                 1
1496 #define  STM_TIM23_CCMR1_CC2S_INPUT_TI1                 2
1497 #define  STM_TIM23_CCMR1_CC2S_INPUT_TRC                 3
1498 #define  STM_TIM23_CCMR1_CC2S_MASK                      3
1499
1500 #define STM_TIM23_CCMR1_OC1CE   7
1501 #define STM_TIM23_CCMR1_OC1M    4
1502 #define  STM_TIM23_CCMR1_OC1M_FROZEN                    0
1503 #define  STM_TIM23_CCMR1_OC1M_SET_HIGH_ON_MATCH         1
1504 #define  STM_TIM23_CCMR1_OC1M_SET_LOW_ON_MATCH          2
1505 #define  STM_TIM23_CCMR1_OC1M_TOGGLE                    3
1506 #define  STM_TIM23_CCMR1_OC1M_FORCE_LOW                 4
1507 #define  STM_TIM23_CCMR1_OC1M_FORCE_HIGH                5
1508 #define  STM_TIM23_CCMR1_OC1M_PWM_MODE_1                6
1509 #define  STM_TIM23_CCMR1_OC1M_PWM_MODE_2                7
1510 #define  STM_TIM23_CCMR1_OC1M_MASK                      7
1511 #define STM_TIM23_CCMR1_OC1PE   11
1512 #define STM_TIM23_CCMR1_OC1FE   2
1513 #define STM_TIM23_CCMR1_CC1S    0
1514 #define  STM_TIM23_CCMR1_CC1S_OUTPUT                    0
1515 #define  STM_TIM23_CCMR1_CC1S_INPUT_TI1                 1
1516 #define  STM_TIM23_CCMR1_CC1S_INPUT_TI2                 2
1517 #define  STM_TIM23_CCMR1_CC1S_INPUT_TRC                 3
1518 #define  STM_TIM23_CCMR1_CC1S_MASK                      3
1519
1520 #define STM_TIM23_CCMR2_OC4CE   15
1521 #define STM_TIM23_CCMR2_OC4M    12
1522 #define  STM_TIM23_CCMR2_OC4M_FROZEN                    0
1523 #define  STM_TIM23_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1524 #define  STM_TIM23_CCMR2_OC4M_SET_LOW_ON_MATCH          2
1525 #define  STM_TIM23_CCMR2_OC4M_TOGGLE                    3
1526 #define  STM_TIM23_CCMR2_OC4M_FORCE_LOW                 4
1527 #define  STM_TIM23_CCMR2_OC4M_FORCE_HIGH                5
1528 #define  STM_TIM23_CCMR2_OC4M_PWM_MODE_1                6
1529 #define  STM_TIM23_CCMR2_OC4M_PWM_MODE_2                7
1530 #define  STM_TIM23_CCMR2_OC4M_MASK                      7
1531 #define STM_TIM23_CCMR2_OC4PE   11
1532 #define STM_TIM23_CCMR2_OC4FE   10
1533 #define STM_TIM23_CCMR2_CC4S    8
1534 #define  STM_TIM23_CCMR2_CC4S_OUTPUT                    0
1535 #define  STM_TIM23_CCMR2_CC4S_INPUT_TI4                 1
1536 #define  STM_TIM23_CCMR2_CC4S_INPUT_TI3                 2
1537 #define  STM_TIM23_CCMR2_CC4S_INPUT_TRC                 3
1538 #define  STM_TIM23_CCMR2_CC4S_MASK                      3
1539
1540 #define STM_TIM23_CCMR2_OC3CE   7
1541 #define STM_TIM23_CCMR2_OC3M    4
1542 #define  STM_TIM23_CCMR2_OC3M_FROZEN                    0
1543 #define  STM_TIM23_CCMR2_OC3M_SET_HIGH_ON_MATCH         1
1544 #define  STM_TIM23_CCMR2_OC3M_SET_LOW_ON_MATCH          2
1545 #define  STM_TIM23_CCMR2_OC3M_TOGGLE                    3
1546 #define  STM_TIM23_CCMR2_OC3M_FORCE_LOW                 4
1547 #define  STM_TIM23_CCMR2_OC3M_FORCE_HIGH                5
1548 #define  STM_TIM23_CCMR2_OC3M_PWM_MODE_1                6
1549 #define  STM_TIM23_CCMR2_OC3M_PWM_MODE_2                7
1550 #define  STM_TIM23_CCMR2_OC3M_MASK                      7
1551 #define STM_TIM23_CCMR2_OC3PE   11
1552 #define STM_TIM23_CCMR2_OC3FE   2
1553 #define STM_TIM23_CCMR2_CC3S    0
1554 #define  STM_TIM23_CCMR2_CC3S_OUTPUT                    0
1555 #define  STM_TIM23_CCMR2_CC3S_INPUT_TI3                 1
1556 #define  STM_TIM23_CCMR2_CC3S_INPUT_TI4                 2
1557 #define  STM_TIM23_CCMR2_CC3S_INPUT_TRC                 3
1558 #define  STM_TIM23_CCMR2_CC3S_MASK                      3
1559
1560 #define STM_TIM23_CCER_CC4NP    15
1561 #define STM_TIM23_CCER_CC4P     13
1562 #define STM_TIM23_CCER_CC4E     12
1563 #define STM_TIM23_CCER_CC3NP    11
1564 #define STM_TIM23_CCER_CC3P     9
1565 #define STM_TIM23_CCER_CC3E     8
1566 #define STM_TIM23_CCER_CC2NP    7
1567 #define STM_TIM23_CCER_CC2P     5
1568 #define STM_TIM23_CCER_CC2E     4
1569 #define STM_TIM23_CCER_CC1NP    3
1570 #define STM_TIM23_CCER_CC1P     1
1571 #define STM_TIM23_CCER_CC1E     0
1572
1573 struct stm_usb {
1574         struct {
1575                 vuint16_t       r;
1576                 uint16_t        _;
1577         } epr[8];
1578         uint8_t         reserved_20[0x40 - 0x20];
1579         vuint16_t       cntr;
1580         uint16_t        reserved_42;
1581         vuint16_t       istr;
1582         uint16_t        reserved_46;
1583         vuint16_t       fnr;
1584         uint16_t        reserved_4a;
1585         vuint16_t       daddr;
1586         uint16_t        reserved_4e;
1587         vuint16_t       btable;
1588         uint16_t        reserved_52;
1589         vuint16_t       lpmcsr;
1590         uint16_t        reserved_56;
1591         vuint16_t       bcdr;
1592         uint16_t        reserved_5a;
1593 };
1594
1595 extern struct stm_usb stm_usb;
1596
1597 #define STM_USB_EPR_CTR_RX      15
1598 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1599 #define STM_USB_EPR_DTOG_RX     14
1600 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1601 #define STM_USB_EPR_STAT_RX     12
1602 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1603 #define  STM_USB_EPR_STAT_RX_STALL                      1
1604 #define  STM_USB_EPR_STAT_RX_NAK                        2
1605 #define  STM_USB_EPR_STAT_RX_VALID                      3
1606 #define  STM_USB_EPR_STAT_RX_MASK                       3
1607 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1608 #define STM_USB_EPR_SETUP       11
1609 #define STM_USB_EPR_EP_TYPE     9
1610 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1611 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1612 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1613 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1614 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1615 #define STM_USB_EPR_EP_KIND     8
1616 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1617 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1618 #define STM_USB_EPR_CTR_TX      7
1619 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1620 #define STM_USB_EPR_DTOG_TX     6
1621 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1622 #define STM_USB_EPR_STAT_TX     4
1623 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1624 #define  STM_USB_EPR_STAT_TX_STALL                      1
1625 #define  STM_USB_EPR_STAT_TX_NAK                        2
1626 #define  STM_USB_EPR_STAT_TX_VALID                      3
1627 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1628 #define  STM_USB_EPR_STAT_TX_MASK                       3
1629 #define STM_USB_EPR_EA          0
1630 #define  STM_USB_EPR_EA_MASK                            0xf
1631
1632 #define STM_USB_CNTR_CTRM       15
1633 #define STM_USB_CNTR_PMAOVRM    14
1634 #define STM_USB_CNTR_ERRM       13
1635 #define STM_USB_CNTR_WKUPM      12
1636 #define STM_USB_CNTR_SUSPM      11
1637 #define STM_USB_CNTR_RESETM     10
1638 #define STM_USB_CNTR_SOFM       9
1639 #define STM_USB_CNTR_ESOFM      8
1640 #define STM_USB_CNTR_RESUME     4
1641 #define STM_USB_CNTR_FSUSP      3
1642 #define STM_USB_CNTR_LP_MODE    2
1643 #define STM_USB_CNTR_PDWN       1
1644 #define STM_USB_CNTR_FRES       0
1645
1646 #define STM_USB_ISTR_CTR        15
1647 #define STM_USB_ISTR_PMAOVR     14
1648 #define STM_USB_ISTR_ERR        13
1649 #define STM_USB_ISTR_WKUP       12
1650 #define STM_USB_ISTR_SUSP       11
1651 #define STM_USB_ISTR_RESET      10
1652 #define STM_USB_ISTR_SOF        9
1653 #define STM_USB_ISTR_ESOF       8
1654 #define STM_USB_L1REQ           7
1655 #define STM_USB_ISTR_DIR        4
1656 #define STM_USB_ISTR_EP_ID      0
1657 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1658
1659 #define STM_USB_FNR_RXDP        15
1660 #define STM_USB_FNR_RXDM        14
1661 #define STM_USB_FNR_LCK         13
1662 #define STM_USB_FNR_LSOF        11
1663 #define  STM_USB_FNR_LSOF_MASK                  0x3
1664 #define STM_USB_FNR_FN          0
1665 #define  STM_USB_FNR_FN_MASK                    0x7ff
1666
1667 #define STM_USB_DADDR_EF        7
1668 #define STM_USB_DADDR_ADD       0
1669 #define  STM_USB_DADDR_ADD_MASK                 0x7f
1670
1671 #define STM_USB_BCDR_DPPU       15
1672 #define STM_USB_BCDR_PS2DET     7
1673 #define STM_USB_BCDR_SDET       6
1674 #define STM_USB_BCDR_PDET       5
1675 #define STM_USB_BCDR_DCDET      4
1676 #define STM_USB_BCDR_SDEN       3
1677 #define STM_USB_BCDR_PDEN       2
1678 #define STM_USB_BCDR_DCDEN      1
1679 #define STM_USB_BCDR_BCDEN      0
1680
1681 union stm_usb_bdt {
1682         struct {
1683                 vuint16_t       addr_tx;
1684                 vuint16_t       count_tx;
1685                 vuint16_t       addr_rx;
1686                 vuint16_t       count_rx;
1687         } single;
1688         struct {
1689                 vuint16_t       addr;
1690                 vuint16_t       count;
1691         } double_tx[2];
1692         struct {
1693                 vuint16_t       addr;
1694                 vuint16_t       count;
1695         } double_rx[2];
1696 };
1697
1698 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
1699 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
1700 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
1701 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
1702 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
1703
1704 #define STM_USB_BDT_SIZE        8
1705
1706 extern uint8_t stm_usb_sram[];
1707
1708 struct stm_exti {
1709         vuint32_t       imr;
1710         vuint32_t       emr;
1711         vuint32_t       rtsr;
1712         vuint32_t       ftsr;
1713
1714         vuint32_t       swier;
1715         vuint32_t       pr;
1716 };
1717
1718 extern struct stm_exti stm_exti;
1719
1720 #endif /* _STM32F0_H_ */