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   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19 #include <ao_data.h>
  20
  21 #define AO_ADC_DEBUG    0
  22
  23 static uint8_t  ao_adc_ready;
  24
  25 /*
  26  * Callback from DMA ISR
  27  *
  28  * Mark time in ring, shut down DMA engine
  29  */
  30 static void ao_adc_done(int index)
  31 {
  32         (void) index;
  33         /* Clear ISR bits */
  34         stm_adc.isr = ((1 << STM_ADC_ISR_AWD) |
  35                        (1 << STM_ADC_ISR_OVR) |
  36                        (1 << STM_ADC_ISR_EOSEQ) |
  37                        (1 << STM_ADC_ISR_EOC));
  38
  39         AO_DATA_PRESENT(AO_DATA_ADC);
  40         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
  41         if (ao_data_present == AO_DATA_ALL) {
  42 #if HAS_MS5607
  43                 ao_data_ring[ao_data_head].ms5607_raw = ao_ms5607_current;
  44 #endif
  45 #if HAS_MMA655X
  46                 ao_data_ring[ao_data_head].mma655x = ao_mma655x_current;
  47 #endif
  48 #if HAS_HMC5883
  49                 ao_data_ring[ao_data_head].hmc5883 = ao_hmc5883_current;
  50 #endif
  51 #if HAS_MPU6000
  52                 ao_data_ring[ao_data_head].mpu6000 = ao_mpu6000_current;
  53 #endif
  54                 ao_data_ring[ao_data_head].tick = ao_tick_count;
  55                 ao_data_head = ao_data_ring_next(ao_data_head);
  56                 ao_wakeup((void *) &ao_data_head);
  57         }
  58         ao_adc_ready = 1;
  59 }
  60
  61 /*
  62  * Start the ADC sequence using the DMA engine
  63  */
  64 void
  65 ao_adc_poll(void)
  66 {
  67         if (!ao_adc_ready)
  68                 return;
  69         ao_adc_ready = 0;
  70         stm_adc.isr = 0;
  71         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1),
  72                             &stm_adc.dr,
  73                             (void *) (&ao_data_ring[ao_data_head].adc),
  74                             AO_NUM_ADC,
  75                             (0 << STM_DMA_CCR_MEM2MEM) |
  76                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  77                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  78                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  79                             (1 << STM_DMA_CCR_MINC) |
  80                             (0 << STM_DMA_CCR_PINC) |
  81                             (0 << STM_DMA_CCR_CIRC) |
  82                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR) |
  83                             (1 << STM_DMA_CCR_TCIE));
  84         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1), ao_adc_done);
  85         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
  86
  87         stm_adc.cr |= (1 << STM_ADC_CR_ADSTART);
  88 }
  89
  90 static void
  91 ao_adc_dump(void)
  92 {
  93         struct ao_data  packet;
  94
  95         ao_data_get(&packet);
  96         AO_ADC_DUMP(&packet);
  97 }
  98
  99 #if AO_ADC_DEBUG
 100 static void
 101 ao_adc_one(void)
 102 {
 103         int             ch;
 104         uint16_t        value;
 105
 106         ao_cmd_decimal();
 107         if (ao_cmd_status != ao_cmd_success)
 108                 return;
 109         ch = ao_cmd_lex_i;
 110         if (ch < 0 || AO_NUM_ADC <= ch) {
 111                 ao_cmd_status = ao_cmd_syntax_error;
 112                 return;
 113         }
 114
 115         ao_timer_set_adc_interval(0);
 116         ao_delay(1);
 117
 118         printf("At top, data %u isr %04x cr %04x\n", stm_adc.dr, stm_adc.isr, stm_adc.cr);
 119
 120         if (stm_adc.cr & (1 << STM_ADC_CR_ADEN)) {
 121                 printf("Disabling\n"); flush();
 122                 stm_adc.cr |= (1 << STM_ADC_CR_ADDIS);
 123                 while (stm_adc.cr & (1 << STM_ADC_CR_ADDIS))
 124                         ;
 125                 printf("Disabled\n"); flush();
 126         }
 127
 128         /* Turn off everything */
 129         stm_adc.cr &= ~((1 << STM_ADC_CR_ADCAL) |
 130                         (1 << STM_ADC_CR_ADSTP) |
 131                         (1 << STM_ADC_CR_ADSTART) |
 132                         (1 << STM_ADC_CR_ADEN));
 133
 134         printf("After disable, ADC status %04x\n", stm_adc.cr);
 135
 136         /* Configure */
 137         stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) |                             /* analog watchdog channel 0 */
 138                          (0 << STM_ADC_CFGR1_AWDEN) |                             /* Disable analog watchdog */
 139                          (0 << STM_ADC_CFGR1_AWDSGL) |                            /* analog watchdog on all channels */
 140                          (0 << STM_ADC_CFGR1_DISCEN) |                            /* Not discontinuous mode. All channels converted with one trigger */
 141                          (0 << STM_ADC_CFGR1_AUTOOFF) |                           /* Leave ADC running */
 142                          (1 << STM_ADC_CFGR1_WAIT) |                              /* Wait for data to be read before next conversion */
 143                          (0 << STM_ADC_CFGR1_CONT) |                              /* only one set of conversions per trigger */
 144                          (1 << STM_ADC_CFGR1_OVRMOD) |                            /* overwrite on overrun */
 145                          (STM_ADC_CFGR1_EXTEN_DISABLE << STM_ADC_CFGR1_EXTEN) |   /* SW trigger */
 146                          (0 << STM_ADC_CFGR1_ALIGN) |                             /* Align to LSB */
 147                          (STM_ADC_CFGR1_RES_12 << STM_ADC_CFGR1_RES) |            /* 12 bit resolution */
 148                          (STM_ADC_CFGR1_SCANDIR_UP << STM_ADC_CFGR1_SCANDIR) |    /* scan 0 .. n */
 149                          (STM_ADC_CFGR1_DMACFG_ONESHOT << STM_ADC_CFGR1_DMACFG) | /* one set of conversions then stop */
 150                          (0 << STM_ADC_CFGR1_DMAEN));                             /* disable DMA */
 151
 152         stm_adc.chselr = (1 << ch);
 153
 154         /* Longest sample time */
 155         stm_adc.smpr = STM_ADC_SMPR_SMP_41_5 << STM_ADC_SMPR_SMP;
 156
 157         printf("Before enable, ADC status %04x\n", stm_adc.cr); flush();
 158         /* Enable */
 159         stm_adc.cr |= (1 << STM_ADC_CR_ADEN);
 160         while ((stm_adc.isr & (1 << STM_ADC_ISR_ADRDY)) == 0)
 161                 ;
 162
 163         /* Start */
 164         stm_adc.cr |= (1 << STM_ADC_CR_ADSTART);
 165
 166         /* Wait for conversion complete */
 167         while (!(stm_adc.isr & (1 << STM_ADC_ISR_EOC)))
 168                 ;
 169
 170         value = stm_adc.dr;
 171         printf ("value %u, cr is %04x isr is %04x\n",
 172                 value, stm_adc.cr, stm_adc.isr);
 173
 174
 175         /* Clear ISR bits */
 176         stm_adc.isr = ((1 << STM_ADC_ISR_AWD) |
 177                        (1 << STM_ADC_ISR_OVR) |
 178                        (1 << STM_ADC_ISR_EOSEQ) |
 179                        (1 << STM_ADC_ISR_EOC));
 180 }
 181 #endif
 182
 183 const struct ao_cmds ao_adc_cmds[] = {
 184         { ao_adc_dump,  "a\0Display current ADC values" },
 185 #if AO_ADC_DEBUG
 186         { ao_adc_one,   "A ch\0Display one ADC channel" },
 187 #endif
 188         { 0, NULL },
 189 };
 190
 191 void
 192 ao_adc_init(void)
 193 {
 194         uint32_t        chselr;
 195
 196         /* Reset ADC */
 197         stm_rcc.apb2rstr |= (1 << STM_RCC_APB2RSTR_ADCRST);
 198         stm_rcc.apb2rstr &= ~(1 << STM_RCC_APB2RSTR_ADCRST);
 199
 200         /* Turn on ADC pins */
 201         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
 202
 203 #ifdef AO_ADC_PIN0_PORT
 204         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
 205         stm_pupdr_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_PUPDR_NONE);
 206 #endif
 207 #ifdef AO_ADC_PIN1_PORT
 208         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
 209         stm_pupdr_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_PUPDR_NONE);
 210 #endif
 211 #ifdef AO_ADC_PIN2_PORT
 212         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 213         stm_pupdr_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_PUPDR_NONE);
 214 #endif
 215 #ifdef AO_ADC_PIN3_PORT
 216         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 217         stm_pupdr_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_PUPDR_NONE);
 218 #endif
 219 #ifdef AO_ADC_PIN4_PORT
 220         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 221         stm_pupdr_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_PUPDR_NONE);
 222 #endif
 223 #ifdef AO_ADC_PIN5_PORT
 224         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 225         stm_pupdr_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_PUPDR_NONE);
 226 #endif
 227 #ifdef AO_ADC_PIN6_PORT
 228         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 229         stm_pupdr_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_PUPDR_NONE);
 230 #endif
 231 #ifdef AO_ADC_PIN7_PORT
 232         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 233         stm_pupdr_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_PUPDR_NONE);
 234 #endif
 235 #ifdef AO_ADC_PIN24_PORT
 236         #error "Too many ADC ports"
 237 #endif
 238
 239         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADCEN);
 240
 241         chselr = 0;
 242 #if AO_NUM_ADC > 0
 243         chselr |= (1 << AO_ADC_PIN0_CH);
 244 #endif
 245 #if AO_NUM_ADC > 1
 246         chselr |= (1 << AO_ADC_PIN1_CH);
 247 #endif
 248 #if AO_NUM_ADC > 2
 249         chselr |= (1 << AO_ADC_PIN2_CH);
 250 #endif
 251 #if AO_NUM_ADC > 3
 252         chselr |= (1 << AO_ADC_PIN3_CH);
 253 #endif
 254 #if AO_NUM_ADC > 4
 255         chselr |= (1 << AO_ADC_PIN4_CH);
 256 #endif
 257 #if AO_NUM_ADC > 5
 258         chselr |= (1 << AO_ADC_PIN5_CH);
 259 #endif
 260 #if AO_NUM_ADC > 6
 261         chselr |= (1 << AO_ADC_PIN6_CH);
 262 #endif
 263 #if AO_NUM_ADC > 7
 264         chselr |= (1 << AO_ADC_PIN7_CH);
 265 #endif
 266 #if AO_NUM_ADC > 8
 267 #error Need more ADC defines
 268 #endif
 269
 270         /* Wait for ADC to be idle */
 271         while (stm_adc.cr & ((1 << STM_ADC_CR_ADCAL) |
 272                              (1 << STM_ADC_CR_ADDIS)))
 273                 ;
 274
 275         /* Disable */
 276         if (stm_adc.cr & (1 << STM_ADC_CR_ADEN)) {
 277                 stm_adc.cr |= (1 << STM_ADC_CR_ADDIS);
 278                 while (stm_adc.cr & (1 << STM_ADC_CR_ADDIS))
 279                         ;
 280         }
 281
 282         /* Turn off everything */
 283         stm_adc.cr &= ~((1 << STM_ADC_CR_ADCAL) |
 284                         (1 << STM_ADC_CR_ADSTP) |
 285                         (1 << STM_ADC_CR_ADSTART) |
 286                         (1 << STM_ADC_CR_ADEN));
 287
 288         /* Configure */
 289         stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) |                             /* analog watchdog channel 0 */
 290                          (0 << STM_ADC_CFGR1_AWDEN) |                             /* Disable analog watchdog */
 291                          (0 << STM_ADC_CFGR1_AWDSGL) |                            /* analog watchdog on all channels */
 292                          (0 << STM_ADC_CFGR1_DISCEN) |                            /* Not discontinuous mode. All channels converted with one trigger */
 293                          (0 << STM_ADC_CFGR1_AUTOOFF) |                           /* Leave ADC running */
 294                          (1 << STM_ADC_CFGR1_WAIT) |                              /* Wait for data to be read before next conversion */
 295                          (0 << STM_ADC_CFGR1_CONT) |                              /* only one set of conversions per trigger */
 296                          (1 << STM_ADC_CFGR1_OVRMOD) |                            /* overwrite on overrun */
 297                          (STM_ADC_CFGR1_EXTEN_DISABLE << STM_ADC_CFGR1_EXTEN) |   /* SW trigger */
 298                          (0 << STM_ADC_CFGR1_ALIGN) |                             /* Align to LSB */
 299                          (STM_ADC_CFGR1_RES_12 << STM_ADC_CFGR1_RES) |            /* 12 bit resolution */
 300                          (STM_ADC_CFGR1_SCANDIR_UP << STM_ADC_CFGR1_SCANDIR) |    /* scan 0 .. n */
 301                          (STM_ADC_CFGR1_DMACFG_ONESHOT << STM_ADC_CFGR1_DMACFG) | /* one set of conversions then stop */
 302                          (1 << STM_ADC_CFGR1_DMAEN));                             /* enable DMA */
 303
 304         /* Set the clock */
 305         stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_2 << STM_ADC_CFGR2_CKMODE;
 306
 307         /* Shortest sample time */
 308         stm_adc.smpr = STM_ADC_SMPR_SMP_71_5 << STM_ADC_SMPR_SMP;
 309
 310         stm_adc.chselr = chselr;
 311
 312         stm_adc.ccr = ((0 << STM_ADC_CCR_VBATEN) |
 313                        (0 << STM_ADC_CCR_TSEN) |
 314                        (0 << STM_ADC_CCR_VREFEN));
 315
 316         /* Calibrate */
 317         stm_adc.cr |= (1 << STM_ADC_CR_ADCAL);
 318         while ((stm_adc.cr & (1 << STM_ADC_CR_ADCAL)) != 0)
 319                 ;
 320
 321         /* Enable */
 322         stm_adc.cr |= (1 << STM_ADC_CR_ADEN);
 323         while ((stm_adc.isr & (1 << STM_ADC_ISR_ADRDY)) == 0)
 324                 ;
 325
 326         /* Clear any stale status bits */
 327         stm_adc.isr = 0;
 328
 329         /* Turn on syscfg */
 330         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
 331
 332         /* Set ADC to use DMA channel 1 (option 1) */
 333         stm_syscfg.cfgr1 &= ~(1 << STM_SYSCFG_CFGR1_ADC_DMA_RMP);
 334
 335         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
 336
 337         ao_cmd_register(&ao_adc_cmds[0]);
 338
 339         ao_adc_ready = 1;
 340 }