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   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19 #include <ao_adc_fast.h>
  20
  21 uint16_t ao_adc_ring[AO_ADC_RING_SIZE] __attribute__((aligned(4)));
  22
  23 /* Maximum number of samples fetched per _ao_adc_start call */
  24 #define AO_ADC_RING_CHUNK       (AO_ADC_RING_SIZE >> 1)
  25
  26 uint16_t ao_adc_ring_head, ao_adc_ring_tail;
  27 uint16_t ao_adc_running;
  28
  29 /*
  30  * Callback from DMA ISR
  31  *
  32  * Wakeup any waiting processes, mark the DMA as done, start the ADC
  33  * if there's still lots of space in the ring
  34  */
  35 static void ao_adc_dma_done(int index)
  36 {
  37         (void) index;
  38         ao_adc_ring_head += ao_adc_running;
  39         if (ao_adc_ring_head == AO_ADC_RING_SIZE)
  40                 ao_adc_ring_head = 0;
  41         ao_adc_running = 0;
  42         ao_wakeup(&ao_adc_ring_head);
  43         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
  44         _ao_adc_start();
  45 }
  46
  47 void
  48 _ao_adc_start(void)
  49 {
  50         uint16_t        *buf;
  51         uint16_t        count;
  52
  53         if (ao_adc_running)
  54                 return;
  55         count = _ao_adc_space();
  56         if (count == 0)
  57                 return;
  58         if (count > AO_ADC_RING_CHUNK)
  59                 count = AO_ADC_RING_CHUNK;
  60         ao_adc_running = count;
  61         buf = ao_adc_ring + ao_adc_ring_head;
  62         stm_adc.isr = 0;
  63         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1),
  64                             &stm_adc.dr,
  65                             buf,
  66                             count,
  67                             (0 << STM_DMA_CCR_MEM2MEM) |
  68                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  69                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  70                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  71                             (1 << STM_DMA_CCR_MINC) |
  72                             (0 << STM_DMA_CCR_PINC) |
  73                             (0 << STM_DMA_CCR_CIRC) |
  74                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  75         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1), ao_adc_dma_done);
  76         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
  77
  78         stm_adc.cr |= (1 << STM_ADC_CR_ADSTART);
  79 }
  80
  81 void
  82 ao_adc_init(void)
  83 {
  84         uint32_t        chselr;
  85         int             i;
  86
  87         /* Reset ADC */
  88         stm_rcc.apb2rstr |= (1 << STM_RCC_APB2RSTR_ADCRST);
  89         stm_rcc.apb2rstr &= ~(1 << STM_RCC_APB2RSTR_ADCRST);
  90
  91         /* Turn on ADC pins */
  92         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
  93
  94 #ifdef AO_ADC_PIN0_PORT
  95         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
  96 #endif
  97 #ifdef AO_ADC_PIN1_PORT
  98         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
  99 #endif
 100 #ifdef AO_ADC_PIN2_PORT
 101         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 102 #endif
 103 #ifdef AO_ADC_PIN3_PORT
 104         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 105 #endif
 106 #ifdef AO_ADC_PIN4_PORT
 107         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 108 #endif
 109 #ifdef AO_ADC_PIN5_PORT
 110         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 111 #endif
 112 #ifdef AO_ADC_PIN6_PORT
 113         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 114 #endif
 115 #ifdef AO_ADC_PIN7_PORT
 116         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 117 #endif
 118 #ifdef AO_ADC_PIN24_PORT
 119         #error "Too many ADC ports"
 120 #endif
 121
 122         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADCEN);
 123
 124         chselr = 0;
 125 #if AO_NUM_ADC > 0
 126         chselr |= (1 << AO_ADC_PIN0_CH);
 127 #endif
 128 #if AO_NUM_ADC > 1
 129         chselr |= (1 << AO_ADC_PIN1_CH);
 130 #endif
 131 #if AO_NUM_ADC > 2
 132         chselr |= (1 << AO_ADC_PIN2_CH);
 133 #endif
 134 #if AO_NUM_ADC > 3
 135         chselr |= (1 << AO_ADC_PIN3_CH);
 136 #endif
 137 #if AO_NUM_ADC > 4
 138         chselr |= (1 << AO_ADC_PIN4_CH);
 139 #endif
 140 #if AO_NUM_ADC > 5
 141         chselr |= (1 << AO_ADC_PIN5_CH);
 142 #endif
 143 #if AO_NUM_ADC > 6
 144         chselr |= (1 << AO_ADC_PIN6_CH);
 145 #endif
 146 #if AO_NUM_ADC > 7
 147         chselr |= (1 << AO_ADC_PIN7_CH);
 148 #endif
 149 #if AO_NUM_ADC > 8
 150 #error Need more ADC defines
 151 #endif
 152
 153         /* Set the clock */
 154         stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_2 << STM_ADC_CFGR2_CKMODE;
 155
 156         /* Shortest sample time */
 157         stm_adc.smpr = STM_ADC_SMPR_SMP_1_5 << STM_ADC_SMPR_SMP;
 158
 159         /* Calibrate */
 160         stm_adc.cr |= (1 << STM_ADC_CR_ADCAL);
 161         for (i = 0; i < 0xf000; i++) {
 162                 if ((stm_adc.cr & (1 << STM_ADC_CR_ADCAL)) == 0)
 163                         break;
 164         }
 165
 166         /* Enable */
 167         stm_adc.cr |= (1 << STM_ADC_CR_ADEN);
 168         while ((stm_adc.isr & (1 << STM_ADC_ISR_ADRDY)) == 0)
 169                 ;
 170
 171         stm_adc.chselr = chselr;
 172
 173         stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) |
 174                          (0 << STM_ADC_CFGR1_AWDEN) |
 175                          (0 << STM_ADC_CFGR1_AWDSGL) |
 176                          (0 << STM_ADC_CFGR1_DISCEN) |
 177                          (0 << STM_ADC_CFGR1_AUTOOFF) |
 178                          (0 << STM_ADC_CFGR1_WAIT) |
 179                          (1 << STM_ADC_CFGR1_CONT) |
 180                          (1 << STM_ADC_CFGR1_OVRMOD) |
 181                          (STM_ADC_CFGR1_EXTEN_DISABLE << STM_ADC_CFGR1_EXTEN) |
 182                          (0 << STM_ADC_CFGR1_ALIGN) |
 183                          (STM_ADC_CFGR1_RES_12 << STM_ADC_CFGR1_RES) |
 184                          (STM_ADC_CFGR1_SCANDIR_UP << STM_ADC_CFGR1_SCANDIR) |
 185                          (STM_ADC_CFGR1_DMACFG_ONESHOT << STM_ADC_CFGR1_DMACFG) |
 186                          (1 << STM_ADC_CFGR1_DMAEN));
 187         stm_adc.ccr = 0;
 188
 189         /* Clear any stale status bits */
 190         stm_adc.isr = 0;
 191
 192         /* Turn on syscfg */
 193         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
 194
 195         /* Set ADC to use DMA channel 1 (option 1) */
 196         stm_syscfg.cfgr1 &= ~(1 << STM_SYSCFG_CFGR1_ADC_DMA_RMP);
 197
 198         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
 199 }