2 * Copyright © 2015 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #include <ao_adc_fast.h>
21 static uint8_t ao_adc_done;
24 * Callback from DMA ISR
26 * Mark time in ring, shut down DMA engine
28 static void ao_adc_dma_done(int index)
32 ao_wakeup(&ao_adc_done);
36 * Start the ADC sequence using the DMA engine
39 ao_adc_read(uint16_t *dest, int len)
43 ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1),
47 (0 << STM_DMA_CCR_MEM2MEM) |
48 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
49 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
50 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
51 (1 << STM_DMA_CCR_MINC) |
52 (0 << STM_DMA_CCR_PINC) |
53 (0 << STM_DMA_CCR_CIRC) |
54 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
55 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1), ao_adc_dma_done);
56 ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
58 stm_adc.cr |= (1 << STM_ADC_CR_ADSTART);
59 ao_arch_block_interrupts();
61 ao_sleep(&ao_adc_done);
62 ao_arch_release_interrupts();
64 ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
66 stm_adc.cr |= (1 << STM_ADC_CR_ADSTP);
67 while ((stm_adc.cr & (1 << STM_ADC_CR_ADSTP)) != 0)
78 stm_rcc.apb2rstr |= (1 << STM_RCC_APB2RSTR_ADCRST);
79 stm_rcc.apb2rstr &= ~(1 << STM_RCC_APB2RSTR_ADCRST);
81 /* Turn on ADC pins */
82 stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
84 #ifdef AO_ADC_PIN0_PORT
85 stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
87 #ifdef AO_ADC_PIN1_PORT
88 stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
90 #ifdef AO_ADC_PIN2_PORT
91 stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
93 #ifdef AO_ADC_PIN3_PORT
94 stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
96 #ifdef AO_ADC_PIN4_PORT
97 stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
99 #ifdef AO_ADC_PIN5_PORT
100 stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
102 #ifdef AO_ADC_PIN6_PORT
103 stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
105 #ifdef AO_ADC_PIN7_PORT
106 stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
108 #ifdef AO_ADC_PIN24_PORT
109 #error "Too many ADC ports"
112 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADCEN);
116 chselr |= (1 << AO_ADC_PIN0_CH);
119 chselr |= (1 << AO_ADC_PIN1_CH);
122 chselr |= (1 << AO_ADC_PIN2_CH);
125 chselr |= (1 << AO_ADC_PIN3_CH);
128 chselr |= (1 << AO_ADC_PIN4_CH);
131 chselr |= (1 << AO_ADC_PIN5_CH);
134 chselr |= (1 << AO_ADC_PIN6_CH);
137 chselr |= (1 << AO_ADC_PIN7_CH);
140 #error Need more ADC defines
142 stm_adc.chselr = chselr;
145 stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_2 << STM_ADC_CFGR2_CKMODE;
147 /* Shortest sample time */
148 stm_adc.smpr = STM_ADC_SMPR_SMP_1_5 << STM_ADC_SMPR_SMP;
151 stm_adc.cr |= (1 << STM_ADC_CR_ADCAL);
152 for (i = 0; i < 0xf000; i++) {
153 if ((stm_adc.cr & (1 << STM_ADC_CR_ADCAL)) == 0)
158 stm_adc.cr |= (1 << STM_ADC_CR_ADEN);
159 while ((stm_adc.isr & (1 << STM_ADC_ISR_ADRDY)) == 0)
162 stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) |
163 (0 << STM_ADC_CFGR1_AWDEN) |
164 (0 << STM_ADC_CFGR1_AWDSGL) |
165 (0 << STM_ADC_CFGR1_DISCEN) |
166 (0 << STM_ADC_CFGR1_AUTOOFF) |
167 (1 << STM_ADC_CFGR1_WAIT) |
168 (1 << STM_ADC_CFGR1_CONT) |
169 (0 << STM_ADC_CFGR1_OVRMOD) |
170 (STM_ADC_CFGR1_EXTEN_DISABLE << STM_ADC_CFGR1_EXTEN) |
171 (0 << STM_ADC_CFGR1_ALIGN) |
172 (STM_ADC_CFGR1_RES_12 << STM_ADC_CFGR1_RES) |
173 (STM_ADC_CFGR1_SCANDIR_UP << STM_ADC_CFGR1_SCANDIR) |
174 (STM_ADC_CFGR1_DMACFG_ONESHOT << STM_ADC_CFGR1_DMACFG) |
175 (1 << STM_ADC_CFGR1_DMAEN));
178 /* Clear any stale status bits */
182 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
184 /* Set ADC to use DMA channel 1 (option 1) */
185 stm_syscfg.cfgr1 &= ~(1 << STM_SYSCFG_CFGR1_ADC_DMA_RMP);
187 ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));