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   1 /*
   2  * Copyright © 2018 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include <ao.h>
  20 #include "stm32f4.h"
  21 #include <string.h>
  22 #include <ao_boot.h>
  23
  24 extern void main(void);
  25 extern char __stack__;
  26 extern char __text_start__, __text_end__;
  27 extern char _start__, _end__;
  28 extern char __bss_start__, __bss_end__;
  29
  30 /* Interrupt functions */
  31
  32 void stm_halt_isr(void)
  33 {
  34         ao_panic(AO_PANIC_CRASH);
  35 }
  36
  37 void stm_ignore_isr(void)
  38 {
  39 }
  40
  41 const void *stm_interrupt_vector[];
  42
  43 void start(void)
  44 {
  45 #ifdef AO_BOOT_CHAIN
  46         if (ao_boot_check_chain()) {
  47 #ifdef AO_BOOT_PIN
  48                 ao_boot_check_pin();
  49 #endif
  50         }
  51 #endif
  52         /* Enable FPU */
  53         stm_scb.cpacr |= ((STM_SCB_CPACR_FULL << STM_SCB_CPACR_FP0) |
  54                           (STM_SCB_CPACR_FULL << STM_SCB_CPACR_FP1));
  55         ao_arch_nop();
  56         /* Set interrupt vector table offset */
  57         stm_scb.vtor = (uint32_t) &stm_interrupt_vector;
  58         memcpy(&_start__, &__text_end__, &_end__ - &_start__);
  59         memset(&__bss_start__, '\0', &__bss_end__ - &__bss_start__);
  60         main();
  61 }
  62
  63 #define STRINGIFY(x) #x
  64
  65 #define isr(name) \
  66         void __attribute__ ((weak)) stm_ ## name ## _isr(void); \
  67         _Pragma(STRINGIFY(weak stm_ ## name ## _isr = stm_ignore_isr))
  68
  69 #define isr_halt(name) \
  70         void __attribute__ ((weak)) stm_ ## name ## _isr(void); \
  71         _Pragma(STRINGIFY(weak stm_ ## name ## _isr = stm_halt_isr))
  72
  73 isr(nmi)
  74 isr_halt(hardfault)
  75 isr_halt(memmanage)
  76 isr_halt(busfault)
  77 isr_halt(usagefault)
  78 isr(svc)
  79 isr(debugmon)
  80 isr(pendsv)
  81 isr(systick)
  82 isr(wwdg)
  83 isr(pvd)
  84 isr(tamper_stamp)
  85 isr(rtc_wkup)
  86 isr(flash)
  87 isr(rcc)
  88 isr(exti0)
  89 isr(exti1)
  90 isr(exti2)
  91 isr(exti3)
  92 isr(exti4)
  93 isr(dma1_stream0)
  94 isr(dma1_stream1)
  95 isr(dma1_stream2)
  96 isr(dma1_stream3)
  97 isr(dma1_stream4)
  98 isr(dma1_stream5)
  99 isr(dma1_stream6)
 100 isr(adc)
 101 isr(can1_tx)
 102 isr(can1_rx0)
 103 isr(can1_rx1)
 104 isr(can1_sce)
 105 isr(exti9_5)
 106 isr(tim1_brk_tim9)
 107 isr(tim1_up_tim10)
 108 isr(tim_trg_com_tim11)
 109 isr(tim1_cc)
 110 isr(tim2)
 111 isr(tim3)
 112 isr(tim4)
 113 isr(i2c1_evt)
 114 isr(i2c1_err)
 115 isr(i2c2_evt)
 116 isr(i2c2_err)
 117 isr(spi1)
 118 isr(spi2)
 119 isr(usart1)
 120 isr(usart2)
 121 isr(usart3)
 122 isr(exti15_10)
 123 isr(rtc_alarm)
 124 isr(otg_fs_wkup)
 125 isr(tim8_brk_tim12)
 126 isr(tim8_up_tim13)
 127 isr(tim8_trg_com_tim14)
 128 isr(tim8_cc)
 129 isr(dma1_stream7)
 130 isr(fsmc)
 131 isr(sdio)
 132 isr(tim5)
 133 isr(spi3)
 134 isr(uart4)
 135 isr(uart5)
 136 isr(tim6_glb_it)
 137 isr(tim7)
 138 isr(dma2_stream0)
 139 isr(dma2_stream1)
 140 isr(dma2_stream2)
 141 isr(dma2_stream3)
 142 isr(dma2_stream4)
 143 isr(dfsdm1_flt0)
 144 isr(dfsdm1_flt1)
 145 isr(can2_tx)
 146 isr(can2_rx0)
 147 isr(can2_rx1)
 148 isr(can2_sce)
 149 isr(otg_fs)
 150 isr(dma2_stream5)
 151 isr(dma2_stream6)
 152 isr(dma2_stream7)
 153 isr(usart6)
 154 isr(i2c3_ev)
 155 isr(i2c3_er)
 156 isr(can3_tx)
 157 isr(can3_rx0)
 158 isr(can3_rx1)
 159 isr(can3_sce)
 160 isr(crypto)
 161 isr(rng)
 162 isr(fpu)
 163 isr(uart7)
 164 isr(uart8)
 165 isr(spi4)
 166 isr(spi5)
 167 isr(sai1)
 168 isr(uart9)
 169 isr(uart10)
 170 isr(quad_spi)
 171 isr(i2cfmp1_ev)
 172 isr(i2cfmp1_er)
 173 isr(exti23)
 174 isr(dfsdm2_flt0)
 175 isr(dfsdm2_flt1)
 176 isr(dfsdm2_flt2)
 177 isr(dfsdm2_flt3)
 178
 179 #define i(addr,name)    [(addr)/4] = stm_ ## name ## _isr
 180
 181 __attribute__ ((section(".interrupt")))
 182 const void *stm_interrupt_vector[] = {
 183         [0] = &__stack__,
 184         [1] = start,
 185         i(0x08, nmi),
 186         i(0x0c, hardfault),
 187         i(0x10, memmanage),
 188         i(0x14, busfault),
 189         i(0x18, usagefault),
 190         i(0x2c, svc),
 191         i(0x30, debugmon),
 192         i(0x38, pendsv),
 193         i(0x3c, systick),
 194         i(0x40, wwdg),
 195         i(0x44, pvd),
 196         i(0x48, tamper_stamp),
 197         i(0x4c, rtc_wkup),
 198         i(0x50, flash),
 199         i(0x54, rcc),
 200         i(0x58, exti0),
 201         i(0x5c, exti1),
 202         i(0x60, exti2),
 203         i(0x64, exti3),
 204         i(0x68, exti4),
 205         i(0x6c, dma1_stream0),
 206         i(0x70, dma1_stream1),
 207         i(0x74, dma1_stream2),
 208         i(0x78, dma1_stream3),
 209         i(0x7c, dma1_stream4),
 210         i(0x80, dma1_stream5),
 211         i(0x84, dma1_stream6),
 212         i(0x88, adc),
 213         i(0x8c, can1_tx),
 214         i(0x90, can1_rx0),
 215         i(0x94, can1_rx1),
 216         i(0x98, can1_sce),
 217         i(0x9c, exti9_5),
 218         i(0xa0, tim1_brk_tim9),
 219         i(0xa4, tim1_up_tim10),
 220         i(0xa8, tim_trg_com_tim11),
 221         i(0xac, tim1_cc),
 222         i(0xb0, tim2),
 223         i(0xb4, tim3),
 224         i(0xb8, tim4),
 225         i(0xbc, i2c1_evt),
 226         i(0xc0, i2c1_err),
 227         i(0xc4, i2c2_evt),
 228         i(0xc8, i2c2_err),
 229         i(0xcc, spi1),
 230         i(0xd0, spi2),
 231         i(0xd4, usart1),
 232         i(0xd8, usart2),
 233         i(0xdc, usart3),
 234         i(0xe0, exti15_10),
 235         i(0xe4, rtc_alarm),
 236         i(0xe8, otg_fs_wkup),
 237         i(0xec, tim8_brk_tim12),
 238         i(0xf0, tim8_up_tim13),
 239         i(0xf4, tim8_trg_com_tim14),
 240         i(0xf8, tim8_cc),
 241         i(0xfc, dma1_stream7),
 242         i(0x100, fsmc),
 243         i(0x104, sdio),
 244         i(0x108, tim5),
 245         i(0x10c, spi3),
 246         i(0x110, uart4),
 247         i(0x114, uart5),
 248         i(0x118,tim6_glb_it),
 249         i(0x11c, tim7),
 250         i(0x120, dma2_stream0),
 251         i(0x124, dma2_stream1),
 252         i(0x128, dma2_stream2),
 253         i(0x12c, dma2_stream3),
 254         i(0x130, dma2_stream4),
 255         i(0x134, dfsdm1_flt0),
 256         i(0x138, dfsdm1_flt1),
 257         i(0x13c, can2_tx),
 258         i(0x140, can2_rx0),
 259         i(0x144, can2_rx1),
 260         i(0x148, can2_sce),
 261         i(0x14c, otg_fs),
 262         i(0x150, dma2_stream5),
 263         i(0x154, dma2_stream6),
 264         i(0x158, dma2_stream7),
 265         i(0x15c, usart6),
 266         i(0x160, i2c3_ev),
 267         i(0x164, i2c3_er),
 268         i(0x168, can3_tx),
 269         i(0x16c, can3_rx0),
 270         i(0x170, can3_rx1),
 271         i(0x174, can3_sce),
 272         i(0x17c, crypto),
 273         i(0x180, rng),
 274         i(0x184, fpu),
 275         i(0x188, uart7),
 276         i(0x18c, uart8),
 277         i(0x190, spi4),
 278         i(0x194, spi5),
 279         i(0x19c, sai1),
 280         i(0x1a0, uart9),
 281         i(0x1a4, uart10),
 282         i(0x1b0, quad_spi),
 283         i(0x1bc, i2cfmp1_ev),
 284         i(0x1c0, i2cfmp1_er),
 285         i(0x1c4, exti23),
 286         i(0x1c8, dfsdm2_flt0),
 287         i(0x1cc, dfsdm2_flt1),
 288         i(0x1d0, dfsdm2_flt2),
 289         i(0x1d4, dfsdm2_flt3),
 290 };