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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #ifndef _STM32L_H_
  20 #define _STM32L_H_
  21
  22 #include <stdint.h>
  23
  24 typedef volatile uint32_t       vuint32_t;
  25 typedef volatile void *         vvoid_t;
  26
  27 struct stm_gpio {
  28         vuint32_t       moder;
  29         vuint32_t       otyper;
  30         vuint32_t       ospeedr;
  31         vuint32_t       pupdr;
  32
  33         vuint32_t       idr;
  34         vuint32_t       odr;
  35         vuint32_t       bsrr;
  36         vuint32_t       lckr;
  37
  38         vuint32_t       afrl;
  39         vuint32_t       afrh;
  40 };
  41
  42 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  43 #define STM_MODER_MASK                  3
  44 #define STM_MODER_INPUT                 0
  45 #define STM_MODER_OUTPUT                1
  46 #define STM_MODER_ALTERNATE             2
  47 #define STM_MODER_ANALOG                3
  48
  49 static inline void
  50 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  51         gpio->moder = ((gpio->moder &
  52                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  53                        value << STM_MODER_SHIFT(pin));
  54 }
  55
  56 static inline uint32_t
  57 stm_spread_mask(uint16_t mask) {
  58         uint32_t m = mask;
  59
  60         /* 0000000000000000mmmmmmmmmmmmmmmm */
  61         m = (m & 0xff) | ((m & 0xff00) << 8);
  62         /* 00000000mmmmmmmm00000000mmmmmmmm */
  63         m = (m & 0x000f000f) | ((m & 0x00f000f0) << 4);
  64         /* 0000mmmm0000mmmm0000mmmm0000mmmm */
  65         m = (m & 0x03030303) | ((m & 0x0c0c0c0c) << 2);
  66         /* 00mm00mm00mm00mm00mm00mm00mm00mm */
  67         m = (m & 0x11111111) | ((m & 0x22222222) << 2);
  68         /* 0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m */
  69         return m;
  70 }
  71
  72 static inline void
  73 stm_moder_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
  74         uint32_t        bits32 = stm_spread_mask(mask);
  75         uint32_t        mask32 = 3 * bits32;
  76         uint32_t        value32 = (value & 3) * bits32;
  77
  78         gpio->moder = ((gpio->moder & ~mask32) | value32);
  79 }
  80
  81 static inline uint32_t
  82 stm_moder_get(struct stm_gpio *gpio, int pin) {
  83         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  84 }
  85
  86 #define STM_OTYPER_SHIFT(pin)           (pin)
  87 #define STM_OTYPER_MASK                 1
  88 #define STM_OTYPER_PUSH_PULL            0
  89 #define STM_OTYPER_OPEN_DRAIN           1
  90
  91 static inline void
  92 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  93         gpio->otyper = ((gpio->otyper &
  94                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  95                         value << STM_OTYPER_SHIFT(pin));
  96 }
  97
  98 static inline uint32_t
  99 stm_otyper_get(struct stm_gpio *gpio, int pin) {
 100         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
 101 }
 102
 103 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
 104 #define STM_OSPEEDR_MASK                3
 105 #define STM_OSPEEDR_400kHz              0
 106 #define STM_OSPEEDR_2MHz                1
 107 #define STM_OSPEEDR_10MHz               2
 108 #define STM_OSPEEDR_40MHz               3
 109
 110 static inline void
 111 stm_ospeedr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 112         gpio->ospeedr = ((gpio->ospeedr &
 113                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
 114                        value << STM_OSPEEDR_SHIFT(pin));
 115 }
 116
 117 static inline void
 118 stm_ospeedr_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
 119         uint32_t        bits32 = stm_spread_mask(mask);
 120         uint32_t        mask32 = 3 * bits32;
 121         uint32_t        value32 = (value & 3) * bits32;
 122
 123         gpio->ospeedr = ((gpio->ospeedr & ~mask32) | value32);
 124 }
 125
 126 static inline uint32_t
 127 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
 128         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
 129 }
 130
 131 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
 132 #define STM_PUPDR_MASK                  3
 133 #define STM_PUPDR_NONE                  0
 134 #define STM_PUPDR_PULL_UP               1
 135 #define STM_PUPDR_PULL_DOWN             2
 136 #define STM_PUPDR_RESERVED              3
 137
 138 static inline void
 139 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 140         gpio->pupdr = ((gpio->pupdr &
 141                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 142                        value << STM_PUPDR_SHIFT(pin));
 143 }
 144
 145 static inline void
 146 stm_pupdr_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
 147         uint32_t        bits32 = stm_spread_mask(mask);
 148         uint32_t        mask32 = 3 * bits32;
 149         uint32_t        value32 = (value & 3) * bits32;
 150
 151         gpio->pupdr = (gpio->pupdr & ~mask32) | value32;
 152 }
 153
 154 static inline uint32_t
 155 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 156         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 157 }
 158
 159 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 160 #define STM_AFR_MASK                    0xf
 161 #define STM_AFR_NONE                    0
 162 #define STM_AFR_AF0                     0x0
 163 #define STM_AFR_AF1                     0x1
 164 #define STM_AFR_AF2                     0x2
 165 #define STM_AFR_AF3                     0x3
 166 #define STM_AFR_AF4                     0x4
 167 #define STM_AFR_AF5                     0x5
 168 #define STM_AFR_AF6                     0x6
 169 #define STM_AFR_AF7                     0x7
 170 #define STM_AFR_AF8                     0x8
 171 #define STM_AFR_AF9                     0x9
 172 #define STM_AFR_AF10                    0xa
 173 #define STM_AFR_AF11                    0xb
 174 #define STM_AFR_AF12                    0xc
 175 #define STM_AFR_AF13                    0xd
 176 #define STM_AFR_AF14                    0xe
 177 #define STM_AFR_AF15                    0xf
 178
 179 static inline void
 180 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 181         /*
 182          * Set alternate pin mode too
 183          */
 184         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 185         if (pin < 8)
 186                 gpio->afrl = ((gpio->afrl &
 187                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 188                               value << STM_AFR_SHIFT(pin));
 189         else {
 190                 pin -= 8;
 191                 gpio->afrh = ((gpio->afrh &
 192                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 193                               value << STM_AFR_SHIFT(pin));
 194         }
 195 }
 196
 197 static inline uint32_t
 198 stm_afr_get(struct stm_gpio *gpio, int pin) {
 199         if (pin < 8)
 200                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 201         else {
 202                 pin -= 8;
 203                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 204         }
 205 }
 206
 207 static inline void
 208 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 209         /* Use the bit set/reset register to do this atomically */
 210         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 211 }
 212
 213 static inline void
 214 stm_gpio_set_mask(struct stm_gpio *gpio, uint16_t bits, uint16_t mask) {
 215         /* Use the bit set/reset register to do this atomically */
 216         gpio->bsrr = ((uint32_t) (~bits & mask) << 16) | ((uint32_t) (bits & mask));
 217 }
 218
 219 static inline void
 220 stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) {
 221         gpio->bsrr = bits;
 222 }
 223
 224 static inline void
 225 stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) {
 226         gpio->bsrr = ((uint32_t) bits) << 16;
 227 }
 228
 229 static inline uint8_t
 230 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 231         return (gpio->idr >> pin) & 1;
 232 }
 233
 234 static inline uint16_t
 235 stm_gpio_get_all(struct stm_gpio *gpio) {
 236         return gpio->idr;
 237 }
 238
 239 /*
 240  * We can't define these in registers.ld or our fancy
 241  * ao_enable_gpio macro will expand into a huge pile of code
 242  * as the compiler won't do correct constant folding and
 243  * dead-code elimination
 244  */
 245
 246 extern struct stm_gpio stm_gpioa;
 247 extern struct stm_gpio stm_gpiob;
 248 extern struct stm_gpio stm_gpioc;
 249 extern struct stm_gpio stm_gpiod;
 250 extern struct stm_gpio stm_gpioe;
 251 extern struct stm_gpio stm_gpioh;
 252
 253 #define stm_gpioh  (*((struct stm_gpio *) 0x40021400))
 254 #define stm_gpioe  (*((struct stm_gpio *) 0x40021000))
 255 #define stm_gpiod  (*((struct stm_gpio *) 0x40020c00))
 256 #define stm_gpioc  (*((struct stm_gpio *) 0x40020800))
 257 #define stm_gpiob  (*((struct stm_gpio *) 0x40020400))
 258 #define stm_gpioa  (*((struct stm_gpio *) 0x40020000))
 259
 260 struct stm_usart {
 261         vuint32_t       sr;     /* status register */
 262         vuint32_t       dr;     /* data register */
 263         vuint32_t       brr;    /* baud rate register */
 264         vuint32_t       cr1;    /* control register 1 */
 265
 266         vuint32_t       cr2;    /* control register 2 */
 267         vuint32_t       cr3;    /* control register 3 */
 268         vuint32_t       gtpr;   /* guard time and prescaler */
 269 };
 270
 271 extern struct stm_usart stm_usart1;
 272 extern struct stm_usart stm_usart2;
 273 extern struct stm_usart stm_usart3;
 274
 275 #define STM_USART_SR_CTS        (9)     /* CTS flag */
 276 #define STM_USART_SR_LBD        (8)     /* LIN break detection flag */
 277 #define STM_USART_SR_TXE        (7)     /* Transmit data register empty */
 278 #define STM_USART_SR_TC         (6)     /* Transmission complete */
 279 #define STM_USART_SR_RXNE       (5)     /* Read data register not empty */
 280 #define STM_USART_SR_IDLE       (4)     /* IDLE line detected */
 281 #define STM_USART_SR_ORE        (3)     /* Overrun error */
 282 #define STM_USART_SR_NF         (2)     /* Noise detected flag */
 283 #define STM_USART_SR_FE         (1)     /* Framing error */
 284 #define STM_USART_SR_PE         (0)     /* Parity error */
 285
 286 #define STM_USART_CR1_OVER8     (15)    /* Oversampling mode */
 287 #define STM_USART_CR1_UE        (13)    /* USART enable */
 288 #define STM_USART_CR1_M         (12)    /* Word length */
 289 #define STM_USART_CR1_WAKE      (11)    /* Wakeup method */
 290 #define STM_USART_CR1_PCE       (10)    /* Parity control enable */
 291 #define STM_USART_CR1_PS        (9)     /* Parity selection */
 292 #define STM_USART_CR1_PEIE      (8)     /* PE interrupt enable */
 293 #define STM_USART_CR1_TXEIE     (7)     /* TXE interrupt enable */
 294 #define STM_USART_CR1_TCIE      (6)     /* Transmission complete interrupt enable */
 295 #define STM_USART_CR1_RXNEIE    (5)     /* RXNE interrupt enable */
 296 #define STM_USART_CR1_IDLEIE    (4)     /* IDLE interrupt enable */
 297 #define STM_USART_CR1_TE        (3)     /* Transmitter enable */
 298 #define STM_USART_CR1_RE        (2)     /* Receiver enable */
 299 #define STM_USART_CR1_RWU       (1)     /* Receiver wakeup */
 300 #define STM_USART_CR1_SBK       (0)     /* Send break */
 301
 302 #define STM_USART_CR2_LINEN     (14)    /* LIN mode enable */
 303 #define STM_USART_CR2_STOP      (12)    /* STOP bits */
 304 #define STM_USART_CR2_STOP_MASK 3
 305 #define STM_USART_CR2_STOP_1    0
 306 #define STM_USART_CR2_STOP_0_5  1
 307 #define STM_USART_CR2_STOP_2    2
 308 #define STM_USART_CR2_STOP_1_5  3
 309
 310 #define STM_USART_CR2_CLKEN     (11)    /* Clock enable */
 311 #define STM_USART_CR2_CPOL      (10)    /* Clock polarity */
 312 #define STM_USART_CR2_CPHA      (9)     /* Clock phase */
 313 #define STM_USART_CR2_LBCL      (8)     /* Last bit clock pulse */
 314 #define STM_USART_CR2_LBDIE     (6)     /* LIN break detection interrupt enable */
 315 #define STM_USART_CR2_LBDL      (5)     /* lin break detection length */
 316 #define STM_USART_CR2_ADD       (0)
 317 #define STM_USART_CR2_ADD_MASK  0xf
 318
 319 #define STM_USART_CR3_ONEBITE   (11)    /* One sample bit method enable */
 320 #define STM_USART_CR3_CTSIE     (10)    /* CTS interrupt enable */
 321 #define STM_USART_CR3_CTSE      (9)     /* CTS enable */
 322 #define STM_USART_CR3_RTSE      (8)     /* RTS enable */
 323 #define STM_USART_CR3_DMAT      (7)     /* DMA enable transmitter */
 324 #define STM_USART_CR3_DMAR      (6)     /* DMA enable receiver */
 325 #define STM_USART_CR3_SCEN      (5)     /* Smartcard mode enable */
 326 #define STM_USART_CR3_NACK      (4)     /* Smartcard NACK enable */
 327 #define STM_USART_CR3_HDSEL     (3)     /* Half-duplex selection */
 328 #define STM_USART_CR3_IRLP      (2)     /* IrDA low-power */
 329 #define STM_USART_CR3_IREN      (1)     /* IrDA mode enable */
 330 #define STM_USART_CR3_EIE       (0)     /* Error interrupt enable */
 331
 332 struct stm_tim {
 333 };
 334
 335 extern struct stm_tim stm_tim9;
 336
 337 struct stm_tim1011 {
 338         vuint32_t       cr1;
 339         uint32_t        unused_4;
 340         vuint32_t       smcr;
 341         vuint32_t       dier;
 342         vuint32_t       sr;
 343         vuint32_t       egr;
 344         vuint32_t       ccmr1;
 345         uint32_t        unused_1c;
 346         vuint32_t       ccer;
 347         vuint32_t       cnt;
 348         vuint32_t       psc;
 349         vuint32_t       arr;
 350         uint32_t        unused_30;
 351         vuint32_t       ccr1;
 352         uint32_t        unused_38;
 353         uint32_t        unused_3c;
 354         uint32_t        unused_40;
 355         uint32_t        unused_44;
 356         uint32_t        unused_48;
 357         uint32_t        unused_4c;
 358         vuint32_t       or;
 359 };
 360
 361 extern struct stm_tim1011 stm_tim10;
 362 extern struct stm_tim1011 stm_tim11;
 363
 364 #define STM_TIM1011_CR1_CKD     8
 365 #define  STM_TIM1011_CR1_CKD_1          0
 366 #define  STM_TIM1011_CR1_CKD_2          1
 367 #define  STM_TIM1011_CR1_CKD_4          2
 368 #define  STM_TIM1011_CR1_CKD_MASK       3
 369 #define STM_TIM1011_CR1_ARPE    7
 370 #define STM_TIM1011_CR1_URS     2
 371 #define STM_TIM1011_CR1_UDIS    1
 372 #define STM_TIM1011_CR1_CEN     0
 373
 374 #define STM_TIM1011_SMCR_ETP    15
 375 #define STM_TIM1011_SMCR_ECE    14
 376 #define STM_TIM1011_SMCR_ETPS   12
 377 #define  STM_TIM1011_SMCR_ETPS_OFF      0
 378 #define  STM_TIM1011_SMCR_ETPS_2        1
 379 #define  STM_TIM1011_SMCR_ETPS_4        2
 380 #define  STM_TIM1011_SMCR_ETPS_8        3
 381 #define  STM_TIM1011_SMCR_ETPS_MASK     3
 382 #define STM_TIM1011_SMCR_ETF    8
 383 #define  STM_TIM1011_SMCR_ETF_NONE              0
 384 #define  STM_TIM1011_SMCR_ETF_CK_INT_2          1
 385 #define  STM_TIM1011_SMCR_ETF_CK_INT_4          2
 386 #define  STM_TIM1011_SMCR_ETF_CK_INT_8          3
 387 #define  STM_TIM1011_SMCR_ETF_DTS_2_6           4
 388 #define  STM_TIM1011_SMCR_ETF_DTS_2_8           5
 389 #define  STM_TIM1011_SMCR_ETF_DTS_4_6           6
 390 #define  STM_TIM1011_SMCR_ETF_DTS_4_8           7
 391 #define  STM_TIM1011_SMCR_ETF_DTS_8_6           8
 392 #define  STM_TIM1011_SMCR_ETF_DTS_8_8           9
 393 #define  STM_TIM1011_SMCR_ETF_DTS_16_5          10
 394 #define  STM_TIM1011_SMCR_ETF_DTS_16_6          11
 395 #define  STM_TIM1011_SMCR_ETF_DTS_16_8          12
 396 #define  STM_TIM1011_SMCR_ETF_DTS_32_5          13
 397 #define  STM_TIM1011_SMCR_ETF_DTS_32_6          14
 398 #define  STM_TIM1011_SMCR_ETF_DTS_32_8          15
 399 #define  STM_TIM1011_SMCR_ETF_MASK              15
 400
 401 #define STM_TIM1011_DIER_CC1E   1
 402 #define STM_TIM1011_DIER_UIE    0
 403
 404 #define STM_TIM1011_SR_CC1OF    9
 405 #define STM_TIM1011_SR_CC1IF    1
 406 #define STM_TIM1011_SR_UIF      0
 407
 408 #define STM_TIM1011_EGR_CC1G    1
 409 #define STM_TIM1011_EGR_UG      0
 410
 411 #define STM_TIM1011_CCMR1_OC1CE 7
 412 #define STM_TIM1011_CCMR1_OC1M  4
 413 #define  STM_TIM1011_CCMR1_OC1M_FROZEN                  0
 414 #define  STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH   1
 415 #define  STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
 416 #define  STM_TIM1011_CCMR1_OC1M_TOGGLE                  3
 417 #define  STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE          4
 418 #define  STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE            5
 419 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_1              6
 420 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_2              7
 421 #define  STM_TIM1011_CCMR1_OC1M_MASK                    7
 422 #define STM_TIM1011_CCMR1_OC1PE 3
 423 #define STM_TIM1011_CCMR1_OC1FE 2
 424 #define STM_TIM1011_CCMR1_CC1S  0
 425 #define  STM_TIM1011_CCMR1_CC1S_OUTPUT                  0
 426 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI1               1
 427 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI2               2
 428 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TRC               3
 429 #define  STM_TIM1011_CCMR1_CC1S_MASK                    3
 430
 431 #define  STM_TIM1011_CCMR1_IC1F_NONE            0
 432 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_2        1
 433 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_4        2
 434 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_8        3
 435 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_6         4
 436 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_8         5
 437 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_6         6
 438 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_8         7
 439 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_6         8
 440 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_8         9
 441 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_5        10
 442 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_6        11
 443 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_8        12
 444 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_5        13
 445 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_6        14
 446 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_8        15
 447 #define  STM_TIM1011_CCMR1_IC1F_MASK            15
 448 #define STM_TIM1011_CCMR1_IC1PSC        2
 449 #define  STM_TIM1011_CCMR1_IC1PSC_1             0
 450 #define  STM_TIM1011_CCMR1_IC1PSC_2             1
 451 #define  STM_TIM1011_CCMR1_IC1PSC_4             2
 452 #define  STM_TIM1011_CCMR1_IC1PSC_8             3
 453 #define  STM_TIM1011_CCMR1_IC1PSC_MASK          3
 454 #define STM_TIM1011_CCMR1_CC1S          0
 455
 456 #define STM_TIM1011_CCER_CC1NP          3
 457 #define STM_TIM1011_CCER_CC1P           1
 458 #define STM_TIM1011_CCER_CC1E           0
 459
 460 #define STM_TIM1011_OR_TI1_RMP_RI       3
 461 #define STM_TIM1011_ETR_RMP             2
 462 #define STM_TIM1011_TI1_RMP             0
 463 #define  STM_TIM1011_TI1_RMP_GPIO               0
 464 #define  STM_TIM1011_TI1_RMP_LSI                1
 465 #define  STM_TIM1011_TI1_RMP_LSE                2
 466 #define  STM_TIM1011_TI1_RMP_RTC                3
 467 #define  STM_TIM1011_TI1_RMP_MASK               3
 468
 469 /* Flash interface */
 470
 471 struct stm_flash {
 472         vuint32_t       acr;
 473         vuint32_t       pecr;
 474         vuint32_t       pdkeyr;
 475         vuint32_t       pekeyr;
 476
 477         vuint32_t       prgkeyr;
 478         vuint32_t       optkeyr;
 479         vuint32_t       sr;
 480         vuint32_t       obr;
 481
 482         vuint32_t       wrpr;
 483 };
 484
 485 extern struct stm_flash stm_flash;
 486
 487 #define STM_FLASH_ACR_RUN_PD    (4)
 488 #define STM_FLASH_ACR_SLEEP_PD  (3)
 489 #define STM_FLASH_ACR_ACC64     (2)
 490 #define STM_FLASH_ACR_PRFEN     (1)
 491 #define STM_FLASH_ACR_LATENCY   (0)
 492
 493 #define STM_FLASH_PECR_OBL_LAUNCH       18
 494 #define STM_FLASH_PECR_ERRIE            17
 495 #define STM_FLASH_PECR_EOPIE            16
 496 #define STM_FLASH_PECR_FPRG             10
 497 #define STM_FLASH_PECR_ERASE            9
 498 #define STM_FLASH_PECR_FTDW             8
 499 #define STM_FLASH_PECR_DATA             4
 500 #define STM_FLASH_PECR_PROG             3
 501 #define STM_FLASH_PECR_OPTLOCK          2
 502 #define STM_FLASH_PECR_PRGLOCK          1
 503 #define STM_FLASH_PECR_PELOCK           0
 504
 505 #define STM_FLASH_SR_OPTVERR            11
 506 #define STM_FLASH_SR_SIZERR             10
 507 #define STM_FLASH_SR_PGAERR             9
 508 #define STM_FLASH_SR_WRPERR             8
 509 #define STM_FLASH_SR_READY              3
 510 #define STM_FLASH_SR_ENDHV              2
 511 #define STM_FLASH_SR_EOP                1
 512 #define STM_FLASH_SR_BSY                0
 513
 514 #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
 515 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
 516
 517 #define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
 518 #define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
 519
 520 struct stm_rcc {
 521         vuint32_t       cr;
 522         vuint32_t       icscr;
 523         vuint32_t       cfgr;
 524         vuint32_t       cir;
 525
 526         vuint32_t       ahbrstr;
 527         vuint32_t       apb2rstr;
 528         vuint32_t       apb1rstr;
 529         vuint32_t       ahbenr;
 530
 531         vuint32_t       apb2enr;
 532         vuint32_t       apb1enr;
 533         vuint32_t       ahblenr;
 534         vuint32_t       apb2lpenr;
 535
 536         vuint32_t       apb1lpenr;
 537         vuint32_t       csr;
 538 };
 539
 540 extern struct stm_rcc stm_rcc;
 541
 542 /* Nominal high speed internal oscillator frequency is 16MHz */
 543 #define STM_HSI_FREQ            16000000
 544
 545 #define STM_RCC_CR_RTCPRE       (29)
 546 #define  STM_RCC_CR_RTCPRE_HSE_DIV_2    0
 547 #define  STM_RCC_CR_RTCPRE_HSE_DIV_4    1
 548 #define  STM_RCC_CR_RTCPRE_HSE_DIV_8    2
 549 #define  STM_RCC_CR_RTCPRE_HSE_DIV_16   3
 550 #define  STM_RCC_CR_RTCPRE_HSE_MASK     3
 551
 552 #define STM_RCC_CR_CSSON        (28)
 553 #define STM_RCC_CR_PLLRDY       (25)
 554 #define STM_RCC_CR_PLLON        (24)
 555 #define STM_RCC_CR_HSEBYP       (18)
 556 #define STM_RCC_CR_HSERDY       (17)
 557 #define STM_RCC_CR_HSEON        (16)
 558 #define STM_RCC_CR_MSIRDY       (9)
 559 #define STM_RCC_CR_MSION        (8)
 560 #define STM_RCC_CR_HSIRDY       (1)
 561 #define STM_RCC_CR_HSION        (0)
 562
 563 #define STM_RCC_CFGR_MCOPRE     (28)
 564 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 565 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 566 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 567 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 568 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 569 #define  STM_RCC_CFGR_MCOPRE_MASK       7
 570
 571 #define STM_RCC_CFGR_MCOSEL     (24)
 572 #define  STM_RCC_CFGR_MCOSEL_DISABLE    0
 573 #define  STM_RCC_CFGR_MCOSEL_SYSCLK     1
 574 #define  STM_RCC_CFGR_MCOSEL_HSI        2
 575 #define  STM_RCC_CFGR_MCOSEL_MSI        3
 576 #define  STM_RCC_CFGR_MCOSEL_HSE        4
 577 #define  STM_RCC_CFGR_MCOSEL_PLL        5
 578 #define  STM_RCC_CFGR_MCOSEL_LSI        6
 579 #define  STM_RCC_CFGR_MCOSEL_LSE        7
 580 #define  STM_RCC_CFGR_MCOSEL_MASK       7
 581
 582 #define STM_RCC_CFGR_PLLDIV     (22)
 583 #define  STM_RCC_CFGR_PLLDIV_2          1
 584 #define  STM_RCC_CFGR_PLLDIV_3          2
 585 #define  STM_RCC_CFGR_PLLDIV_4          3
 586 #define  STM_RCC_CFGR_PLLDIV_MASK       3
 587
 588 #define STM_RCC_CFGR_PLLMUL     (18)
 589 #define  STM_RCC_CFGR_PLLMUL_3          0
 590 #define  STM_RCC_CFGR_PLLMUL_4          1
 591 #define  STM_RCC_CFGR_PLLMUL_6          2
 592 #define  STM_RCC_CFGR_PLLMUL_8          3
 593 #define  STM_RCC_CFGR_PLLMUL_12         4
 594 #define  STM_RCC_CFGR_PLLMUL_16         5
 595 #define  STM_RCC_CFGR_PLLMUL_24         6
 596 #define  STM_RCC_CFGR_PLLMUL_32         7
 597 #define  STM_RCC_CFGR_PLLMUL_48         8
 598 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 599
 600 #define STM_RCC_CFGR_PLLSRC     (16)
 601
 602 #define STM_RCC_CFGR_PPRE2      (11)
 603 #define  STM_RCC_CFGR_PPRE2_DIV_1       0
 604 #define  STM_RCC_CFGR_PPRE2_DIV_2       4
 605 #define  STM_RCC_CFGR_PPRE2_DIV_4       5
 606 #define  STM_RCC_CFGR_PPRE2_DIV_8       6
 607 #define  STM_RCC_CFGR_PPRE2_DIV_16      7
 608 #define  STM_RCC_CFGR_PPRE2_MASK        7
 609
 610 #define STM_RCC_CFGR_PPRE1      (8)
 611 #define  STM_RCC_CFGR_PPRE1_DIV_1       0
 612 #define  STM_RCC_CFGR_PPRE1_DIV_2       4
 613 #define  STM_RCC_CFGR_PPRE1_DIV_4       5
 614 #define  STM_RCC_CFGR_PPRE1_DIV_8       6
 615 #define  STM_RCC_CFGR_PPRE1_DIV_16      7
 616 #define  STM_RCC_CFGR_PPRE1_MASK        7
 617
 618 #define STM_RCC_CFGR_HPRE       (4)
 619 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 620 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 621 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 622 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 623 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 624 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 625 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 626 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 627 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 628 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 629
 630 #define STM_RCC_CFGR_SWS        (2)
 631 #define  STM_RCC_CFGR_SWS_MSI           0
 632 #define  STM_RCC_CFGR_SWS_HSI           1
 633 #define  STM_RCC_CFGR_SWS_HSE           2
 634 #define  STM_RCC_CFGR_SWS_PLL           3
 635 #define  STM_RCC_CFGR_SWS_MASK          3
 636
 637 #define STM_RCC_CFGR_SW         (0)
 638 #define  STM_RCC_CFGR_SW_MSI            0
 639 #define  STM_RCC_CFGR_SW_HSI            1
 640 #define  STM_RCC_CFGR_SW_HSE            2
 641 #define  STM_RCC_CFGR_SW_PLL            3
 642 #define  STM_RCC_CFGR_SW_MASK           3
 643
 644 #define STM_RCC_AHBENR_DMA1EN           (24)
 645 #define STM_RCC_AHBENR_FLITFEN          (15)
 646 #define STM_RCC_AHBENR_CRCEN            (12)
 647 #define STM_RCC_AHBENR_GPIOHEN          (5)
 648 #define STM_RCC_AHBENR_GPIOEEN          (4)
 649 #define STM_RCC_AHBENR_GPIODEN          (3)
 650 #define STM_RCC_AHBENR_GPIOCEN          (2)
 651 #define STM_RCC_AHBENR_GPIOBEN          (1)
 652 #define STM_RCC_AHBENR_GPIOAEN          (0)
 653
 654 #define STM_RCC_APB2ENR_USART1EN        (14)
 655 #define STM_RCC_APB2ENR_SPI1EN          (12)
 656 #define STM_RCC_APB2ENR_ADC1EN          (9)
 657 #define STM_RCC_APB2ENR_TIM11EN         (4)
 658 #define STM_RCC_APB2ENR_TIM10EN         (3)
 659 #define STM_RCC_APB2ENR_TIM9EN          (2)
 660 #define STM_RCC_APB2ENR_SYSCFGEN        (0)
 661
 662 #define STM_RCC_APB1ENR_COMPEN          (31)
 663 #define STM_RCC_APB1ENR_DACEN           (29)
 664 #define STM_RCC_APB1ENR_PWREN           (28)
 665 #define STM_RCC_APB1ENR_USBEN           (23)
 666 #define STM_RCC_APB1ENR_I2C2EN          (22)
 667 #define STM_RCC_APB1ENR_I2C1EN          (21)
 668 #define STM_RCC_APB1ENR_USART3EN        (18)
 669 #define STM_RCC_APB1ENR_USART2EN        (17)
 670 #define STM_RCC_APB1ENR_SPI2EN          (14)
 671 #define STM_RCC_APB1ENR_WWDGEN          (11)
 672 #define STM_RCC_APB1ENR_LCDEN           (9)
 673 #define STM_RCC_APB1ENR_TIM7EN          (5)
 674 #define STM_RCC_APB1ENR_TIM6EN          (4)
 675 #define STM_RCC_APB1ENR_TIM4EN          (2)
 676 #define STM_RCC_APB1ENR_TIM3EN          (1)
 677 #define STM_RCC_APB1ENR_TIM2EN          (0)
 678
 679 #define STM_RCC_CSR_LPWRRSTF            (31)
 680 #define STM_RCC_CSR_WWDGRSTF            (30)
 681 #define STM_RCC_CSR_IWDGRSTF            (29)
 682 #define STM_RCC_CSR_SFTRSTF             (28)
 683 #define STM_RCC_CSR_PORRSTF             (27)
 684 #define STM_RCC_CSR_PINRSTF             (26)
 685 #define STM_RCC_CSR_OBLRSTF             (25)
 686 #define STM_RCC_CSR_RMVF                (24)
 687 #define STM_RCC_CSR_RTFRST              (23)
 688 #define STM_RCC_CSR_RTCEN               (22)
 689 #define STM_RCC_CSR_RTCSEL              (16)
 690
 691 #define  STM_RCC_CSR_RTCSEL_NONE                0
 692 #define  STM_RCC_CSR_RTCSEL_LSE                 1
 693 #define  STM_RCC_CSR_RTCSEL_LSI                 2
 694 #define  STM_RCC_CSR_RTCSEL_HSE                 3
 695 #define  STM_RCC_CSR_RTCSEL_MASK                3
 696
 697 #define STM_RCC_CSR_LSEBYP              (10)
 698 #define STM_RCC_CSR_LSERDY              (9)
 699 #define STM_RCC_CSR_LSEON               (8)
 700 #define STM_RCC_CSR_LSIRDY              (1)
 701 #define STM_RCC_CSR_LSION               (0)
 702
 703 struct stm_pwr {
 704         vuint32_t       cr;
 705         vuint32_t       csr;
 706 };
 707
 708 extern struct stm_pwr stm_pwr;
 709
 710 #define STM_PWR_CR_LPRUN        (14)
 711
 712 #define STM_PWR_CR_VOS          (11)
 713 #define  STM_PWR_CR_VOS_1_8             1
 714 #define  STM_PWR_CR_VOS_1_5             2
 715 #define  STM_PWR_CR_VOS_1_2             3
 716 #define  STM_PWR_CR_VOS_MASK            3
 717
 718 #define STM_PWR_CR_FWU          (10)
 719 #define STM_PWR_CR_ULP          (9)
 720 #define STM_PWR_CR_DBP          (8)
 721
 722 #define STM_PWR_CR_PLS          (5)
 723 #define  STM_PWR_CR_PLS_1_9     0
 724 #define  STM_PWR_CR_PLS_2_1     1
 725 #define  STM_PWR_CR_PLS_2_3     2
 726 #define  STM_PWR_CR_PLS_2_5     3
 727 #define  STM_PWR_CR_PLS_2_7     4
 728 #define  STM_PWR_CR_PLS_2_9     5
 729 #define  STM_PWR_CR_PLS_3_1     6
 730 #define  STM_PWR_CR_PLS_EXT     7
 731 #define  STM_PWR_CR_PLS_MASK    7
 732
 733 #define STM_PWR_CR_PVDE         (4)
 734 #define STM_PWR_CR_CSBF         (3)
 735 #define STM_PWR_CR_CWUF         (2)
 736 #define STM_PWR_CR_PDDS         (1)
 737 #define STM_PWR_CR_LPSDSR       (0)
 738
 739 #define STM_PWR_CSR_EWUP3       (10)
 740 #define STM_PWR_CSR_EWUP2       (9)
 741 #define STM_PWR_CSR_EWUP1       (8)
 742 #define STM_PWR_CSR_REGLPF      (5)
 743 #define STM_PWR_CSR_VOSF        (4)
 744 #define STM_PWR_CSR_VREFINTRDYF (3)
 745 #define STM_PWR_CSR_PVDO        (2)
 746 #define STM_PWR_CSR_SBF         (1)
 747 #define STM_PWR_CSR_WUF         (0)
 748
 749 struct stm_tim67 {
 750         vuint32_t       cr1;
 751         vuint32_t       cr2;
 752         uint32_t        _unused_08;
 753         vuint32_t       dier;
 754
 755         vuint32_t       sr;
 756         vuint32_t       egr;
 757         uint32_t        _unused_18;
 758         uint32_t        _unused_1c;
 759
 760         uint32_t        _unused_20;
 761         vuint32_t       cnt;
 762         vuint32_t       psc;
 763         vuint32_t       arr;
 764 };
 765
 766 extern struct stm_tim67 stm_tim6;
 767
 768 #define STM_TIM67_CR1_ARPE      (7)
 769 #define STM_TIM67_CR1_OPM       (3)
 770 #define STM_TIM67_CR1_URS       (2)
 771 #define STM_TIM67_CR1_UDIS      (1)
 772 #define STM_TIM67_CR1_CEN       (0)
 773
 774 #define STM_TIM67_CR2_MMS       (4)
 775 #define  STM_TIM67_CR2_MMS_RESET        0
 776 #define  STM_TIM67_CR2_MMS_ENABLE       1
 777 #define  STM_TIM67_CR2_MMS_UPDATE       2
 778 #define  STM_TIM67_CR2_MMS_MASK         7
 779
 780 #define STM_TIM67_DIER_UDE      (8)
 781 #define STM_TIM67_DIER_UIE      (0)
 782
 783 #define STM_TIM67_SR_UIF        (0)
 784
 785 #define STM_TIM67_EGR_UG        (0)
 786
 787 struct stm_lcd {
 788         vuint32_t       cr;
 789         vuint32_t       fcr;
 790         vuint32_t       sr;
 791         vuint32_t       clr;
 792         uint32_t        unused_0x10;
 793         vuint32_t       ram[8*2];
 794 };
 795
 796 extern struct stm_lcd stm_lcd;
 797
 798 #define STM_LCD_CR_MUX_SEG              (7)
 799
 800 #define STM_LCD_CR_BIAS                 (5)
 801 #define  STM_LCD_CR_BIAS_1_4            0
 802 #define  STM_LCD_CR_BIAS_1_2            1
 803 #define  STM_LCD_CR_BIAS_1_3            2
 804 #define  STM_LCD_CR_BIAS_MASK           3
 805
 806 #define STM_LCD_CR_DUTY                 (2)
 807 #define  STM_LCD_CR_DUTY_STATIC         0
 808 #define  STM_LCD_CR_DUTY_1_2            1
 809 #define  STM_LCD_CR_DUTY_1_3            2
 810 #define  STM_LCD_CR_DUTY_1_4            3
 811 #define  STM_LCD_CR_DUTY_1_8            4
 812 #define  STM_LCD_CR_DUTY_MASK           7
 813
 814 #define STM_LCD_CR_VSEL                 (1)
 815 #define STM_LCD_CR_LCDEN                (0)
 816
 817 #define STM_LCD_FCR_PS                  (22)
 818 #define  STM_LCD_FCR_PS_1               0x0
 819 #define  STM_LCD_FCR_PS_2               0x1
 820 #define  STM_LCD_FCR_PS_4               0x2
 821 #define  STM_LCD_FCR_PS_8               0x3
 822 #define  STM_LCD_FCR_PS_16              0x4
 823 #define  STM_LCD_FCR_PS_32              0x5
 824 #define  STM_LCD_FCR_PS_64              0x6
 825 #define  STM_LCD_FCR_PS_128             0x7
 826 #define  STM_LCD_FCR_PS_256             0x8
 827 #define  STM_LCD_FCR_PS_512             0x9
 828 #define  STM_LCD_FCR_PS_1024            0xa
 829 #define  STM_LCD_FCR_PS_2048            0xb
 830 #define  STM_LCD_FCR_PS_4096            0xc
 831 #define  STM_LCD_FCR_PS_8192            0xd
 832 #define  STM_LCD_FCR_PS_16384           0xe
 833 #define  STM_LCD_FCR_PS_32768           0xf
 834 #define  STM_LCD_FCR_PS_MASK            0xf
 835
 836 #define STM_LCD_FCR_DIV                 (18)
 837 #define STM_LCD_FCR_DIV_16              0x0
 838 #define STM_LCD_FCR_DIV_17              0x1
 839 #define STM_LCD_FCR_DIV_18              0x2
 840 #define STM_LCD_FCR_DIV_19              0x3
 841 #define STM_LCD_FCR_DIV_20              0x4
 842 #define STM_LCD_FCR_DIV_21              0x5
 843 #define STM_LCD_FCR_DIV_22              0x6
 844 #define STM_LCD_FCR_DIV_23              0x7
 845 #define STM_LCD_FCR_DIV_24              0x8
 846 #define STM_LCD_FCR_DIV_25              0x9
 847 #define STM_LCD_FCR_DIV_26              0xa
 848 #define STM_LCD_FCR_DIV_27              0xb
 849 #define STM_LCD_FCR_DIV_28              0xc
 850 #define STM_LCD_FCR_DIV_29              0xd
 851 #define STM_LCD_FCR_DIV_30              0xe
 852 #define STM_LCD_FCR_DIV_31              0xf
 853 #define STM_LCD_FCR_DIV_MASK            0xf
 854
 855 #define STM_LCD_FCR_BLINK               (16)
 856 #define  STM_LCD_FCR_BLINK_DISABLE              0
 857 #define  STM_LCD_FCR_BLINK_SEG0_COM0            1
 858 #define  STM_LCD_FCR_BLINK_SEG0_COMALL          2
 859 #define  STM_LCD_FCR_BLINK_SEGALL_COMALL        3
 860 #define  STM_LCD_FCR_BLINK_MASK                 3
 861
 862 #define STM_LCD_FCR_BLINKF              (13)
 863 #define  STM_LCD_FCR_BLINKF_8                   0
 864 #define  STM_LCD_FCR_BLINKF_16                  1
 865 #define  STM_LCD_FCR_BLINKF_32                  2
 866 #define  STM_LCD_FCR_BLINKF_64                  3
 867 #define  STM_LCD_FCR_BLINKF_128                 4
 868 #define  STM_LCD_FCR_BLINKF_256                 5
 869 #define  STM_LCD_FCR_BLINKF_512                 6
 870 #define  STM_LCD_FCR_BLINKF_1024                7
 871 #define  STM_LCD_FCR_BLINKF_MASK                7
 872
 873 #define STM_LCD_FCR_CC                  (10)
 874 #define  STM_LCD_FCR_CC_MASK                    7
 875
 876 #define STM_LCD_FCR_DEAD                (7)
 877 #define  STM_LCD_FCR_DEAD_MASK                  7
 878
 879 #define STM_LCD_FCR_PON                 (4)
 880 #define  STM_LCD_FCR_PON_MASK                   7
 881
 882 #define STM_LCD_FCR_UDDIE               (3)
 883 #define STM_LCD_FCR_SOFIE               (1)
 884 #define STM_LCD_FCR_HD                  (0)
 885
 886 #define STM_LCD_SR_FCRSF                (5)
 887 #define STM_LCD_SR_RDY                  (4)
 888 #define STM_LCD_SR_UDD                  (3)
 889 #define STM_LCD_SR_UDR                  (2)
 890 #define STM_LCD_SR_SOF                  (1)
 891 #define STM_LCD_SR_ENS                  (0)
 892
 893 #define STM_LCD_CLR_UDDC                (3)
 894 #define STM_LCD_CLR_SOFC                (1)
 895
 896 /* The SYSTICK starts at 0xe000e010 */
 897
 898 struct stm_systick {
 899         vuint32_t       csr;
 900         vuint32_t       rvr;
 901         vuint32_t       cvr;
 902         vuint32_t       calib;
 903 };
 904
 905 extern struct stm_systick stm_systick;
 906
 907 #define STM_SYSTICK_CSR_ENABLE          0
 908 #define STM_SYSTICK_CSR_TICKINT         1
 909 #define STM_SYSTICK_CSR_CLKSOURCE       2
 910 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               0
 911 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK                 1
 912 #define STM_SYSTICK_CSR_COUNTFLAG       16
 913
 914 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 915
 916 struct stm_nvic {
 917         vuint32_t       iser[8];        /* 0x000 0xe000e100 Set Enable Register */
 918
 919         uint8_t         _unused020[0x080 - 0x020];
 920
 921         vuint32_t       icer[8];        /* 0x080 0xe000e180 Clear Enable Register */
 922
 923         uint8_t         _unused0a0[0x100 - 0x0a0];
 924
 925         vuint32_t       ispr[8];        /* 0x100 0xe000e200 Set Pending Register */
 926
 927         uint8_t         _unused120[0x180 - 0x120];
 928
 929         vuint32_t       icpr[8];        /* 0x180 0xe000e280 Clear Pending Register */
 930
 931         uint8_t         _unused1a0[0x200 - 0x1a0];
 932
 933         vuint32_t       iabr[8];        /* 0x200 0xe000e300 Active Bit Register */
 934
 935         uint8_t         _unused220[0x300 - 0x220];
 936
 937         vuint32_t       ipr[60];        /* 0x300 0xe000e400 Priority Register */
 938
 939         uint8_t         _unused3f0[0xc00 - 0x3f0];
 940
 941         vuint32_t       cpuid_base;     /* 0xc00 0xe000ed00 CPUID Base Register */
 942         vuint32_t       ics;            /* 0xc04 0xe000ed04 Interrupt Control State Register */
 943         vuint32_t       vto;            /* 0xc08 0xe000ed08 Vector Table Offset Register */
 944         vuint32_t       ai_rc;          /* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */
 945         vuint32_t       sc;             /* 0xc10 0xe000ed10 System Control Register */
 946         vuint32_t       cc;             /* 0xc14 0xe000ed14 Configuration Control Register */
 947
 948         vuint32_t       shpr7_4;        /* 0xc18 0xe000ed18 System Hander Priority Registers */
 949         vuint32_t       shpr11_8;       /* 0xc1c */
 950         vuint32_t       shpr15_12;      /* 0xc20 */
 951
 952         uint8_t         _unusedc18[0xe00 - 0xc24];
 953
 954         vuint32_t       stir;           /* 0xe00 */
 955 };
 956
 957 extern struct stm_nvic stm_nvic;
 958
 959 #define IRQ_REG(irq)    ((irq) >> 5)
 960 #define IRQ_BIT(irq)    ((irq) & 0x1f)
 961 #define IRQ_MASK(irq)   (1 << IRQ_BIT(irq))
 962 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
 963
 964 static inline void
 965 stm_nvic_set_enable(int irq) {
 966         stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
 967 }
 968
 969 static inline void
 970 stm_nvic_clear_enable(int irq) {
 971         stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
 972 }
 973
 974 static inline int
 975 stm_nvic_enabled(int irq) {
 976         return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
 977 }
 978
 979 static inline void
 980 stm_nvic_set_pending(int irq) {
 981         stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
 982 }
 983
 984 static inline void
 985 stm_nvic_clear_pending(int irq) {
 986         stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
 987 }
 988
 989 static inline int
 990 stm_nvic_pending(int irq) {
 991         return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
 992 }
 993
 994 static inline int
 995 stm_nvic_active(int irq) {
 996         return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
 997 }
 998
 999 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
1000 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
1001 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
1002
1003 static inline void
1004 stm_nvic_set_priority(int irq, uint8_t prio) {
1005         int             n = IRQ_PRIO_REG(irq);
1006         uint32_t        v;
1007
1008         v = stm_nvic.ipr[n];
1009         v &= ~IRQ_PRIO_MASK(irq);
1010         v |= (prio) << IRQ_PRIO_BIT(irq);
1011         stm_nvic.ipr[n] = v;
1012 }
1013
1014 static inline uint8_t
1015 stm_nvic_get_priority(int irq) {
1016         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
1017 }
1018
1019 struct stm_scb {
1020         vuint32_t       cpuid;
1021         vuint32_t       icsr;
1022         vuint32_t       vtor;
1023         vuint32_t       aircr;
1024
1025         vuint32_t       scr;
1026         vuint32_t       ccr;
1027         vuint32_t       shpr1;
1028         vuint32_t       shpr2;
1029
1030         vuint32_t       shpr3;
1031         vuint32_t       shcrs;
1032         vuint32_t       cfsr;
1033         vuint32_t       hfsr;
1034
1035         uint32_t        unused_30;
1036         vuint32_t       mmfar;
1037         vuint32_t       bfar;
1038 };
1039
1040 extern struct stm_scb stm_scb;
1041
1042 #define STM_SCB_AIRCR_VECTKEY           16
1043 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
1044 #define STM_SCB_AIRCR_PRIGROUP          8
1045 #define STM_SCB_AIRCR_SYSRESETREQ       2
1046 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
1047 #define STM_SCB_AIRCR_VECTRESET         0
1048
1049 struct stm_mpu {
1050         vuint32_t       typer;
1051         vuint32_t       cr;
1052         vuint32_t       rnr;
1053         vuint32_t       rbar;
1054
1055         vuint32_t       rasr;
1056         vuint32_t       rbar_a1;
1057         vuint32_t       rasr_a1;
1058         vuint32_t       rbar_a2;
1059         vuint32_t       rasr_a2;
1060         vuint32_t       rbar_a3;
1061         vuint32_t       rasr_a3;
1062 };
1063
1064 extern struct stm_mpu stm_mpu;
1065
1066 #define STM_MPU_TYPER_IREGION   16
1067 #define  STM_MPU_TYPER_IREGION_MASK     0xff
1068 #define STM_MPU_TYPER_DREGION   8
1069 #define  STM_MPU_TYPER_DREGION_MASK     0xff
1070 #define STM_MPU_TYPER_SEPARATE  0
1071
1072 #define STM_MPU_CR_PRIVDEFENA   2
1073 #define STM_MPU_CR_HFNMIENA     1
1074 #define STM_MPU_CR_ENABLE       0
1075
1076 #define STM_MPU_RNR_REGION      0
1077 #define STM_MPU_RNR_REGION_MASK         0xff
1078
1079 #define STM_MPU_RBAR_ADDR       5
1080 #define STM_MPU_RBAR_ADDR_MASK          0x7ffffff
1081
1082 #define STM_MPU_RBAR_VALID      4
1083 #define STM_MPU_RBAR_REGION     0
1084 #define STM_MPU_RBAR_REGION_MASK        0xf
1085
1086 #define STM_MPU_RASR_XN         28
1087 #define STM_MPU_RASR_AP         24
1088 #define  STM_MPU_RASR_AP_NONE_NONE      0
1089 #define  STM_MPU_RASR_AP_RW_NONE        1
1090 #define  STM_MPU_RASR_AP_RW_RO          2
1091 #define  STM_MPU_RASR_AP_RW_RW          3
1092 #define  STM_MPU_RASR_AP_RO_NONE        5
1093 #define  STM_MPU_RASR_AP_RO_RO          6
1094 #define  STM_MPU_RASR_AP_MASK           7
1095 #define STM_MPU_RASR_TEX        19
1096 #define  STM_MPU_RASR_TEX_MASK          7
1097 #define STM_MPU_RASR_S          18
1098 #define STM_MPU_RASR_C          17
1099 #define STM_MPU_RASR_B          16
1100 #define STM_MPU_RASR_SRD        8
1101 #define  STM_MPU_RASR_SRD_MASK          0xff
1102 #define STM_MPU_RASR_SIZE       1
1103 #define  STM_MPU_RASR_SIZE_MASK         0x1f
1104 #define STM_MPU_RASR_ENABLE     0
1105
1106 #define isr_decl(name) void stm_ ## name ## _isr(void)
1107
1108 isr_decl(halt);
1109 isr_decl(ignore);
1110
1111 isr_decl(nmi);
1112 isr_decl(hardfault);
1113 isr_decl(memmanage);
1114 isr_decl(busfault);
1115 isr_decl(usagefault);
1116 isr_decl(svc);
1117 isr_decl(debugmon);
1118 isr_decl(pendsv);
1119 isr_decl(systick);
1120 isr_decl(wwdg);
1121 isr_decl(pvd);
1122 isr_decl(tamper_stamp);
1123 isr_decl(rtc_wkup);
1124 isr_decl(flash);
1125 isr_decl(rcc);
1126 isr_decl(exti0);
1127 isr_decl(exti1);
1128 isr_decl(exti2);
1129 isr_decl(exti3);
1130 isr_decl(exti4);
1131 isr_decl(dma1_channel1);
1132 isr_decl(dma1_channel2);
1133 isr_decl(dma1_channel3);
1134 isr_decl(dma1_channel4);
1135 isr_decl(dma1_channel5);
1136 isr_decl(dma1_channel6);
1137 isr_decl(dma1_channel7);
1138 isr_decl(adc1);
1139 isr_decl(usb_hp);
1140 isr_decl(usb_lp);
1141 isr_decl(dac);
1142 isr_decl(comp);
1143 isr_decl(exti9_5);
1144 isr_decl(lcd);
1145 isr_decl(tim9);
1146 isr_decl(tim10);
1147 isr_decl(tim11);
1148 isr_decl(tim2);
1149 isr_decl(tim3);
1150 isr_decl(tim4);
1151 isr_decl(i2c1_ev);
1152 isr_decl(i2c1_er);
1153 isr_decl(i2c2_ev);
1154 isr_decl(i2c2_er);
1155 isr_decl(spi1);
1156 isr_decl(spi2);
1157 isr_decl(usart1);
1158 isr_decl(usart2);
1159 isr_decl(usart3);
1160 isr_decl(exti15_10);
1161 isr_decl(rtc_alarm);
1162 isr_decl(usb_fs_wkup);
1163 isr_decl(tim6);
1164 isr_decl(tim7);
1165
1166 #undef isr_decl
1167
1168 #define STM_ISR_WWDG_POS                0
1169 #define STM_ISR_PVD_POS                 1
1170 #define STM_ISR_TAMPER_STAMP_POS        2
1171 #define STM_ISR_RTC_WKUP_POS            3
1172 #define STM_ISR_FLASH_POS               4
1173 #define STM_ISR_RCC_POS                 5
1174 #define STM_ISR_EXTI0_POS               6
1175 #define STM_ISR_EXTI1_POS               7
1176 #define STM_ISR_EXTI2_POS               8
1177 #define STM_ISR_EXTI3_POS               9
1178 #define STM_ISR_EXTI4_POS               10
1179 #define STM_ISR_DMA1_CHANNEL1_POS       11
1180 #define STM_ISR_DMA2_CHANNEL1_POS       12
1181 #define STM_ISR_DMA3_CHANNEL1_POS       13
1182 #define STM_ISR_DMA4_CHANNEL1_POS       14
1183 #define STM_ISR_DMA5_CHANNEL1_POS       15
1184 #define STM_ISR_DMA6_CHANNEL1_POS       16
1185 #define STM_ISR_DMA7_CHANNEL1_POS       17
1186 #define STM_ISR_ADC1_POS                18
1187 #define STM_ISR_USB_HP_POS              19
1188 #define STM_ISR_USB_LP_POS              20
1189 #define STM_ISR_DAC_POS                 21
1190 #define STM_ISR_COMP_POS                22
1191 #define STM_ISR_EXTI9_5_POS             23
1192 #define STM_ISR_LCD_POS                 24
1193 #define STM_ISR_TIM9_POS                25
1194 #define STM_ISR_TIM10_POS               26
1195 #define STM_ISR_TIM11_POS               27
1196 #define STM_ISR_TIM2_POS                28
1197 #define STM_ISR_TIM3_POS                29
1198 #define STM_ISR_TIM4_POS                30
1199 #define STM_ISR_I2C1_EV_POS             31
1200 #define STM_ISR_I2C1_ER_POS             32
1201 #define STM_ISR_I2C2_EV_POS             33
1202 #define STM_ISR_I2C2_ER_POS             34
1203 #define STM_ISR_SPI1_POS                35
1204 #define STM_ISR_SPI2_POS                36
1205 #define STM_ISR_USART1_POS              37
1206 #define STM_ISR_USART2_POS              38
1207 #define STM_ISR_USART3_POS              39
1208 #define STM_ISR_EXTI15_10_POS           40
1209 #define STM_ISR_RTC_ALARM_POS           41
1210 #define STM_ISR_USB_FS_WKUP_POS         42
1211 #define STM_ISR_TIM6_POS                43
1212 #define STM_ISR_TIM7_POS                44
1213
1214 struct stm_syscfg {
1215         vuint32_t       memrmp;
1216         vuint32_t       pmc;
1217         vuint32_t       exticr[4];
1218 };
1219
1220 extern struct stm_syscfg stm_syscfg;
1221
1222 #define STM_SYSCFG_MEMRMP_MEM_MODE      0
1223 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH          0
1224 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH        1
1225 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SRAM                3
1226 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MASK                3
1227
1228 #define STM_SYSCFG_PMC_USB_PU           0
1229
1230 #define STM_SYSCFG_EXTICR_PA            0
1231 #define STM_SYSCFG_EXTICR_PB            1
1232 #define STM_SYSCFG_EXTICR_PC            2
1233 #define STM_SYSCFG_EXTICR_PD            3
1234 #define STM_SYSCFG_EXTICR_PE            4
1235 #define STM_SYSCFG_EXTICR_PH            5
1236
1237 static inline void
1238 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1239         uint8_t reg = pin >> 2;
1240         uint8_t shift = (pin & 3) << 2;
1241         uint8_t val = 0;
1242
1243         /* Enable SYSCFG */
1244         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
1245
1246         if (gpio == &stm_gpioa)
1247                 val = STM_SYSCFG_EXTICR_PA;
1248         else if (gpio == &stm_gpiob)
1249                 val = STM_SYSCFG_EXTICR_PB;
1250         else if (gpio == &stm_gpioc)
1251                 val = STM_SYSCFG_EXTICR_PC;
1252         else if (gpio == &stm_gpiod)
1253                 val = STM_SYSCFG_EXTICR_PD;
1254         else if (gpio == &stm_gpioe)
1255                 val = STM_SYSCFG_EXTICR_PE;
1256
1257         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
1258 }
1259
1260
1261 struct stm_dma_channel {
1262         vuint32_t       ccr;
1263         vuint32_t       cndtr;
1264         vvoid_t         cpar;
1265         vvoid_t         cmar;
1266         vuint32_t       reserved;
1267 };
1268
1269 #define STM_NUM_DMA     7
1270
1271 struct stm_dma {
1272         vuint32_t               isr;
1273         vuint32_t               ifcr;
1274         struct stm_dma_channel  channel[STM_NUM_DMA];
1275 };
1276
1277 extern struct stm_dma stm_dma;
1278
1279 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
1280  */
1281
1282 #define STM_DMA_INDEX(channel)          ((channel) - 1)
1283
1284 #define STM_DMA_ISR(index)              ((index) << 2)
1285 #define STM_DMA_ISR_MASK                        0xf
1286 #define STM_DMA_ISR_TEIF                        3
1287 #define STM_DMA_ISR_HTIF                        2
1288 #define STM_DMA_ISR_TCIF                        1
1289 #define STM_DMA_ISR_GIF                         0
1290
1291 #define STM_DMA_IFCR(index)             ((index) << 2)
1292 #define STM_DMA_IFCR_MASK                       0xf
1293 #define STM_DMA_IFCR_CTEIF                      3
1294 #define STM_DMA_IFCR_CHTIF                      2
1295 #define STM_DMA_IFCR_CTCIF                      1
1296 #define STM_DMA_IFCR_CGIF                       0
1297
1298 #define STM_DMA_CCR_MEM2MEM             (14)
1299
1300 #define STM_DMA_CCR_PL                  (12)
1301 #define  STM_DMA_CCR_PL_LOW                     (0)
1302 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
1303 #define  STM_DMA_CCR_PL_HIGH                    (2)
1304 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
1305 #define  STM_DMA_CCR_PL_MASK                    (3)
1306
1307 #define STM_DMA_CCR_MSIZE               (10)
1308 #define  STM_DMA_CCR_MSIZE_8                    (0)
1309 #define  STM_DMA_CCR_MSIZE_16                   (1)
1310 #define  STM_DMA_CCR_MSIZE_32                   (2)
1311 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
1312
1313 #define STM_DMA_CCR_PSIZE               (8)
1314 #define  STM_DMA_CCR_PSIZE_8                    (0)
1315 #define  STM_DMA_CCR_PSIZE_16                   (1)
1316 #define  STM_DMA_CCR_PSIZE_32                   (2)
1317 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
1318
1319 #define STM_DMA_CCR_MINC                (7)
1320 #define STM_DMA_CCR_PINC                (6)
1321 #define STM_DMA_CCR_CIRC                (5)
1322 #define STM_DMA_CCR_DIR                 (4)
1323 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
1324 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
1325 #define STM_DMA_CCR_TEIE                (3)
1326 #define STM_DMA_CCR_HTIE                (2)
1327 #define STM_DMA_CCR_TCIE                (1)
1328 #define STM_DMA_CCR_EN                  (0)
1329
1330 #define STM_DMA_CHANNEL_ADC1            1
1331 #define STM_DMA_CHANNEL_SPI1_RX         2
1332 #define STM_DMA_CHANNEL_SPI1_TX         3
1333 #define STM_DMA_CHANNEL_SPI2_RX         4
1334 #define STM_DMA_CHANNEL_SPI2_TX         5
1335 #define STM_DMA_CHANNEL_USART3_TX       2
1336 #define STM_DMA_CHANNEL_USART3_RX       3
1337 #define STM_DMA_CHANNEL_USART1_TX       4
1338 #define STM_DMA_CHANNEL_USART1_RX       5
1339 #define STM_DMA_CHANNEL_USART2_RX       6
1340 #define STM_DMA_CHANNEL_USART2_TX       7
1341 #define STM_DMA_CHANNEL_I2C2_TX         4
1342 #define STM_DMA_CHANNEL_I2C2_RX         5
1343 #define STM_DMA_CHANNEL_I2C1_TX         6
1344 #define STM_DMA_CHANNEL_I2C1_RX         7
1345 #define STM_DMA_CHANNEL_TIM2_CH3        1
1346 #define STM_DMA_CHANNEL_TIM2_UP         2
1347 #define STM_DMA_CHANNEL_TIM2_CH1        5
1348 #define STM_DMA_CHANNEL_TIM2_CH2        7
1349 #define STM_DMA_CHANNEL_TIM2_CH4        7
1350 #define STM_DMA_CHANNEL_TIM3_CH3        2
1351 #define STM_DMA_CHANNEL_TIM3_CH4        3
1352 #define STM_DMA_CHANNEL_TIM3_UP         3
1353 #define STM_DMA_CHANNEL_TIM3_CH1        6
1354 #define STM_DMA_CHANNEL_TIM3_TRIG       6
1355 #define STM_DMA_CHANNEL_TIM4_CH1        1
1356 #define STM_DMA_CHANNEL_TIM4_CH2        4
1357 #define STM_DMA_CHANNEL_TIM4_CH3        5
1358 #define STM_DMA_CHANNEL_TIM4_UP         7
1359 #define STM_DMA_CHANNEL_TIM6_UP_DA      2
1360 #define STM_DMA_CHANNEL_C_CHANNEL1      2
1361 #define STM_DMA_CHANNEL_TIM7_UP_DA      3
1362 #define STM_DMA_CHANNEL_C_CHANNEL2      3
1363
1364 /*
1365  * Only spi channel 1 and 2 can use DMA
1366  */
1367 #define STM_NUM_SPI     2
1368
1369 struct stm_spi {
1370         vuint32_t       cr1;
1371         vuint32_t       cr2;
1372         vuint32_t       sr;
1373         vuint32_t       dr;
1374         vuint32_t       crcpr;
1375         vuint32_t       rxcrcr;
1376         vuint32_t       txcrcr;
1377 };
1378
1379 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1380
1381 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1382  */
1383
1384 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1385
1386 #define STM_SPI_CR1_BIDIMODE            15
1387 #define STM_SPI_CR1_BIDIOE              14
1388 #define STM_SPI_CR1_CRCEN               13
1389 #define STM_SPI_CR1_CRCNEXT             12
1390 #define STM_SPI_CR1_DFF                 11
1391 #define STM_SPI_CR1_RXONLY              10
1392 #define STM_SPI_CR1_SSM                 9
1393 #define STM_SPI_CR1_SSI                 8
1394 #define STM_SPI_CR1_LSBFIRST            7
1395 #define STM_SPI_CR1_SPE                 6
1396 #define STM_SPI_CR1_BR                  3
1397 #define  STM_SPI_CR1_BR_PCLK_2                  0
1398 #define  STM_SPI_CR1_BR_PCLK_4                  1
1399 #define  STM_SPI_CR1_BR_PCLK_8                  2
1400 #define  STM_SPI_CR1_BR_PCLK_16                 3
1401 #define  STM_SPI_CR1_BR_PCLK_32                 4
1402 #define  STM_SPI_CR1_BR_PCLK_64                 5
1403 #define  STM_SPI_CR1_BR_PCLK_128                6
1404 #define  STM_SPI_CR1_BR_PCLK_256                7
1405 #define  STM_SPI_CR1_BR_MASK                    7
1406
1407 #define STM_SPI_CR1_MSTR                2
1408 #define STM_SPI_CR1_CPOL                1
1409 #define STM_SPI_CR1_CPHA                0
1410
1411 #define STM_SPI_CR2_TXEIE       7
1412 #define STM_SPI_CR2_RXNEIE      6
1413 #define STM_SPI_CR2_ERRIE       5
1414 #define STM_SPI_CR2_SSOE        2
1415 #define STM_SPI_CR2_TXDMAEN     1
1416 #define STM_SPI_CR2_RXDMAEN     0
1417
1418 #define STM_SPI_SR_FRE          8
1419 #define STM_SPI_SR_BSY          7
1420 #define STM_SPI_SR_OVR          6
1421 #define STM_SPI_SR_MODF         5
1422 #define STM_SPI_SR_CRCERR       4
1423 #define STM_SPI_SR_UDR          3
1424 #define STM_SPI_SR_CHSIDE       2
1425 #define STM_SPI_SR_TXE          1
1426 #define STM_SPI_SR_RXNE         0
1427
1428 struct stm_adc {
1429         vuint32_t       sr;
1430         vuint32_t       cr1;
1431         vuint32_t       cr2;
1432         vuint32_t       smpr1;
1433         vuint32_t       smpr2;
1434         vuint32_t       smpr3;
1435         vuint32_t       jofr1;
1436         vuint32_t       jofr2;
1437         vuint32_t       jofr3;
1438         vuint32_t       jofr4;
1439         vuint32_t       htr;
1440         vuint32_t       ltr;
1441         vuint32_t       sqr1;
1442         vuint32_t       sqr2;
1443         vuint32_t       sqr3;
1444         vuint32_t       sqr4;
1445         vuint32_t       sqr5;
1446         vuint32_t       jsqr;
1447         vuint32_t       jdr1;
1448         vuint32_t       jdr2;
1449         vuint32_t       jdr3;
1450         vuint32_t       jdr4;
1451         vuint32_t       dr;
1452         uint8_t         reserved[0x300 - 0x5c];
1453         vuint32_t       csr;
1454         vuint32_t       ccr;
1455 };
1456
1457 extern struct stm_adc stm_adc;
1458
1459 #define STM_ADC_SQ_TEMP         16
1460 #define STM_ADC_SQ_V_REF        17
1461
1462 #define STM_ADC_SR_JCNR         9
1463 #define STM_ADC_SR_RCNR         8
1464 #define STM_ADC_SR_ADONS        6
1465 #define STM_ADC_SR_OVR          5
1466 #define STM_ADC_SR_STRT         4
1467 #define STM_ADC_SR_JSTRT        3
1468 #define STM_ADC_SR_JEOC         2
1469 #define STM_ADC_SR_EOC          1
1470 #define STM_ADC_SR_AWD          0
1471
1472 #define STM_ADC_CR1_OVRIE       26
1473 #define STM_ADC_CR1_RES         24
1474 #define  STM_ADC_CR1_RES_12             0
1475 #define  STM_ADC_CR1_RES_10             1
1476 #define  STM_ADC_CR1_RES_8              2
1477 #define  STM_ADC_CR1_RES_6              3
1478 #define  STM_ADC_CR1_RES_MASK           3
1479 #define STM_ADC_CR1_AWDEN       23
1480 #define STM_ADC_CR1_JAWDEN      22
1481 #define STM_ADC_CR1_PDI         17
1482 #define STM_ADC_CR1_PDD         16
1483 #define STM_ADC_CR1_DISCNUM     13
1484 #define  STM_ADC_CR1_DISCNUM_1          0
1485 #define  STM_ADC_CR1_DISCNUM_2          1
1486 #define  STM_ADC_CR1_DISCNUM_3          2
1487 #define  STM_ADC_CR1_DISCNUM_4          3
1488 #define  STM_ADC_CR1_DISCNUM_5          4
1489 #define  STM_ADC_CR1_DISCNUM_6          5
1490 #define  STM_ADC_CR1_DISCNUM_7          6
1491 #define  STM_ADC_CR1_DISCNUM_8          7
1492 #define  STM_ADC_CR1_DISCNUM_MASK       7
1493 #define STM_ADC_CR1_JDISCEN     12
1494 #define STM_ADC_CR1_DISCEN      11
1495 #define STM_ADC_CR1_JAUTO       10
1496 #define STM_ADC_CR1_AWDSGL      9
1497 #define STM_ADC_CR1_SCAN        8
1498 #define STM_ADC_CR1_JEOCIE      7
1499 #define STM_ADC_CR1_AWDIE       6
1500 #define STM_ADC_CR1_EOCIE       5
1501 #define STM_ADC_CR1_AWDCH       0
1502 #define  STM_ADC_CR1_AWDCH_MASK         0x1f
1503
1504 #define STM_ADC_CR2_SWSTART     30
1505 #define STM_ADC_CR2_EXTEN       28
1506 #define  STM_ADC_CR2_EXTEN_DISABLE      0
1507 #define  STM_ADC_CR2_EXTEN_RISING       1
1508 #define  STM_ADC_CR2_EXTEN_FALLING      2
1509 #define  STM_ADC_CR2_EXTEN_BOTH         3
1510 #define  STM_ADC_CR2_EXTEN_MASK         3
1511 #define STM_ADC_CR2_EXTSEL      24
1512 #define  STM_ADC_CR2_EXTSEL_TIM9_CC2    0
1513 #define  STM_ADC_CR2_EXTSEL_TIM9_TRGO   1
1514 #define  STM_ADC_CR2_EXTSEL_TIM2_CC3    2
1515 #define  STM_ADC_CR2_EXTSEL_TIM2_CC2    3
1516 #define  STM_ADC_CR2_EXTSEL_TIM3_TRGO   4
1517 #define  STM_ADC_CR2_EXTSEL_TIM4_CC4    5
1518 #define  STM_ADC_CR2_EXTSEL_TIM2_TRGO   6
1519 #define  STM_ADC_CR2_EXTSEL_TIM3_CC1    7
1520 #define  STM_ADC_CR2_EXTSEL_TIM3_CC3    8
1521 #define  STM_ADC_CR2_EXTSEL_TIM4_TRGO   9
1522 #define  STM_ADC_CR2_EXTSEL_TIM6_TRGO   10
1523 #define  STM_ADC_CR2_EXTSEL_EXTI_11     15
1524 #define  STM_ADC_CR2_EXTSEL_MASK        15
1525 #define STM_ADC_CR2_JWSTART     22
1526 #define STM_ADC_CR2_JEXTEN      20
1527 #define  STM_ADC_CR2_JEXTEN_DISABLE     0
1528 #define  STM_ADC_CR2_JEXTEN_RISING      1
1529 #define  STM_ADC_CR2_JEXTEN_FALLING     2
1530 #define  STM_ADC_CR2_JEXTEN_BOTH        3
1531 #define  STM_ADC_CR2_JEXTEN_MASK        3
1532 #define STM_ADC_CR2_JEXTSEL     16
1533 #define  STM_ADC_CR2_JEXTSEL_TIM9_CC1   0
1534 #define  STM_ADC_CR2_JEXTSEL_TIM9_TRGO  1
1535 #define  STM_ADC_CR2_JEXTSEL_TIM2_TRGO  2
1536 #define  STM_ADC_CR2_JEXTSEL_TIM2_CC1   3
1537 #define  STM_ADC_CR2_JEXTSEL_TIM3_CC4   4
1538 #define  STM_ADC_CR2_JEXTSEL_TIM4_TRGO  5
1539 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC1   6
1540 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC2   7
1541 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC3   8
1542 #define  STM_ADC_CR2_JEXTSEL_TIM10_CC1  9
1543 #define  STM_ADC_CR2_JEXTSEL_TIM7_TRGO  10
1544 #define  STM_ADC_CR2_JEXTSEL_EXTI_15    15
1545 #define  STM_ADC_CR2_JEXTSEL_MASK       15
1546 #define STM_ADC_CR2_ALIGN       11
1547 #define STM_ADC_CR2_EOCS        10
1548 #define STM_ADC_CR2_DDS         9
1549 #define STM_ADC_CR2_DMA         8
1550 #define STM_ADC_CR2_DELS        4
1551 #define  STM_ADC_CR2_DELS_NONE          0
1552 #define  STM_ADC_CR2_DELS_UNTIL_READ    1
1553 #define  STM_ADC_CR2_DELS_7             2
1554 #define  STM_ADC_CR2_DELS_15            3
1555 #define  STM_ADC_CR2_DELS_31            4
1556 #define  STM_ADC_CR2_DELS_63            5
1557 #define  STM_ADC_CR2_DELS_127           6
1558 #define  STM_ADC_CR2_DELS_255           7
1559 #define  STM_ADC_CR2_DELS_MASK          7
1560 #define STM_ADC_CR2_CONT        1
1561 #define STM_ADC_CR2_ADON        0
1562
1563 #define STM_ADC_CCR_TSVREFE     23
1564 #define STM_ADC_CCR_ADCPRE      16
1565 #define  STM_ADC_CCR_ADCPRE_HSI_1       0
1566 #define  STM_ADC_CCR_ADCPRE_HSI_2       1
1567 #define  STM_ADC_CCR_ADCPRE_HSI_4       2
1568 #define  STM_ADC_CCR_ADCPRE_MASK        3
1569
1570 struct stm_temp_cal {
1571         uint16_t        vref;
1572         uint16_t        ts_cal_cold;
1573         uint16_t        reserved;
1574         uint16_t        ts_cal_hot;
1575 };
1576
1577 extern struct stm_temp_cal      stm_temp_cal;
1578
1579 #define stm_temp_cal_cold       25
1580 #define stm_temp_cal_hot        110
1581
1582 struct stm_dbg_mcu {
1583         uint32_t        idcode;
1584 };
1585
1586 extern struct stm_dbg_mcu       stm_dbg_mcu;
1587
1588 static inline uint16_t
1589 stm_dev_id(void) {
1590         return stm_dbg_mcu.idcode & 0xfff;
1591 }
1592
1593 struct stm_flash_size {
1594         uint16_t        f_size;
1595 };
1596
1597 extern struct stm_flash_size    stm_flash_size_medium;
1598 extern struct stm_flash_size    stm_flash_size_large;
1599
1600 /* Returns flash size in bytes */
1601 extern uint32_t
1602 stm_flash_size(void);
1603
1604 struct stm_device_id {
1605         uint32_t        u_id0;
1606         uint32_t        u_id1;
1607         uint32_t        u_id2;
1608 };
1609
1610 extern struct stm_device_id     stm_device_id;
1611
1612 #define STM_NUM_I2C     2
1613
1614 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1615
1616 struct stm_i2c {
1617         vuint32_t       cr1;
1618         vuint32_t       cr2;
1619         vuint32_t       oar1;
1620         vuint32_t       oar2;
1621         vuint32_t       dr;
1622         vuint32_t       sr1;
1623         vuint32_t       sr2;
1624         vuint32_t       ccr;
1625         vuint32_t       trise;
1626 };
1627
1628 extern struct stm_i2c stm_i2c1, stm_i2c2;
1629
1630 #define STM_I2C_CR1_SWRST       15
1631 #define STM_I2C_CR1_ALERT       13
1632 #define STM_I2C_CR1_PEC         12
1633 #define STM_I2C_CR1_POS         11
1634 #define STM_I2C_CR1_ACK         10
1635 #define STM_I2C_CR1_STOP        9
1636 #define STM_I2C_CR1_START       8
1637 #define STM_I2C_CR1_NOSTRETCH   7
1638 #define STM_I2C_CR1_ENGC        6
1639 #define STM_I2C_CR1_ENPEC       5
1640 #define STM_I2C_CR1_ENARP       4
1641 #define STM_I2C_CR1_SMBTYPE     3
1642 #define STM_I2C_CR1_SMBUS       1
1643 #define STM_I2C_CR1_PE          0
1644
1645 #define STM_I2C_CR2_LAST        12
1646 #define STM_I2C_CR2_DMAEN       11
1647 #define STM_I2C_CR2_ITBUFEN     10
1648 #define STM_I2C_CR2_ITEVTEN     9
1649 #define STM_I2C_CR2_ITERREN     8
1650 #define STM_I2C_CR2_FREQ        0
1651 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1652 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1653 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1654 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1655 #define  STM_I2C_CR2_FREQ_24_MHZ        24
1656 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1657 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1658
1659 #define STM_I2C_SR1_SMBALERT    15
1660 #define STM_I2C_SR1_TIMEOUT     14
1661 #define STM_I2C_SR1_PECERR      12
1662 #define STM_I2C_SR1_OVR         11
1663 #define STM_I2C_SR1_AF          10
1664 #define STM_I2C_SR1_ARLO        9
1665 #define STM_I2C_SR1_BERR        8
1666 #define STM_I2C_SR1_TXE         7
1667 #define STM_I2C_SR1_RXNE        6
1668 #define STM_I2C_SR1_STOPF       4
1669 #define STM_I2C_SR1_ADD10       3
1670 #define STM_I2C_SR1_BTF         2
1671 #define STM_I2C_SR1_ADDR        1
1672 #define STM_I2C_SR1_SB          0
1673
1674 #define STM_I2C_SR2_PEC         8
1675 #define  STM_I2C_SR2_PEC_MASK   0xff00
1676 #define STM_I2C_SR2_DUALF       7
1677 #define STM_I2C_SR2_SMBHOST     6
1678 #define STM_I2C_SR2_SMBDEFAULT  5
1679 #define STM_I2C_SR2_GENCALL     4
1680 #define STM_I2C_SR2_TRA         2
1681 #define STM_I2C_SR2_BUSY        1
1682 #define STM_I2C_SR2_MSL         0
1683
1684 #define STM_I2C_CCR_FS          15
1685 #define STM_I2C_CCR_DUTY        14
1686 #define STM_I2C_CCR_CCR         0
1687 #define  STM_I2C_CCR_MASK       0x7ff
1688
1689 struct stm_tim234 {
1690         vuint32_t       cr1;
1691         vuint32_t       cr2;
1692         vuint32_t       smcr;
1693         vuint32_t       dier;
1694
1695         vuint32_t       sr;
1696         vuint32_t       egr;
1697         vuint32_t       ccmr1;
1698         vuint32_t       ccmr2;
1699
1700         vuint32_t       ccer;
1701         vuint32_t       cnt;
1702         vuint32_t       psc;
1703         vuint32_t       arr;
1704
1705         uint32_t        reserved_30;
1706         vuint32_t       ccr1;
1707         vuint32_t       ccr2;
1708         vuint32_t       ccr3;
1709
1710         vuint32_t       ccr4;
1711         uint32_t        reserved_44;
1712         vuint32_t       dcr;
1713         vuint32_t       dmar;
1714
1715         uint32_t        reserved_50;
1716 };
1717
1718 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1719
1720 #define STM_TIM234_CR1_CKD      8
1721 #define  STM_TIM234_CR1_CKD_1           0
1722 #define  STM_TIM234_CR1_CKD_2           1
1723 #define  STM_TIM234_CR1_CKD_4           2
1724 #define  STM_TIM234_CR1_CKD_MASK        3
1725 #define STM_TIM234_CR1_ARPE     7
1726 #define STM_TIM234_CR1_CMS      5
1727 #define  STM_TIM234_CR1_CMS_EDGE        0
1728 #define  STM_TIM234_CR1_CMS_CENTER_1    1
1729 #define  STM_TIM234_CR1_CMS_CENTER_2    2
1730 #define  STM_TIM234_CR1_CMS_CENTER_3    3
1731 #define  STM_TIM234_CR1_CMS_MASK        3
1732 #define STM_TIM234_CR1_DIR      4
1733 #define  STM_TIM234_CR1_DIR_UP          0
1734 #define  STM_TIM234_CR1_DIR_DOWN        1
1735 #define STM_TIM234_CR1_OPM      3
1736 #define STM_TIM234_CR1_URS      2
1737 #define STM_TIM234_CR1_UDIS     1
1738 #define STM_TIM234_CR1_CEN      0
1739
1740 #define STM_TIM234_CR2_TI1S     7
1741 #define STM_TIM234_CR2_MMS      4
1742 #define  STM_TIM234_CR2_MMS_RESET               0
1743 #define  STM_TIM234_CR2_MMS_ENABLE              1
1744 #define  STM_TIM234_CR2_MMS_UPDATE              2
1745 #define  STM_TIM234_CR2_MMS_COMPARE_PULSE       3
1746 #define  STM_TIM234_CR2_MMS_COMPARE_OC1REF      4
1747 #define  STM_TIM234_CR2_MMS_COMPARE_OC2REF      5
1748 #define  STM_TIM234_CR2_MMS_COMPARE_OC3REF      6
1749 #define  STM_TIM234_CR2_MMS_COMPARE_OC4REF      7
1750 #define  STM_TIM234_CR2_MMS_MASK                7
1751 #define STM_TIM234_CR2_CCDS     3
1752
1753 #define STM_TIM234_SMCR_ETP     15
1754 #define STM_TIM234_SMCR_ECE     14
1755 #define STM_TIM234_SMCR_ETPS    12
1756 #define  STM_TIM234_SMCR_ETPS_OFF               0
1757 #define  STM_TIM234_SMCR_ETPS_DIV_2             1
1758 #define  STM_TIM234_SMCR_ETPS_DIV_4             2
1759 #define  STM_TIM234_SMCR_ETPS_DIV_8             3
1760 #define  STM_TIM234_SMCR_ETPS_MASK              3
1761 #define STM_TIM234_SMCR_ETF     8
1762 #define  STM_TIM234_SMCR_ETF_NONE               0
1763 #define  STM_TIM234_SMCR_ETF_INT_N_2            1
1764 #define  STM_TIM234_SMCR_ETF_INT_N_4            2
1765 #define  STM_TIM234_SMCR_ETF_INT_N_8            3
1766 #define  STM_TIM234_SMCR_ETF_DTS_2_N_6          4
1767 #define  STM_TIM234_SMCR_ETF_DTS_2_N_8          5
1768 #define  STM_TIM234_SMCR_ETF_DTS_4_N_6          6
1769 #define  STM_TIM234_SMCR_ETF_DTS_4_N_8          7
1770 #define  STM_TIM234_SMCR_ETF_DTS_8_N_6          8
1771 #define  STM_TIM234_SMCR_ETF_DTS_8_N_8          9
1772 #define  STM_TIM234_SMCR_ETF_DTS_16_N_5         10
1773 #define  STM_TIM234_SMCR_ETF_DTS_16_N_6         11
1774 #define  STM_TIM234_SMCR_ETF_DTS_16_N_8         12
1775 #define  STM_TIM234_SMCR_ETF_DTS_32_N_5         13
1776 #define  STM_TIM234_SMCR_ETF_DTS_32_N_6         14
1777 #define  STM_TIM234_SMCR_ETF_DTS_32_N_8         15
1778 #define  STM_TIM234_SMCR_ETF_MASK               15
1779 #define STM_TIM234_SMCR_MSM     7
1780 #define STM_TIM234_SMCR_TS      4
1781 #define  STM_TIM234_SMCR_TS_ITR0                0
1782 #define  STM_TIM234_SMCR_TS_ITR1                1
1783 #define  STM_TIM234_SMCR_TS_ITR2                2
1784 #define  STM_TIM234_SMCR_TS_ITR3                3
1785 #define  STM_TIM234_SMCR_TS_TI1F_ED             4
1786 #define  STM_TIM234_SMCR_TS_TI1FP1              5
1787 #define  STM_TIM234_SMCR_TS_TI2FP2              6
1788 #define  STM_TIM234_SMCR_TS_ETRF                7
1789 #define  STM_TIM234_SMCR_TS_MASK                7
1790 #define STM_TIM234_SMCR_OCCS    3
1791 #define STM_TIM234_SMCR_SMS     0
1792 #define  STM_TIM234_SMCR_SMS_DISABLE            0
1793 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_1     1
1794 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_2     2
1795 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_3     3
1796 #define  STM_TIM234_SMCR_SMS_RESET_MODE         4
1797 #define  STM_TIM234_SMCR_SMS_GATED_MODE         5
1798 #define  STM_TIM234_SMCR_SMS_TRIGGER_MODE       6
1799 #define  STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK     7
1800 #define  STM_TIM234_SMCR_SMS_MASK               7
1801
1802 #define STM_TIM234_DIER_CC4IE           4
1803 #define STM_TIM234_DIER_CC3IE           3
1804 #define STM_TIM234_DIER_CC2IE           2
1805 #define STM_TIM234_DIER_CC1IE           1
1806 #define STM_TIM234_DIER_UIE             0
1807
1808 #define STM_TIM234_SR_CC4OF     12
1809 #define STM_TIM234_SR_CC3OF     11
1810 #define STM_TIM234_SR_CC2OF     10
1811 #define STM_TIM234_SR_CC1OF     9
1812 #define STM_TIM234_SR_TIF       6
1813 #define STM_TIM234_SR_CC4IF     4
1814 #define STM_TIM234_SR_CC3IF     3
1815 #define STM_TIM234_SR_CC2IF     2
1816 #define STM_TIM234_SR_CC1IF     1
1817 #define STM_TIM234_SR_UIF       0
1818
1819 #define STM_TIM234_EGR_TG       6
1820 #define STM_TIM234_EGR_CC4G     4
1821 #define STM_TIM234_EGR_CC3G     3
1822 #define STM_TIM234_EGR_CC2G     2
1823 #define STM_TIM234_EGR_CC1G     1
1824 #define STM_TIM234_EGR_UG       0
1825
1826 #define STM_TIM234_CCMR1_OC2CE  15
1827 #define STM_TIM234_CCMR1_OC2M   12
1828 #define  STM_TIM234_CCMR1_OC2M_FROZEN                   0
1829 #define  STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH        1
1830 #define  STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH         2
1831 #define  STM_TIM234_CCMR1_OC2M_TOGGLE                   3
1832 #define  STM_TIM234_CCMR1_OC2M_FORCE_LOW                4
1833 #define  STM_TIM234_CCMR1_OC2M_FORCE_HIGH               5
1834 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_1               6
1835 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_2               7
1836 #define  STM_TIM234_CCMR1_OC2M_MASK                     7
1837 #define STM_TIM234_CCMR1_OC2PE  11
1838 #define STM_TIM234_CCMR1_OC2FE  10
1839 #define STM_TIM234_CCMR1_CC2S   8
1840 #define  STM_TIM234_CCMR1_CC2S_OUTPUT                   0
1841 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI2                1
1842 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI1                2
1843 #define  STM_TIM234_CCMR1_CC2S_INPUT_TRC                3
1844 #define  STM_TIM234_CCMR1_CC2S_MASK                     3
1845
1846 #define STM_TIM234_CCMR1_OC1CE  7
1847 #define STM_TIM234_CCMR1_OC1M   4
1848 #define  STM_TIM234_CCMR1_OC1M_FROZEN                   0
1849 #define  STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH        1
1850 #define  STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH         2
1851 #define  STM_TIM234_CCMR1_OC1M_TOGGLE                   3
1852 #define  STM_TIM234_CCMR1_OC1M_FORCE_LOW                4
1853 #define  STM_TIM234_CCMR1_OC1M_FORCE_HIGH               5
1854 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_1               6
1855 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_2               7
1856 #define  STM_TIM234_CCMR1_OC1M_MASK                     7
1857 #define STM_TIM234_CCMR1_OC1PE  3
1858 #define STM_TIM234_CCMR1_OC1FE  2
1859 #define STM_TIM234_CCMR1_CC1S   0
1860 #define  STM_TIM234_CCMR1_CC1S_OUTPUT                   0
1861 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI1                1
1862 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI2                2
1863 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC                3
1864 #define  STM_TIM234_CCMR1_CC1S_MASK                     3
1865
1866 #define STM_TIM234_CCMR2_OC4CE  15
1867 #define STM_TIM234_CCMR2_OC4M   12
1868 #define  STM_TIM234_CCMR2_OC4M_FROZEN                   0
1869 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
1870 #define  STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH         2
1871 #define  STM_TIM234_CCMR2_OC4M_TOGGLE                   3
1872 #define  STM_TIM234_CCMR2_OC4M_FORCE_LOW                4
1873 #define  STM_TIM234_CCMR2_OC4M_FORCE_HIGH               5
1874 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_1               6
1875 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_2               7
1876 #define  STM_TIM234_CCMR2_OC4M_MASK                     7
1877 #define STM_TIM234_CCMR2_OC4PE  11
1878 #define STM_TIM234_CCMR2_OC4FE  10
1879 #define STM_TIM234_CCMR2_CC4S   8
1880 #define  STM_TIM234_CCMR2_CC4S_OUTPUT                   0
1881 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI4                1
1882 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI3                2
1883 #define  STM_TIM234_CCMR2_CC4S_INPUT_TRC                3
1884 #define  STM_TIM234_CCMR2_CC4S_MASK                     3
1885
1886 #define STM_TIM234_CCMR2_OC3CE  7
1887 #define STM_TIM234_CCMR2_OC3M   4
1888 #define  STM_TIM234_CCMR2_OC3M_FROZEN                   0
1889 #define  STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH        1
1890 #define  STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH         2
1891 #define  STM_TIM234_CCMR2_OC3M_TOGGLE                   3
1892 #define  STM_TIM234_CCMR2_OC3M_FORCE_LOW                4
1893 #define  STM_TIM234_CCMR2_OC3M_FORCE_HIGH               5
1894 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_1               6
1895 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_2               7
1896 #define  STM_TIM234_CCMR2_OC3M_MASK                     7
1897 #define STM_TIM234_CCMR2_OC3PE  3
1898 #define STM_TIM234_CCMR2_OC3FE  2
1899 #define STM_TIM234_CCMR2_CC3S   0
1900 #define  STM_TIM234_CCMR2_CC3S_OUTPUT                   0
1901 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI3                1
1902 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI4                2
1903 #define  STM_TIM234_CCMR2_CC3S_INPUT_TRC                3
1904 #define  STM_TIM234_CCMR2_CC3S_MASK                     3
1905
1906 #define STM_TIM234_CCER_CC4NP   15
1907 #define STM_TIM234_CCER_CC4P    13
1908 #define  STM_TIM234_CCER_CC4P_ACTIVE_HIGH       0
1909 #define  STM_TIM234_CCER_CC4P_ACTIVE_LOW        1
1910 #define STM_TIM234_CCER_CC4E    12
1911 #define STM_TIM234_CCER_CC3NP   11
1912 #define STM_TIM234_CCER_CC3P    9
1913 #define  STM_TIM234_CCER_CC3P_ACTIVE_HIGH       0
1914 #define  STM_TIM234_CCER_CC3P_ACTIVE_LOW        1
1915 #define STM_TIM234_CCER_CC3E    8
1916 #define STM_TIM234_CCER_CC2NP   7
1917 #define STM_TIM234_CCER_CC2P    5
1918 #define  STM_TIM234_CCER_CC2P_ACTIVE_HIGH       0
1919 #define  STM_TIM234_CCER_CC2P_ACTIVE_LOW        1
1920 #define STM_TIM234_CCER_CC2E    4
1921 #define STM_TIM234_CCER_CC1NP   3
1922 #define STM_TIM234_CCER_CC1P    1
1923 #define  STM_TIM234_CCER_CC1P_ACTIVE_HIGH       0
1924 #define  STM_TIM234_CCER_CC1P_ACTIVE_LOW        1
1925 #define STM_TIM234_CCER_CC1E    0
1926
1927 struct stm_usb {
1928         vuint32_t       epr[8];
1929         uint8_t         reserved_20[0x40 - 0x20];
1930         vuint32_t       cntr;
1931         vuint32_t       istr;
1932         vuint32_t       fnr;
1933         vuint32_t       daddr;
1934         vuint32_t       btable;
1935 };
1936
1937 #define STM_USB_EPR_CTR_RX      15
1938 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1939 #define STM_USB_EPR_DTOG_RX     14
1940 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1941 #define STM_USB_EPR_STAT_RX     12
1942 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1943 #define  STM_USB_EPR_STAT_RX_STALL                      1
1944 #define  STM_USB_EPR_STAT_RX_NAK                        2
1945 #define  STM_USB_EPR_STAT_RX_VALID                      3
1946 #define  STM_USB_EPR_STAT_RX_MASK                       3
1947 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1948 #define STM_USB_EPR_SETUP       11
1949 #define STM_USB_EPR_EP_TYPE     9
1950 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1951 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1952 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1953 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1954 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1955 #define STM_USB_EPR_EP_KIND     8
1956 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1957 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1958 #define STM_USB_EPR_CTR_TX      7
1959 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1960 #define STM_USB_EPR_DTOG_TX     6
1961 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1962 #define STM_USB_EPR_STAT_TX     4
1963 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1964 #define  STM_USB_EPR_STAT_TX_STALL                      1
1965 #define  STM_USB_EPR_STAT_TX_NAK                        2
1966 #define  STM_USB_EPR_STAT_TX_VALID                      3
1967 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1968 #define  STM_USB_EPR_STAT_TX_MASK                       3
1969 #define STM_USB_EPR_EA          0
1970 #define  STM_USB_EPR_EA_MASK                            0xf
1971
1972 #define STM_USB_CNTR_CTRM       15
1973 #define STM_USB_CNTR_PMAOVRM    14
1974 #define STM_USB_CNTR_ERRM       13
1975 #define STM_USB_CNTR_WKUPM      12
1976 #define STM_USB_CNTR_SUSPM      11
1977 #define STM_USB_CNTR_RESETM     10
1978 #define STM_USB_CNTR_SOFM       9
1979 #define STM_USB_CNTR_ESOFM      8
1980 #define STM_USB_CNTR_RESUME     4
1981 #define STM_USB_CNTR_FSUSP      3
1982 #define STM_USB_CNTR_LP_MODE    2
1983 #define STM_USB_CNTR_PDWN       1
1984 #define STM_USB_CNTR_FRES       0
1985
1986 #define STM_USB_ISTR_CTR        15
1987 #define STM_USB_ISTR_PMAOVR     14
1988 #define STM_USB_ISTR_ERR        13
1989 #define STM_USB_ISTR_WKUP       12
1990 #define STM_USB_ISTR_SUSP       11
1991 #define STM_USB_ISTR_RESET      10
1992 #define STM_USB_ISTR_SOF        9
1993 #define STM_USB_ISTR_ESOF       8
1994 #define STM_USB_ISTR_DIR        4
1995 #define STM_USB_ISTR_EP_ID      0
1996 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1997
1998 #define STM_USB_FNR_RXDP        15
1999 #define STM_USB_FNR_RXDM        14
2000 #define STM_USB_FNR_LCK         13
2001 #define STM_USB_FNR_LSOF        11
2002 #define  STM_USB_FNR_LSOF_MASK                  0x3
2003 #define STM_USB_FNR_FN          0
2004 #define  STM_USB_FNR_FN_MASK                    0x7ff
2005
2006 #define STM_USB_DADDR_EF        7
2007 #define STM_USB_DADDR_ADD       0
2008 #define  STM_USB_DADDR_ADD_MASK                 0x7f
2009
2010 extern struct stm_usb stm_usb;
2011
2012 union stm_usb_bdt {
2013         struct {
2014                 vuint32_t       addr_tx;
2015                 vuint32_t       count_tx;
2016                 vuint32_t       addr_rx;
2017                 vuint32_t       count_rx;
2018         } single;
2019         struct {
2020                 vuint32_t       addr;
2021                 vuint32_t       count;
2022         } double_tx[2];
2023         struct {
2024                 vuint32_t       addr;
2025                 vuint32_t       count;
2026         } double_rx[2];
2027 };
2028
2029 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
2030 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
2031 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
2032 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
2033 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
2034
2035 #define STM_USB_BDT_SIZE        8
2036
2037 extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4)));
2038
2039 struct stm_exti {
2040         vuint32_t       imr;
2041         vuint32_t       emr;
2042         vuint32_t       rtsr;
2043         vuint32_t       ftsr;
2044
2045         vuint32_t       swier;
2046         vuint32_t       pr;
2047 };
2048
2049 extern struct stm_exti stm_exti;
2050
2051 #endif /* _STM32L_H_ */