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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #ifndef _STM32L_H_
  19 #define _STM32L_H_
  20
  21 #include <stdint.h>
  22
  23 typedef volatile uint32_t       vuint32_t;
  24 typedef volatile void *         vvoid_t;
  25
  26 struct stm_gpio {
  27         vuint32_t       moder;
  28         vuint32_t       otyper;
  29         vuint32_t       ospeedr;
  30         vuint32_t       pupdr;
  31
  32         vuint32_t       idr;
  33         vuint32_t       odr;
  34         vuint32_t       bsrr;
  35         vuint32_t       lckr;
  36
  37         vuint32_t       afrl;
  38         vuint32_t       afrh;
  39 };
  40
  41 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  42 #define STM_MODER_MASK                  3
  43 #define STM_MODER_INPUT                 0
  44 #define STM_MODER_OUTPUT                1
  45 #define STM_MODER_ALTERNATE             2
  46 #define STM_MODER_ANALOG                3
  47
  48 static inline void
  49 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  50         gpio->moder = ((gpio->moder &
  51                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  52                        value << STM_MODER_SHIFT(pin));
  53 }
  54
  55 static inline vuint32_t
  56 stm_moder_get(struct stm_gpio *gpio, int pin) {
  57         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  58 }
  59
  60 #define STM_OTYPER_SHIFT(pin)           (pin)
  61 #define STM_OTYPER_MASK                 1
  62 #define STM_OTYPER_PUSH_PULL            0
  63 #define STM_OTYPER_OPEN_DRAIN           1
  64
  65 static inline void
  66 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  67         gpio->otyper = ((gpio->otyper &
  68                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  69                         value << STM_OTYPER_SHIFT(pin));
  70 }
  71
  72 static inline vuint32_t
  73 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  74         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  75 }
  76
  77 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  78 #define STM_OSPEEDR_MASK                3
  79 #define STM_OSPEEDR_400kHz              0
  80 #define STM_OSPEEDR_2MHz                1
  81 #define STM_OSPEEDR_10MHz               2
  82 #define STM_OSPEEDR_40MHz               3
  83
  84 static inline void
  85 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  86         gpio->ospeedr = ((gpio->ospeedr &
  87                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  88                        value << STM_OSPEEDR_SHIFT(pin));
  89 }
  90
  91 static inline vuint32_t
  92 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  93         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  94 }
  95
  96 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
  97 #define STM_PUPDR_MASK                  3
  98 #define STM_PUPDR_NONE                  0
  99 #define STM_PUPDR_PULL_UP               1
 100 #define STM_PUPDR_PULL_DOWN             2
 101 #define STM_PUPDR_RESERVED              3
 102
 103 static inline void
 104 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 105         gpio->pupdr = ((gpio->pupdr &
 106                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 107                        value << STM_PUPDR_SHIFT(pin));
 108 }
 109
 110 static inline uint32_t
 111 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 112         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 113 }
 114
 115 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 116 #define STM_AFR_MASK                    0xf
 117 #define STM_AFR_NONE                    0
 118 #define STM_AFR_AF0                     0x0
 119 #define STM_AFR_AF1                     0x1
 120 #define STM_AFR_AF2                     0x2
 121 #define STM_AFR_AF3                     0x3
 122 #define STM_AFR_AF4                     0x4
 123 #define STM_AFR_AF5                     0x5
 124 #define STM_AFR_AF6                     0x6
 125 #define STM_AFR_AF7                     0x7
 126 #define STM_AFR_AF8                     0x8
 127 #define STM_AFR_AF9                     0x9
 128 #define STM_AFR_AF10                    0xa
 129 #define STM_AFR_AF11                    0xb
 130 #define STM_AFR_AF12                    0xc
 131 #define STM_AFR_AF13                    0xd
 132 #define STM_AFR_AF14                    0xe
 133 #define STM_AFR_AF15                    0xf
 134
 135 static inline void
 136 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 137         /*
 138          * Set alternate pin mode too
 139          */
 140         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 141         if (pin < 8)
 142                 gpio->afrl = ((gpio->afrl &
 143                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 144                               value << STM_AFR_SHIFT(pin));
 145         else {
 146                 pin -= 8;
 147                 gpio->afrh = ((gpio->afrh &
 148                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 149                               value << STM_AFR_SHIFT(pin));
 150         }
 151 }
 152
 153 static inline uint32_t
 154 stm_afr_get(struct stm_gpio *gpio, int pin) {
 155         if (pin < 8)
 156                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 157         else {
 158                 pin -= 8;
 159                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 160         }
 161 }
 162
 163 static inline void
 164 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 165         /* Use the bit set/reset register to do this atomically */
 166         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 167 }
 168
 169 static inline uint8_t
 170 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 171         return (gpio->idr >> pin) & 1;
 172 }
 173
 174 extern struct stm_gpio stm_gpioa;
 175 extern struct stm_gpio stm_gpiob;
 176 extern struct stm_gpio stm_gpioc;
 177 extern struct stm_gpio stm_gpiod;
 178 extern struct stm_gpio stm_gpioe;
 179 extern struct stm_gpio stm_gpioh;
 180
 181 struct stm_usart {
 182         vuint32_t       sr;     /* status register */
 183         vuint32_t       dr;     /* data register */
 184         vuint32_t       brr;    /* baud rate register */
 185         vuint32_t       cr1;    /* control register 1 */
 186
 187         vuint32_t       cr2;    /* control register 2 */
 188         vuint32_t       cr3;    /* control register 3 */
 189         vuint32_t       gtpr;   /* guard time and prescaler */
 190 };
 191
 192 extern struct stm_usart stm_usart1;
 193 extern struct stm_usart stm_usart2;
 194 extern struct stm_usart stm_usart3;
 195
 196 #define STM_USART_SR_CTS        (9)     /* CTS flag */
 197 #define STM_USART_SR_LBD        (8)     /* LIN break detection flag */
 198 #define STM_USART_SR_TXE        (7)     /* Transmit data register empty */
 199 #define STM_USART_SR_TC         (6)     /* Transmission complete */
 200 #define STM_USART_SR_RXNE       (5)     /* Read data register not empty */
 201 #define STM_USART_SR_IDLE       (4)     /* IDLE line detected */
 202 #define STM_USART_SR_ORE        (3)     /* Overrun error */
 203 #define STM_USART_SR_NF         (2)     /* Noise detected flag */
 204 #define STM_USART_SR_FE         (1)     /* Framing error */
 205 #define STM_USART_SR_PE         (0)     /* Parity error */
 206
 207 #define STM_USART_CR1_OVER8     (15)    /* Oversampling mode */
 208 #define STM_USART_CR1_UE        (13)    /* USART enable */
 209 #define STM_USART_CR1_M         (12)    /* Word length */
 210 #define STM_USART_CR1_WAKE      (11)    /* Wakeup method */
 211 #define STM_USART_CR1_PCE       (10)    /* Parity control enable */
 212 #define STM_USART_CR1_PS        (9)     /* Parity selection */
 213 #define STM_USART_CR1_PEIE      (8)     /* PE interrupt enable */
 214 #define STM_USART_CR1_TXEIE     (7)     /* TXE interrupt enable */
 215 #define STM_USART_CR1_TCIE      (6)     /* Transmission complete interrupt enable */
 216 #define STM_USART_CR1_RXNEIE    (5)     /* RXNE interrupt enable */
 217 #define STM_USART_CR1_IDLEIE    (4)     /* IDLE interrupt enable */
 218 #define STM_USART_CR1_TE        (3)     /* Transmitter enable */
 219 #define STM_USART_CR1_RE        (2)     /* Receiver enable */
 220 #define STM_USART_CR1_RWU       (1)     /* Receiver wakeup */
 221 #define STM_USART_CR1_SBK       (0)     /* Send break */
 222
 223 #define STM_USART_CR2_LINEN     (14)    /* LIN mode enable */
 224 #define STM_USART_CR2_STOP      (12)    /* STOP bits */
 225 #define STM_USART_CR2_STOP_MASK 3
 226 #define STM_USART_CR2_STOP_1    0
 227 #define STM_USART_CR2_STOP_0_5  1
 228 #define STM_USART_CR2_STOP_2    2
 229 #define STM_USART_CR2_STOP_1_5  3
 230
 231 #define STM_USART_CR2_CLKEN     (11)    /* Clock enable */
 232 #define STM_USART_CR2_CPOL      (10)    /* Clock polarity */
 233 #define STM_USART_CR2_CPHA      (9)     /* Clock phase */
 234 #define STM_USART_CR2_LBCL      (8)     /* Last bit clock pulse */
 235 #define STM_USART_CR2_LBDIE     (6)     /* LIN break detection interrupt enable */
 236 #define STM_USART_CR2_LBDL      (5)     /* lin break detection length */
 237 #define STM_USART_CR2_ADD       (0)
 238 #define STM_USART_CR2_ADD_MASK  0xf
 239
 240 #define STM_USART_CR3_ONEBITE   (11)    /* One sample bit method enable */
 241 #define STM_USART_CR3_CTSIE     (10)    /* CTS interrupt enable */
 242 #define STM_USART_CR3_CTSE      (9)     /* CTS enable */
 243 #define STM_USART_CR3_RTSE      (8)     /* RTS enable */
 244 #define STM_USART_CR3_DMAT      (7)     /* DMA enable transmitter */
 245 #define STM_USART_CR3_DMAR      (6)     /* DMA enable receiver */
 246 #define STM_USART_CR3_SCEN      (5)     /* Smartcard mode enable */
 247 #define STM_USART_CR3_NACK      (4)     /* Smartcard NACK enable */
 248 #define STM_USART_CR3_HDSEL     (3)     /* Half-duplex selection */
 249 #define STM_USART_CR3_IRLP      (2)     /* IrDA low-power */
 250 #define STM_USART_CR3_IREN      (1)     /* IrDA mode enable */
 251 #define STM_USART_CR3_EIE       (0)     /* Error interrupt enable */
 252
 253 struct stm_tim {
 254 };
 255
 256 extern struct stm_tim stm_tim9;
 257 extern struct stm_tim stm_tim10;
 258 extern struct stm_tim stm_tim11;
 259
 260 /* Flash interface */
 261
 262 struct stm_flash {
 263         vuint32_t       acr;
 264         vuint32_t       pecr;
 265         vuint32_t       pdkeyr;
 266         vuint32_t       pekeyr;
 267
 268         vuint32_t       prgkeyr;
 269         vuint32_t       optkeyr;
 270         vuint32_t       sr;
 271         vuint32_t       obr;
 272
 273         vuint32_t       wrpr;
 274 };
 275
 276 extern struct stm_flash stm_flash;
 277
 278 #define STM_FLASH_ACR_RUN_PD    (4)
 279 #define STM_FLASH_ACR_SLEEP_PD  (3)
 280 #define STM_FLASH_ACR_ACC64     (2)
 281 #define STM_FLASH_ACR_PRFEN     (1)
 282 #define STM_FLASH_ACR_LATENCY   (0)
 283
 284 #define STM_FLASH_PECR_OBL_LAUNCH       18
 285 #define STM_FLASH_PECR_ERRIE            17
 286 #define STM_FLASH_PECR_EOPIE            16
 287 #define STM_FLASH_PECR_FPRG             10
 288 #define STM_FLASH_PECR_ERASE            9
 289 #define STM_FLASH_PECR_FTDW             8
 290 #define STM_FLASH_PECR_DATA             4
 291 #define STM_FLASH_PECR_PROG             3
 292 #define STM_FLASH_PECR_OPTLOCK          2
 293 #define STM_FLASH_PECR_PRGLOCK          1
 294 #define STM_FLASH_PECR_PELOCK           0
 295
 296 #define STM_FLASH_SR_OPTVERR            11
 297 #define STM_FLASH_SR_SIZERR             10
 298 #define STM_FLASH_SR_PGAERR             9
 299 #define STM_FLASH_SR_WRPERR             8
 300 #define STM_FLASH_SR_READY              3
 301 #define STM_FLASH_SR_ENDHV              2
 302 #define STM_FLASH_SR_EOP                1
 303 #define STM_FLASH_SR_BSY                0
 304
 305 #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
 306 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
 307
 308 struct stm_rcc {
 309         vuint32_t       cr;
 310         vuint32_t       icscr;
 311         vuint32_t       cfgr;
 312         vuint32_t       cir;
 313
 314         vuint32_t       ahbrstr;
 315         vuint32_t       apb2rstr;
 316         vuint32_t       apb1rstr;
 317         vuint32_t       ahbenr;
 318
 319         vuint32_t       apb2enr;
 320         vuint32_t       apb1enr;
 321         vuint32_t       ahblenr;
 322         vuint32_t       apb2lpenr;
 323
 324         vuint32_t       apb1lpenr;
 325         vuint32_t       csr;
 326 };
 327
 328 extern struct stm_rcc stm_rcc;
 329
 330 /* Nominal high speed internal oscillator frequency is 16MHz */
 331 #define STM_HSI_FREQ            16000000
 332
 333 #define STM_RCC_CR_RTCPRE       (29)
 334 #define  STM_RCC_CR_RTCPRE_HSE_DIV_2    0
 335 #define  STM_RCC_CR_RTCPRE_HSE_DIV_4    1
 336 #define  STM_RCC_CR_RTCPRE_HSE_DIV_8    2
 337 #define  STM_RCC_CR_RTCPRE_HSE_DIV_16   3
 338 #define  STM_RCC_CR_RTCPRE_HSE_MASK     3
 339
 340 #define STM_RCC_CR_CSSON        (28)
 341 #define STM_RCC_CR_PLLRDY       (25)
 342 #define STM_RCC_CR_PLLON        (24)
 343 #define STM_RCC_CR_HSEBYP       (18)
 344 #define STM_RCC_CR_HSERDY       (17)
 345 #define STM_RCC_CR_HSEON        (16)
 346 #define STM_RCC_CR_MSIRDY       (9)
 347 #define STM_RCC_CR_MSION        (8)
 348 #define STM_RCC_CR_HSIRDY       (1)
 349 #define STM_RCC_CR_HSION        (0)
 350
 351 #define STM_RCC_CFGR_MCOPRE     (28)
 352 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 353 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 354 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 355 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 356 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 357 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7
 358
 359 #define STM_RCC_CFGR_MCOSEL     (24)
 360 #define  STM_RCC_CFGR_MCOSEL_DISABLE    0
 361 #define  STM_RCC_CFGR_MCOSEL_SYSCLK     1
 362 #define  STM_RCC_CFGR_MCOSEL_HSI        2
 363 #define  STM_RCC_CFGR_MCOSEL_MSI        3
 364 #define  STM_RCC_CFGR_MCOSEL_HSE        4
 365 #define  STM_RCC_CFGR_MCOSEL_PLL        5
 366 #define  STM_RCC_CFGR_MCOSEL_LSI        6
 367 #define  STM_RCC_CFGR_MCOSEL_LSE        7
 368 #define  STM_RCC_CFGR_MCOSEL_MASK       7
 369
 370 #define STM_RCC_CFGR_PLLDIV     (22)
 371 #define  STM_RCC_CFGR_PLLDIV_2          1
 372 #define  STM_RCC_CFGR_PLLDIV_3          2
 373 #define  STM_RCC_CFGR_PLLDIV_4          3
 374 #define  STM_RCC_CFGR_PLLDIV_MASK       3
 375
 376 #define STM_RCC_CFGR_PLLMUL     (18)
 377 #define  STM_RCC_CFGR_PLLMUL_3          0
 378 #define  STM_RCC_CFGR_PLLMUL_4          1
 379 #define  STM_RCC_CFGR_PLLMUL_6          2
 380 #define  STM_RCC_CFGR_PLLMUL_8          3
 381 #define  STM_RCC_CFGR_PLLMUL_12         4
 382 #define  STM_RCC_CFGR_PLLMUL_16         5
 383 #define  STM_RCC_CFGR_PLLMUL_24         6
 384 #define  STM_RCC_CFGR_PLLMUL_32         7
 385 #define  STM_RCC_CFGR_PLLMUL_48         8
 386 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 387
 388 #define STM_RCC_CFGR_PLLSRC     (16)
 389
 390 #define STM_RCC_CFGR_PPRE2      (11)
 391 #define  STM_RCC_CFGR_PPRE2_DIV_1       0
 392 #define  STM_RCC_CFGR_PPRE2_DIV_2       4
 393 #define  STM_RCC_CFGR_PPRE2_DIV_4       5
 394 #define  STM_RCC_CFGR_PPRE2_DIV_8       6
 395 #define  STM_RCC_CFGR_PPRE2_DIV_16      7
 396 #define  STM_RCC_CFGR_PPRE2_MASK        7
 397
 398 #define STM_RCC_CFGR_PPRE1      (8)
 399 #define  STM_RCC_CFGR_PPRE1_DIV_1       0
 400 #define  STM_RCC_CFGR_PPRE1_DIV_2       4
 401 #define  STM_RCC_CFGR_PPRE1_DIV_4       5
 402 #define  STM_RCC_CFGR_PPRE1_DIV_8       6
 403 #define  STM_RCC_CFGR_PPRE1_DIV_16      7
 404 #define  STM_RCC_CFGR_PPRE1_MASK        7
 405
 406 #define STM_RCC_CFGR_HPRE       (4)
 407 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 408 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 409 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 410 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 411 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 412 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 413 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 414 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 415 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 416 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 417
 418 #define STM_RCC_CFGR_SWS        (2)
 419 #define  STM_RCC_CFGR_SWS_MSI           0
 420 #define  STM_RCC_CFGR_SWS_HSI           1
 421 #define  STM_RCC_CFGR_SWS_HSE           2
 422 #define  STM_RCC_CFGR_SWS_PLL           3
 423 #define  STM_RCC_CFGR_SWS_MASK          3
 424
 425 #define STM_RCC_CFGR_SW         (0)
 426 #define  STM_RCC_CFGR_SW_MSI            0
 427 #define  STM_RCC_CFGR_SW_HSI            1
 428 #define  STM_RCC_CFGR_SW_HSE            2
 429 #define  STM_RCC_CFGR_SW_PLL            3
 430 #define  STM_RCC_CFGR_SW_MASK           3
 431
 432 #define STM_RCC_AHBENR_DMA1EN           (24)
 433 #define STM_RCC_AHBENR_FLITFEN          (15)
 434 #define STM_RCC_AHBENR_CRCEN            (12)
 435 #define STM_RCC_AHBENR_GPIOHEN          (5)
 436 #define STM_RCC_AHBENR_GPIOEEN          (4)
 437 #define STM_RCC_AHBENR_GPIODEN          (3)
 438 #define STM_RCC_AHBENR_GPIOCEN          (2)
 439 #define STM_RCC_AHBENR_GPIOBEN          (1)
 440 #define STM_RCC_AHBENR_GPIOAEN          (0)
 441
 442 #define STM_RCC_APB2ENR_USART1EN        (14)
 443 #define STM_RCC_APB2ENR_SPI1EN          (12)
 444 #define STM_RCC_APB2ENR_ADC1EN          (9)
 445 #define STM_RCC_APB2ENR_TIM11EN         (4)
 446 #define STM_RCC_APB2ENR_TIM10EN         (3)
 447 #define STM_RCC_APB2ENR_TIM9EN          (2)
 448 #define STM_RCC_APB2ENR_SYSCFGEN        (0)
 449
 450 #define STM_RCC_APB1ENR_COMPEN          (31)
 451 #define STM_RCC_APB1ENR_DACEN           (29)
 452 #define STM_RCC_APB1ENR_PWREN           (28)
 453 #define STM_RCC_APB1ENR_USBEN           (23)
 454 #define STM_RCC_APB1ENR_I2C2EN          (22)
 455 #define STM_RCC_APB1ENR_I2C1EN          (21)
 456 #define STM_RCC_APB1ENR_USART3EN        (18)
 457 #define STM_RCC_APB1ENR_USART2EN        (17)
 458 #define STM_RCC_APB1ENR_SPI2EN          (14)
 459 #define STM_RCC_APB1ENR_WWDGEN          (11)
 460 #define STM_RCC_APB1ENR_LCDEN           (9)
 461 #define STM_RCC_APB1ENR_TIM7EN          (5)
 462 #define STM_RCC_APB1ENR_TIM6EN          (4)
 463 #define STM_RCC_APB1ENR_TIM4EN          (2)
 464 #define STM_RCC_APB1ENR_TIM3EN          (1)
 465 #define STM_RCC_APB1ENR_TIM2EN          (0)
 466
 467 #define STM_RCC_CSR_LPWRRSTF            (31)
 468 #define STM_RCC_CSR_WWDGRSTF            (30)
 469 #define STM_RCC_CSR_IWDGRSTF            (29)
 470 #define STM_RCC_CSR_SFTRSTF             (28)
 471 #define STM_RCC_CSR_PORRSTF             (27)
 472 #define STM_RCC_CSR_PINRSTF             (26)
 473 #define STM_RCC_CSR_OBLRSTF             (25)
 474 #define STM_RCC_CSR_RMVF                (24)
 475 #define STM_RCC_CSR_RTFRST              (23)
 476 #define STM_RCC_CSR_RTCEN               (22)
 477 #define STM_RCC_CSR_RTCSEL              (16)
 478
 479 #define  STM_RCC_CSR_RTCSEL_NONE                0
 480 #define  STM_RCC_CSR_RTCSEL_LSE                 1
 481 #define  STM_RCC_CSR_RTCSEL_LSI                 2
 482 #define  STM_RCC_CSR_RTCSEL_HSE                 3
 483 #define  STM_RCC_CSR_RTCSEL_MASK                3
 484
 485 #define STM_RCC_CSR_LSEBYP              (10)
 486 #define STM_RCC_CSR_LSERDY              (9)
 487 #define STM_RCC_CSR_LSEON               (8)
 488 #define STM_RCC_CSR_LSIRDY              (1)
 489 #define STM_RCC_CSR_LSION               (0)
 490
 491 struct stm_pwr {
 492         vuint32_t       cr;
 493         vuint32_t       csr;
 494 };
 495
 496 extern struct stm_pwr stm_pwr;
 497
 498 #define STM_PWR_CR_LPRUN        (14)
 499
 500 #define STM_PWR_CR_VOS          (11)
 501 #define  STM_PWR_CR_VOS_1_8             1
 502 #define  STM_PWR_CR_VOS_1_5             2
 503 #define  STM_PWR_CR_VOS_1_2             3
 504 #define  STM_PWR_CR_VOS_MASK            3
 505
 506 #define STM_PWR_CR_FWU          (10)
 507 #define STM_PWR_CR_ULP          (9)
 508 #define STM_PWR_CR_DBP          (8)
 509
 510 #define STM_PWR_CR_PLS          (5)
 511 #define  STM_PWR_CR_PLS_1_9     0
 512 #define  STM_PWR_CR_PLS_2_1     1
 513 #define  STM_PWR_CR_PLS_2_3     2
 514 #define  STM_PWR_CR_PLS_2_5     3
 515 #define  STM_PWR_CR_PLS_2_7     4
 516 #define  STM_PWR_CR_PLS_2_9     5
 517 #define  STM_PWR_CR_PLS_3_1     6
 518 #define  STM_PWR_CR_PLS_EXT     7
 519 #define  STM_PWR_CR_PLS_MASK    7
 520
 521 #define STM_PWR_CR_PVDE         (4)
 522 #define STM_PWR_CR_CSBF         (3)
 523 #define STM_PWR_CR_CWUF         (2)
 524 #define STM_PWR_CR_PDDS         (1)
 525 #define STM_PWR_CR_LPSDSR       (0)
 526
 527 #define STM_PWR_CSR_EWUP3       (10)
 528 #define STM_PWR_CSR_EWUP2       (9)
 529 #define STM_PWR_CSR_EWUP1       (8)
 530 #define STM_PWR_CSR_REGLPF      (5)
 531 #define STM_PWR_CSR_VOSF        (4)
 532 #define STM_PWR_CSR_VREFINTRDYF (3)
 533 #define STM_PWR_CSR_PVDO        (2)
 534 #define STM_PWR_CSR_SBF         (1)
 535 #define STM_PWR_CSR_WUF         (0)
 536
 537 struct stm_tim67 {
 538         vuint32_t       cr1;
 539         vuint32_t       cr2;
 540         uint32_t        _unused_08;
 541         vuint32_t       dier;
 542
 543         vuint32_t       sr;
 544         vuint32_t       egr;
 545         uint32_t        _unused_18;
 546         uint32_t        _unused_1c;
 547
 548         uint32_t        _unused_20;
 549         vuint32_t       cnt;
 550         vuint32_t       psc;
 551         vuint32_t       arr;
 552 };
 553
 554 extern struct stm_tim67 stm_tim6;
 555
 556 #define STM_TIM67_CR1_ARPE      (7)
 557 #define STM_TIM67_CR1_OPM       (3)
 558 #define STM_TIM67_CR1_URS       (2)
 559 #define STM_TIM67_CR1_UDIS      (1)
 560 #define STM_TIM67_CR1_CEN       (0)
 561
 562 #define STM_TIM67_CR2_MMS       (4)
 563 #define  STM_TIM67_CR2_MMS_RESET        0
 564 #define  STM_TIM67_CR2_MMS_ENABLE       1
 565 #define  STM_TIM67_CR2_MMS_UPDATE       2
 566 #define  STM_TIM67_CR2_MMS_MASK         7
 567
 568 #define STM_TIM67_DIER_UDE      (8)
 569 #define STM_TIM67_DIER_UIE      (0)
 570
 571 #define STM_TIM67_SR_UIF        (0)
 572
 573 #define STM_TIM67_EGR_UG        (0)
 574
 575 struct stm_lcd {
 576         vuint32_t       cr;
 577         vuint32_t       fcr;
 578         vuint32_t       sr;
 579         vuint32_t       clr;
 580         uint32_t        unused_0x10;
 581         vuint32_t       ram[8*2];
 582 };
 583
 584 extern struct stm_lcd stm_lcd;
 585
 586 #define STM_LCD_CR_MUX_SEG              (7)
 587
 588 #define STM_LCD_CR_BIAS                 (5)
 589 #define  STM_LCD_CR_BIAS_1_4            0
 590 #define  STM_LCD_CR_BIAS_1_2            1
 591 #define  STM_LCD_CR_BIAS_1_3            2
 592 #define  STM_LCD_CR_BIAS_MASK           3
 593
 594 #define STM_LCD_CR_DUTY                 (2)
 595 #define  STM_LCD_CR_DUTY_STATIC         0
 596 #define  STM_LCD_CR_DUTY_1_2            1
 597 #define  STM_LCD_CR_DUTY_1_3            2
 598 #define  STM_LCD_CR_DUTY_1_4            3
 599 #define  STM_LCD_CR_DUTY_1_8            4
 600 #define  STM_LCD_CR_DUTY_MASK           7
 601
 602 #define STM_LCD_CR_VSEL                 (1)
 603 #define STM_LCD_CR_LCDEN                (0)
 604
 605 #define STM_LCD_FCR_PS                  (22)
 606 #define  STM_LCD_FCR_PS_1               0x0
 607 #define  STM_LCD_FCR_PS_2               0x1
 608 #define  STM_LCD_FCR_PS_4               0x2
 609 #define  STM_LCD_FCR_PS_8               0x3
 610 #define  STM_LCD_FCR_PS_16              0x4
 611 #define  STM_LCD_FCR_PS_32              0x5
 612 #define  STM_LCD_FCR_PS_64              0x6
 613 #define  STM_LCD_FCR_PS_128             0x7
 614 #define  STM_LCD_FCR_PS_256             0x8
 615 #define  STM_LCD_FCR_PS_512             0x9
 616 #define  STM_LCD_FCR_PS_1024            0xa
 617 #define  STM_LCD_FCR_PS_2048            0xb
 618 #define  STM_LCD_FCR_PS_4096            0xc
 619 #define  STM_LCD_FCR_PS_8192            0xd
 620 #define  STM_LCD_FCR_PS_16384           0xe
 621 #define  STM_LCD_FCR_PS_32768           0xf
 622 #define  STM_LCD_FCR_PS_MASK            0xf
 623
 624 #define STM_LCD_FCR_DIV                 (18)
 625 #define STM_LCD_FCR_DIV_16              0x0
 626 #define STM_LCD_FCR_DIV_17              0x1
 627 #define STM_LCD_FCR_DIV_18              0x2
 628 #define STM_LCD_FCR_DIV_19              0x3
 629 #define STM_LCD_FCR_DIV_20              0x4
 630 #define STM_LCD_FCR_DIV_21              0x5
 631 #define STM_LCD_FCR_DIV_22              0x6
 632 #define STM_LCD_FCR_DIV_23              0x7
 633 #define STM_LCD_FCR_DIV_24              0x8
 634 #define STM_LCD_FCR_DIV_25              0x9
 635 #define STM_LCD_FCR_DIV_26              0xa
 636 #define STM_LCD_FCR_DIV_27              0xb
 637 #define STM_LCD_FCR_DIV_28              0xc
 638 #define STM_LCD_FCR_DIV_29              0xd
 639 #define STM_LCD_FCR_DIV_30              0xe
 640 #define STM_LCD_FCR_DIV_31              0xf
 641 #define STM_LCD_FCR_DIV_MASK            0xf
 642
 643 #define STM_LCD_FCR_BLINK               (16)
 644 #define  STM_LCD_FCR_BLINK_DISABLE              0
 645 #define  STM_LCD_FCR_BLINK_SEG0_COM0            1
 646 #define  STM_LCD_FCR_BLINK_SEG0_COMALL          2
 647 #define  STM_LCD_FCR_BLINK_SEGALL_COMALL        3
 648 #define  STM_LCD_FCR_BLINK_MASK                 3
 649
 650 #define STM_LCD_FCR_BLINKF              (13)
 651 #define  STM_LCD_FCR_BLINKF_8                   0
 652 #define  STM_LCD_FCR_BLINKF_16                  1
 653 #define  STM_LCD_FCR_BLINKF_32                  2
 654 #define  STM_LCD_FCR_BLINKF_64                  3
 655 #define  STM_LCD_FCR_BLINKF_128                 4
 656 #define  STM_LCD_FCR_BLINKF_256                 5
 657 #define  STM_LCD_FCR_BLINKF_512                 6
 658 #define  STM_LCD_FCR_BLINKF_1024                7
 659 #define  STM_LCD_FCR_BLINKF_MASK                7
 660
 661 #define STM_LCD_FCR_CC                  (10)
 662 #define  STM_LCD_FCR_CC_MASK                    7
 663
 664 #define STM_LCD_FCR_DEAD                (7)
 665 #define  STM_LCD_FCR_DEAD_MASK                  7
 666
 667 #define STM_LCD_FCR_PON                 (4)
 668 #define  STM_LCD_FCR_PON_MASK                   7
 669
 670 #define STM_LCD_FCR_UDDIE               (3)
 671 #define STM_LCD_FCR_SOFIE               (1)
 672 #define STM_LCD_FCR_HD                  (0)
 673
 674 #define STM_LCD_SR_FCRSF                (5)
 675 #define STM_LCD_SR_RDY                  (4)
 676 #define STM_LCD_SR_UDD                  (3)
 677 #define STM_LCD_SR_UDR                  (2)
 678 #define STM_LCD_SR_SOF                  (1)
 679 #define STM_LCD_SR_ENS                  (0)
 680
 681 #define STM_LCD_CLR_UDDC                (3)
 682 #define STM_LCD_CLR_SOFC                (1)
 683
 684 struct stm_nvic {
 685         vuint32_t       iser[3];        /* 0x000 */
 686
 687         uint8_t         _unused00c[0x080 - 0x00c];
 688
 689         vuint32_t       icer[3];        /* 0x080 */
 690
 691         uint8_t         _unused08c[0x100 - 0x08c];
 692
 693         vuint32_t       ispr[3];        /* 0x100 */
 694
 695         uint8_t         _unused10c[0x180 - 0x10c];
 696
 697         vuint32_t       icpr[3];        /* 0x180 */
 698
 699         uint8_t         _unused18c[0x200 - 0x18c];
 700
 701         vuint32_t       iabr[3];        /* 0x200 */
 702
 703         uint8_t         _unused20c[0x300 - 0x20c];
 704
 705         vuint32_t       ipr[21];        /* 0x300 */
 706
 707         uint8_t         _unused324[0xe00 - 0x324];
 708
 709         vuint32_t       stir;           /* 0xe00 */
 710 };
 711
 712 extern struct stm_nvic stm_nvic;
 713
 714 #define IRQ_REG(irq)    ((irq) >> 5)
 715 #define IRQ_BIT(irq)    ((irq) & 0x1f)
 716 #define IRQ_MASK(irq)   (1 << IRQ_BIT(irq))
 717 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
 718
 719 static inline void
 720 stm_nvic_set_enable(int irq) {
 721         stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
 722 }
 723
 724 static inline void
 725 stm_nvic_clear_enable(int irq) {
 726         stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
 727 }
 728
 729 static inline int
 730 stm_nvic_enabled(int irq) {
 731         return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
 732 }
 733
 734 static inline void
 735 stm_nvic_set_pending(int irq) {
 736         stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
 737 }
 738
 739 static inline void
 740 stm_nvic_clear_pending(int irq) {
 741         stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
 742 }
 743
 744 static inline int
 745 stm_nvic_pending(int irq) {
 746         return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
 747 }
 748
 749 static inline int
 750 stm_nvic_active(int irq) {
 751         return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
 752 }
 753
 754 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 755 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 756 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 757
 758 static inline void
 759 stm_nvic_set_priority(int irq, uint8_t prio) {
 760         int             n = IRQ_PRIO_REG(irq);
 761         uint32_t        v;
 762
 763         v = stm_nvic.ipr[n];
 764         v &= ~IRQ_PRIO_MASK(irq);
 765         v |= (prio) << IRQ_PRIO_BIT(irq);
 766         stm_nvic.ipr[n] = v;
 767 }
 768
 769 static inline uint8_t
 770 stm_nvic_get_priority(int irq) {
 771         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 772 }
 773
 774 #define isr(name) void stm_ ## name ## _isr(void);
 775
 776 isr(nmi)
 777 isr(hardfault)
 778 isr(memmanage)
 779 isr(busfault)
 780 isr(usagefault)
 781 isr(svc)
 782 isr(debugmon)
 783 isr(pendsv)
 784 isr(systick)
 785 isr(wwdg)
 786 isr(pvd)
 787 isr(tamper_stamp)
 788 isr(rtc_wkup)
 789 isr(flash)
 790 isr(rcc)
 791 isr(exti0)
 792 isr(exti1)
 793 isr(exti2)
 794 isr(exti3)
 795 isr(exti4)
 796 isr(dma1_channel1)
 797 isr(dma1_channel2)
 798 isr(dma1_channel3)
 799 isr(dma1_channel4)
 800 isr(dma1_channel5)
 801 isr(dma1_channel6)
 802 isr(dma1_channel7)
 803 isr(adc1)
 804 isr(usb_hp)
 805 isr(usb_lp)
 806 isr(dac)
 807 isr(comp)
 808 isr(exti9_5)
 809 isr(lcd)
 810 isr(tim9)
 811 isr(tim10)
 812 isr(tim11)
 813 isr(tim2)
 814 isr(tim3)
 815 isr(tim4)
 816 isr(i2c1_ev)
 817 isr(i2c1_er)
 818 isr(i2c2_ev)
 819 isr(i2c2_er)
 820 isr(spi1)
 821 isr(spi2)
 822 isr(usart1)
 823 isr(usart2)
 824 isr(usart3)
 825 isr(exti15_10)
 826 isr(rtc_alarm)
 827 isr(usb_fs_wkup)
 828 isr(tim6)
 829 isr(tim7)
 830
 831 #undef isr
 832
 833 #define STM_ISR_WWDG_POS                0
 834 #define STM_ISR_PVD_POS                 1
 835 #define STM_ISR_TAMPER_STAMP_POS        2
 836 #define STM_ISR_RTC_WKUP_POS            3
 837 #define STM_ISR_FLASH_POS               4
 838 #define STM_ISR_RCC_POS                 5
 839 #define STM_ISR_EXTI0_POS               6
 840 #define STM_ISR_EXTI1_POS               7
 841 #define STM_ISR_EXTI2_POS               8
 842 #define STM_ISR_EXTI3_POS               9
 843 #define STM_ISR_EXTI4_POS               10
 844 #define STM_ISR_DMA1_CHANNEL1_POS       11
 845 #define STM_ISR_DMA2_CHANNEL1_POS       12
 846 #define STM_ISR_DMA3_CHANNEL1_POS       13
 847 #define STM_ISR_DMA4_CHANNEL1_POS       14
 848 #define STM_ISR_DMA5_CHANNEL1_POS       15
 849 #define STM_ISR_DMA6_CHANNEL1_POS       16
 850 #define STM_ISR_DMA7_CHANNEL1_POS       17
 851 #define STM_ISR_ADC1_POS                18
 852 #define STM_ISR_USB_HP_POS              19
 853 #define STM_ISR_USB_LP_POS              20
 854 #define STM_ISR_DAC_POS                 21
 855 #define STM_ISR_COMP_POS                22
 856 #define STM_ISR_EXTI9_5_POS             23
 857 #define STM_ISR_LCD_POS                 24
 858 #define STM_ISR_TIM9_POS                25
 859 #define STM_ISR_TIM10_POS               26
 860 #define STM_ISR_TIM11_POS               27
 861 #define STM_ISR_TIM2_POS                28
 862 #define STM_ISR_TIM3_POS                29
 863 #define STM_ISR_TIM4_POS                30
 864 #define STM_ISR_I2C1_EV_POS             31
 865 #define STM_ISR_I2C1_ER_POS             32
 866 #define STM_ISR_I2C2_EV_POS             33
 867 #define STM_ISR_I2C2_ER_POS             34
 868 #define STM_ISR_SPI1_POS                35
 869 #define STM_ISR_SPI2_POS                36
 870 #define STM_ISR_USART1_POS              37
 871 #define STM_ISR_USART2_POS              38
 872 #define STM_ISR_USART3_POS              39
 873 #define STM_ISR_EXTI15_10_POS           40
 874 #define STM_ISR_RTC_ALARM_POS           41
 875 #define STM_ISR_USB_FS_WKUP_POS         42
 876 #define STM_ISR_TIM6_POS                43
 877 #define STM_ISR_TIM7_POS                44
 878
 879 struct stm_syscfg {
 880         vuint32_t       memrmp;
 881         vuint32_t       pmc;
 882         vuint32_t       exticr[4];
 883 };
 884
 885 extern struct stm_syscfg stm_syscfg;
 886
 887 #define STM_SYSCFG_MEMRMP_MEM_MODE      0
 888 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH          0
 889 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH        1
 890 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SRAM                3
 891 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MASK                3
 892
 893 #define STM_SYSCFG_PMC_USB_PU           0
 894
 895 #define STM_SYSCFG_EXTICR_PA            0
 896 #define STM_SYSCFG_EXTICR_PB            1
 897 #define STM_SYSCFG_EXTICR_PC            2
 898 #define STM_SYSCFG_EXTICR_PD            3
 899 #define STM_SYSCFG_EXTICR_PE            4
 900 #define STM_SYSCFG_EXTICR_PH            5
 901
 902 static inline void
 903 stm_exticr_set(struct stm_gpio *gpio, int pin) {
 904         uint8_t reg = pin >> 2;
 905         uint8_t shift = (pin & 3) << 2;
 906         uint8_t val = 0;
 907
 908         if (gpio == &stm_gpioa)
 909                 val = STM_SYSCFG_EXTICR_PA;
 910         else if (gpio == &stm_gpiob)
 911                 val = STM_SYSCFG_EXTICR_PB;
 912         else if (gpio == &stm_gpioc)
 913                 val = STM_SYSCFG_EXTICR_PC;
 914         else if (gpio == &stm_gpiod)
 915                 val = STM_SYSCFG_EXTICR_PD;
 916         else if (gpio == &stm_gpioe)
 917                 val = STM_SYSCFG_EXTICR_PE;
 918
 919         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
 920 }
 921
 922
 923 struct stm_dma_channel {
 924         vuint32_t       ccr;
 925         vuint32_t       cndtr;
 926         vvoid_t         cpar;
 927         vvoid_t         cmar;
 928         vuint32_t       reserved;
 929 };
 930
 931 #define STM_NUM_DMA     7
 932
 933 struct stm_dma {
 934         vuint32_t               isr;
 935         vuint32_t               ifcr;
 936         struct stm_dma_channel  channel[STM_NUM_DMA];
 937 };
 938
 939 extern struct stm_dma stm_dma;
 940
 941 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
 942  */
 943
 944 #define STM_DMA_INDEX(channel)          ((channel) - 1)
 945
 946 #define STM_DMA_ISR(index)              ((index) << 2)
 947 #define STM_DMA_ISR_MASK                        0xf
 948 #define STM_DMA_ISR_TEIF                        3
 949 #define STM_DMA_ISR_HTIF                        2
 950 #define STM_DMA_ISR_TCIF                        1
 951 #define STM_DMA_ISR_GIF                         0
 952
 953 #define STM_DMA_IFCR(index)             ((index) << 2)
 954 #define STM_DMA_IFCR_MASK                       0xf
 955 #define STM_DMA_IFCR_CTEIF                      3
 956 #define STM_DMA_IFCR_CHTIF                      2
 957 #define STM_DMA_IFCR_CTCIF                      1
 958 #define STM_DMA_IFCR_CGIF                       0
 959
 960 #define STM_DMA_CCR_MEM2MEM             (14)
 961
 962 #define STM_DMA_CCR_PL                  (12)
 963 #define  STM_DMA_CCR_PL_LOW                     (0)
 964 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
 965 #define  STM_DMA_CCR_PL_HIGH                    (2)
 966 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
 967 #define  STM_DMA_CCR_PL_MASK                    (3)
 968
 969 #define STM_DMA_CCR_MSIZE               (10)
 970 #define  STM_DMA_CCR_MSIZE_8                    (0)
 971 #define  STM_DMA_CCR_MSIZE_16                   (1)
 972 #define  STM_DMA_CCR_MSIZE_32                   (2)
 973 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
 974
 975 #define STM_DMA_CCR_PSIZE               (8)
 976 #define  STM_DMA_CCR_PSIZE_8                    (0)
 977 #define  STM_DMA_CCR_PSIZE_16                   (1)
 978 #define  STM_DMA_CCR_PSIZE_32                   (2)
 979 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
 980
 981 #define STM_DMA_CCR_MINC                (7)
 982 #define STM_DMA_CCR_PINC                (6)
 983 #define STM_DMA_CCR_CIRC                (5)
 984 #define STM_DMA_CCR_DIR                 (4)
 985 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
 986 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
 987 #define STM_DMA_CCR_TEIE                (3)
 988 #define STM_DMA_CCR_HTIE                (2)
 989 #define STM_DMA_CCR_TCIE                (1)
 990 #define STM_DMA_CCR_EN                  (0)
 991
 992 #define STM_DMA_CHANNEL_ADC1            1
 993 #define STM_DMA_CHANNEL_SPI1_RX         2
 994 #define STM_DMA_CHANNEL_SPI1_TX         3
 995 #define STM_DMA_CHANNEL_SPI2_RX         4
 996 #define STM_DMA_CHANNEL_SPI2_TX         5
 997 #define STM_DMA_CHANNEL_USART3_TX       2
 998 #define STM_DMA_CHANNEL_USART3_RX       3
 999 #define STM_DMA_CHANNEL_USART1_TX       4
1000 #define STM_DMA_CHANNEL_USART1_RX       5
1001 #define STM_DMA_CHANNEL_USART2_RX       6
1002 #define STM_DMA_CHANNEL_USART2_TX       7
1003 #define STM_DMA_CHANNEL_I2C2_TX         4
1004 #define STM_DMA_CHANNEL_I2C2_RX         5
1005 #define STM_DMA_CHANNEL_I2C1_TX         6
1006 #define STM_DMA_CHANNEL_I2C1_RX         7
1007 #define STM_DMA_CHANNEL_TIM2_CH3        1
1008 #define STM_DMA_CHANNEL_TIM2_UP         2
1009 #define STM_DMA_CHANNEL_TIM2_CH1        5
1010 #define STM_DMA_CHANNEL_TIM2_CH2        7
1011 #define STM_DMA_CHANNEL_TIM2_CH4        7
1012 #define STM_DMA_CHANNEL_TIM3_CH3        2
1013 #define STM_DMA_CHANNEL_TIM3_CH4        3
1014 #define STM_DMA_CHANNEL_TIM3_UP         3
1015 #define STM_DMA_CHANNEL_TIM3_CH1        6
1016 #define STM_DMA_CHANNEL_TIM3_TRIG       6
1017 #define STM_DMA_CHANNEL_TIM4_CH1        1
1018 #define STM_DMA_CHANNEL_TIM4_CH2        4
1019 #define STM_DMA_CHANNEL_TIM4_CH3        5
1020 #define STM_DMA_CHANNEL_TIM4_UP         7
1021 #define STM_DMA_CHANNEL_TIM6_UP_DA      2
1022 #define STM_DMA_CHANNEL_C_CHANNEL1      2
1023 #define STM_DMA_CHANNEL_TIM7_UP_DA      3
1024 #define STM_DMA_CHANNEL_C_CHANNEL2      3
1025
1026 /*
1027  * Only spi channel 1 and 2 can use DMA
1028  */
1029 #define STM_NUM_SPI     2
1030
1031 struct stm_spi {
1032         vuint32_t       cr1;
1033         vuint32_t       cr2;
1034         vuint32_t       sr;
1035         vuint32_t       dr;
1036         vuint32_t       crcpr;
1037         vuint32_t       rxcrcr;
1038         vuint32_t       txcrcr;
1039 };
1040
1041 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1042
1043 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1044  */
1045
1046 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1047
1048 #define STM_SPI_CR1_BIDIMODE            15
1049 #define STM_SPI_CR1_BIDIOE              14
1050 #define STM_SPI_CR1_CRCEN               13
1051 #define STM_SPI_CR1_CRCNEXT             12
1052 #define STM_SPI_CR1_DFF                 11
1053 #define STM_SPI_CR1_RXONLY              10
1054 #define STM_SPI_CR1_SSM                 9
1055 #define STM_SPI_CR1_SSI                 8
1056 #define STM_SPI_CR1_LSBFIRST            7
1057 #define STM_SPI_CR1_SPE                 6
1058 #define STM_SPI_CR1_BR                  3
1059 #define  STM_SPI_CR1_BR_PCLK_2                  0
1060 #define  STM_SPI_CR1_BR_PCLK_4                  1
1061 #define  STM_SPI_CR1_BR_PCLK_8                  2
1062 #define  STM_SPI_CR1_BR_PCLK_16                 3
1063 #define  STM_SPI_CR1_BR_PCLK_32                 4
1064 #define  STM_SPI_CR1_BR_PCLK_64                 5
1065 #define  STM_SPI_CR1_BR_PCLK_128                6
1066 #define  STM_SPI_CR1_BR_PCLK_256                7
1067 #define  STM_SPI_CR1_BR_MASK                    7
1068
1069 #define STM_SPI_CR1_MSTR                2
1070 #define STM_SPI_CR1_CPOL                1
1071 #define STM_SPI_CR1_CPHA                0
1072
1073 #define STM_SPI_CR2_TXEIE       7
1074 #define STM_SPI_CR2_RXNEIE      6
1075 #define STM_SPI_CR2_ERRIE       5
1076 #define STM_SPI_CR2_SSOE        2
1077 #define STM_SPI_CR2_TXDMAEN     1
1078 #define STM_SPI_CR2_RXDMAEN     0
1079
1080 #define STM_SPI_SR_BSY          7
1081 #define STM_SPI_SR_OVR          6
1082 #define STM_SPI_SR_MODF         5
1083 #define STM_SPI_SR_CRCERR       4
1084 #define STM_SPI_SR_TXE          1
1085 #define STM_SPI_SR_RXNE         0
1086
1087 struct stm_adc {
1088         vuint32_t       sr;
1089         vuint32_t       cr1;
1090         vuint32_t       cr2;
1091         vuint32_t       smpr1;
1092         vuint32_t       smpr2;
1093         vuint32_t       smpr3;
1094         vuint32_t       jofr1;
1095         vuint32_t       jofr2;
1096         vuint32_t       jofr3;
1097         vuint32_t       jofr4;
1098         vuint32_t       htr;
1099         vuint32_t       ltr;
1100         vuint32_t       sqr1;
1101         vuint32_t       sqr2;
1102         vuint32_t       sqr3;
1103         vuint32_t       sqr4;
1104         vuint32_t       sqr5;
1105         vuint32_t       jsqr;
1106         vuint32_t       jdr1;
1107         vuint32_t       jdr2;
1108         vuint32_t       jdr3;
1109         vuint32_t       jdr4;
1110         vuint32_t       dr;
1111         uint8_t         reserved[0x300 - 0x5c];
1112         vuint32_t       csr;
1113         vuint32_t       ccr;
1114 };
1115
1116 extern struct stm_adc stm_adc;
1117
1118 #define STM_ADC_SR_JCNR         9
1119 #define STM_ADC_SR_RCNR         8
1120 #define STM_ADC_SR_ADONS        6
1121 #define STM_ADC_SR_OVR          5
1122 #define STM_ADC_SR_STRT         4
1123 #define STM_ADC_SR_JSTRT        3
1124 #define STM_ADC_SR_JEOC         2
1125 #define STM_ADC_SR_EOC          1
1126 #define STM_ADC_SR_AWD          0
1127
1128 #define STM_ADC_CR1_OVRIE       26
1129 #define STM_ADC_CR1_RES         24
1130 #define  STM_ADC_CR1_RES_12             0
1131 #define  STM_ADC_CR1_RES_10             1
1132 #define  STM_ADC_CR1_RES_8              2
1133 #define  STM_ADC_CR1_RES_6              3
1134 #define  STM_ADC_CR1_RES_MASK           3
1135 #define STM_ADC_CR1_AWDEN       23
1136 #define STM_ADC_CR1_JAWDEN      22
1137 #define STM_ADC_CR1_PDI         17
1138 #define STM_ADC_CR1_PDD         16
1139 #define STM_ADC_CR1_DISCNUM     13
1140 #define  STM_ADC_CR1_DISCNUM_1          0
1141 #define  STM_ADC_CR1_DISCNUM_2          1
1142 #define  STM_ADC_CR1_DISCNUM_3          2
1143 #define  STM_ADC_CR1_DISCNUM_4          3
1144 #define  STM_ADC_CR1_DISCNUM_5          4
1145 #define  STM_ADC_CR1_DISCNUM_6          5
1146 #define  STM_ADC_CR1_DISCNUM_7          6
1147 #define  STM_ADC_CR1_DISCNUM_8          7
1148 #define  STM_ADC_CR1_DISCNUM_MASK       7
1149 #define STM_ADC_CR1_JDISCEN     12
1150 #define STM_ADC_CR1_DISCEN      11
1151 #define STM_ADC_CR1_JAUTO       10
1152 #define STM_ADC_CR1_AWDSGL      9
1153 #define STM_ADC_CR1_SCAN        8
1154 #define STM_ADC_CR1_JEOCIE      7
1155 #define STM_ADC_CR1_AWDIE       6
1156 #define STM_ADC_CR1_EOCIE       5
1157 #define STM_ADC_CR1_AWDCH       0
1158 #define  STM_ADC_CR1_AWDCH_MASK         0x1f
1159
1160 #define STM_ADC_CR2_SWSTART     30
1161 #define STM_ADC_CR2_EXTEN       28
1162 #define  STM_ADC_CR2_EXTEN_DISABLE      0
1163 #define  STM_ADC_CR2_EXTEN_RISING       1
1164 #define  STM_ADC_CR2_EXTEN_FALLING      2
1165 #define  STM_ADC_CR2_EXTEN_BOTH         3
1166 #define  STM_ADC_CR2_EXTEN_MASK         3
1167 #define STM_ADC_CR2_EXTSEL      24
1168 #define  STM_ADC_CR2_EXTSEL_TIM9_CC2    0
1169 #define  STM_ADC_CR2_EXTSEL_TIM9_TRGO   1
1170 #define  STM_ADC_CR2_EXTSEL_TIM2_CC3    2
1171 #define  STM_ADC_CR2_EXTSEL_TIM2_CC2    3
1172 #define  STM_ADC_CR2_EXTSEL_TIM3_TRGO   4
1173 #define  STM_ADC_CR2_EXTSEL_TIM4_CC4    5
1174 #define  STM_ADC_CR2_EXTSEL_TIM2_TRGO   6
1175 #define  STM_ADC_CR2_EXTSEL_TIM3_CC1    7
1176 #define  STM_ADC_CR2_EXTSEL_TIM3_CC3    8
1177 #define  STM_ADC_CR2_EXTSEL_TIM4_TRGO   9
1178 #define  STM_ADC_CR2_EXTSEL_TIM6_TRGO   10
1179 #define  STM_ADC_CR2_EXTSEL_EXTI_11     15
1180 #define  STM_ADC_CR2_EXTSEL_MASK        15
1181 #define STM_ADC_CR2_JWSTART     22
1182 #define STM_ADC_CR2_JEXTEN      20
1183 #define  STM_ADC_CR2_JEXTEN_DISABLE     0
1184 #define  STM_ADC_CR2_JEXTEN_RISING      1
1185 #define  STM_ADC_CR2_JEXTEN_FALLING     2
1186 #define  STM_ADC_CR2_JEXTEN_BOTH        3
1187 #define  STM_ADC_CR2_JEXTEN_MASK        3
1188 #define STM_ADC_CR2_JEXTSEL     16
1189 #define  STM_ADC_CR2_JEXTSEL_TIM9_CC1   0
1190 #define  STM_ADC_CR2_JEXTSEL_TIM9_TRGO  1
1191 #define  STM_ADC_CR2_JEXTSEL_TIM2_TRGO  2
1192 #define  STM_ADC_CR2_JEXTSEL_TIM2_CC1   3
1193 #define  STM_ADC_CR2_JEXTSEL_TIM3_CC4   4
1194 #define  STM_ADC_CR2_JEXTSEL_TIM4_TRGO  5
1195 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC1   6
1196 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC2   7
1197 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC3   8
1198 #define  STM_ADC_CR2_JEXTSEL_TIM10_CC1  9
1199 #define  STM_ADC_CR2_JEXTSEL_TIM7_TRGO  10
1200 #define  STM_ADC_CR2_JEXTSEL_EXTI_15    15
1201 #define  STM_ADC_CR2_JEXTSEL_MASK       15
1202 #define STM_ADC_CR2_ALIGN       11
1203 #define STM_ADC_CR2_EOCS        10
1204 #define STM_ADC_CR2_DDS         9
1205 #define STM_ADC_CR2_DMA         8
1206 #define STM_ADC_CR2_DELS        4
1207 #define  STM_ADC_CR2_DELS_NONE          0
1208 #define  STM_ADC_CR2_DELS_UNTIL_READ    1
1209 #define  STM_ADC_CR2_DELS_7             2
1210 #define  STM_ADC_CR2_DELS_15            3
1211 #define  STM_ADC_CR2_DELS_31            4
1212 #define  STM_ADC_CR2_DELS_63            5
1213 #define  STM_ADC_CR2_DELS_127           6
1214 #define  STM_ADC_CR2_DELS_255           7
1215 #define  STM_ADC_CR2_DELS_MASK          7
1216 #define STM_ADC_CR2_CONT        1
1217 #define STM_ADC_CR2_ADON        0
1218
1219 #define STM_ADC_CCR_TSVREFE     23
1220 #define STM_ADC_CCR_ADCPRE      16
1221 #define  STM_ADC_CCR_ADCPRE_HSI_1       0
1222 #define  STM_ADC_CCR_ADCPRE_HSI_2       1
1223 #define  STM_ADC_CCR_ADCPRE_HSI_4       2
1224 #define  STM_ADC_CCR_ADCPRE_MASK        3
1225
1226 struct stm_temp_cal {
1227         uint16_t        vref;
1228         uint16_t        ts_cal_cold;
1229         uint16_t        reserved;
1230         uint16_t        ts_cal_hot;
1231 };
1232
1233 extern struct stm_temp_cal      stm_temp_cal;
1234
1235 #define stm_temp_cal_cold       25
1236 #define stm_temp_cal_hot        110
1237
1238 #define STM_NUM_I2C     2
1239
1240 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1241
1242 struct stm_i2c {
1243         vuint32_t       cr1;
1244         vuint32_t       cr2;
1245         vuint32_t       oar1;
1246         vuint32_t       oar2;
1247         vuint32_t       dr;
1248         vuint32_t       sr1;
1249         vuint32_t       sr2;
1250         vuint32_t       ccr;
1251         vuint32_t       trise;
1252 };
1253
1254 extern struct stm_i2c stm_i2c1, stm_i2c2;
1255
1256 #define STM_I2C_CR1_SWRST       15
1257 #define STM_I2C_CR1_ALERT       13
1258 #define STM_I2C_CR1_PEC         12
1259 #define STM_I2C_CR1_POS         11
1260 #define STM_I2C_CR1_ACK         10
1261 #define STM_I2C_CR1_STOP        9
1262 #define STM_I2C_CR1_START       8
1263 #define STM_I2C_CR1_NOSTRETCH   7
1264 #define STM_I2C_CR1_ENGC        6
1265 #define STM_I2C_CR1_ENPEC       5
1266 #define STM_I2C_CR1_ENARP       4
1267 #define STM_I2C_CR1_SMBTYPE     3
1268 #define STM_I2C_CR1_SMBUS       1
1269 #define STM_I2C_CR1_PE          0
1270
1271 #define STM_I2C_CR2_LAST        12
1272 #define STM_I2C_CR2_DMAEN       11
1273 #define STM_I2C_CR2_ITBUFEN     10
1274 #define STM_I2C_CR2_ITEVTEN     9
1275 #define STM_I2C_CR2_ITERREN     8
1276 #define STM_I2C_CR2_FREQ        0
1277 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1278 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1279 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1280 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1281 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1282 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1283
1284 #define STM_I2C_SR1_SMBALERT    15
1285 #define STM_I2C_SR1_TIMEOUT     14
1286 #define STM_I2C_SR1_PECERR      12
1287 #define STM_I2C_SR1_OVR         11
1288 #define STM_I2C_SR1_AF          10
1289 #define STM_I2C_SR1_ARLO        9
1290 #define STM_I2C_SR1_BERR        8
1291 #define STM_I2C_SR1_TXE         7
1292 #define STM_I2C_SR1_RXNE        6
1293 #define STM_I2C_SR1_STOPF       4
1294 #define STM_I2C_SR1_ADD10       3
1295 #define STM_I2C_SR1_BTF         2
1296 #define STM_I2C_SR1_ADDR        1
1297 #define STM_I2C_SR1_SB          0
1298
1299 #define STM_I2C_SR2_PEC         8
1300 #define  STM_I2C_SR2_PEC_MASK   0xff00
1301 #define STM_I2C_SR2_DUALF       7
1302 #define STM_I2C_SR2_SMBHOST     6
1303 #define STM_I2C_SR2_SMBDEFAULT  5
1304 #define STM_I2C_SR2_GENCALL     4
1305 #define STM_I2C_SR2_TRA         2
1306 #define STM_I2C_SR2_BUSY        1
1307 #define STM_I2C_SR2_MSL         0
1308
1309 #define STM_I2C_CCR_FS          15
1310 #define STM_I2C_CCR_DUTY        14
1311 #define STM_I2C_CCR_CCR         0
1312 #define  STM_I2C_CCR_MASK       0x7ff
1313
1314 struct stm_tim234 {
1315         vuint32_t       cr1;
1316         vuint32_t       cr2;
1317         vuint32_t       smcr;
1318         vuint32_t       dier;
1319
1320         vuint32_t       sr;
1321         vuint32_t       egr;
1322         vuint32_t       ccmr1;
1323         vuint32_t       ccmr2;
1324
1325         vuint32_t       ccer;
1326         vuint32_t       cnt;
1327         vuint32_t       psc;
1328         vuint32_t       arr;
1329
1330         uint32_t        reserved_30;
1331         vuint32_t       ccr1;
1332         vuint32_t       ccr2;
1333         vuint32_t       ccr3;
1334
1335         vuint32_t       ccr4;
1336         uint32_t        reserved_44;
1337         vuint32_t       dcr;
1338         vuint32_t       dmar;
1339
1340         uint32_t        reserved_50;
1341 };
1342
1343 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1344
1345 #define STM_TIM234_CR1_CKD      8
1346 #define  STM_TIM234_CR1_CKD_1           0
1347 #define  STM_TIM234_CR1_CKD_2           1
1348 #define  STM_TIM234_CR1_CKD_4           2
1349 #define  STM_TIM234_CR1_CKD_MASK        3
1350 #define STM_TIM234_CR1_ARPE     7
1351 #define STM_TIM234_CR1_CMS      5
1352 #define  STM_TIM234_CR1_CMS_EDGE        0
1353 #define  STM_TIM234_CR1_CMS_CENTER_1    1
1354 #define  STM_TIM234_CR1_CMS_CENTER_2    2
1355 #define  STM_TIM234_CR1_CMS_CENTER_3    3
1356 #define  STM_TIM234_CR1_CMS_MASK        3
1357 #define STM_TIM234_CR1_DIR      4
1358 #define  STM_TIM234_CR1_DIR_UP          0
1359 #define  STM_TIM234_CR1_DIR_DOWN        1
1360 #define STM_TIM234_CR1_OPM      3
1361 #define STM_TIM234_CR1_URS      2
1362 #define STM_TIM234_CR1_UDIS     1
1363 #define STM_TIM234_CR1_CEN      0
1364
1365 #define STM_TIM234_CR2_TI1S     7
1366 #define STM_TIM234_CR2_MMS      4
1367 #define  STM_TIM234_CR2_MMS_RESET               0
1368 #define  STM_TIM234_CR2_MMS_ENABLE              1
1369 #define  STM_TIM234_CR2_MMS_UPDATE              2
1370 #define  STM_TIM234_CR2_MMS_COMPARE_PULSE       3
1371 #define  STM_TIM234_CR2_MMS_COMPARE_OC1REF      4
1372 #define  STM_TIM234_CR2_MMS_COMPARE_OC2REF      5
1373 #define  STM_TIM234_CR2_MMS_COMPARE_OC3REF      6
1374 #define  STM_TIM234_CR2_MMS_COMPARE_OC4REF      7
1375 #define  STM_TIM234_CR2_MMS_MASK                7
1376 #define STM_TIM234_CR2_CCDS     3
1377
1378 #define STM_TIM234_SMCR_ETP     15
1379 #define STM_TIM234_SMCR_ECE     14
1380 #define STM_TIM234_SMCR_ETPS    12
1381 #define  STM_TIM234_SMCR_ETPS_OFF               0
1382 #define  STM_TIM234_SMCR_ETPS_DIV_2             1
1383 #define  STM_TIM234_SMCR_ETPS_DIV_4             2
1384 #define  STM_TIM234_SMCR_ETPS_DIV_8             3
1385 #define  STM_TIM234_SMCR_ETPS_MASK              3
1386 #define STM_TIM234_SMCR_ETF     8
1387 #define  STM_TIM234_SMCR_ETF_NONE               0
1388 #define  STM_TIM234_SMCR_ETF_INT_N_2            1
1389 #define  STM_TIM234_SMCR_ETF_INT_N_4            2
1390 #define  STM_TIM234_SMCR_ETF_INT_N_8            3
1391 #define  STM_TIM234_SMCR_ETF_DTS_2_N_6          4
1392 #define  STM_TIM234_SMCR_ETF_DTS_2_N_8          5
1393 #define  STM_TIM234_SMCR_ETF_DTS_4_N_6          6
1394 #define  STM_TIM234_SMCR_ETF_DTS_4_N_8          7
1395 #define  STM_TIM234_SMCR_ETF_DTS_8_N_6          8
1396 #define  STM_TIM234_SMCR_ETF_DTS_8_N_8          9
1397 #define  STM_TIM234_SMCR_ETF_DTS_16_N_5         10
1398 #define  STM_TIM234_SMCR_ETF_DTS_16_N_6         11
1399 #define  STM_TIM234_SMCR_ETF_DTS_16_N_8         12
1400 #define  STM_TIM234_SMCR_ETF_DTS_32_N_5         13
1401 #define  STM_TIM234_SMCR_ETF_DTS_32_N_6         14
1402 #define  STM_TIM234_SMCR_ETF_DTS_32_N_8         15
1403 #define  STM_TIM234_SMCR_ETF_MASK               15
1404 #define STM_TIM234_SMCR_MSM     7
1405 #define STM_TIM234_SMCR_TS      4
1406 #define  STM_TIM234_SMCR_TS_ITR0                0
1407 #define  STM_TIM234_SMCR_TS_ITR1                1
1408 #define  STM_TIM234_SMCR_TS_ITR2                2
1409 #define  STM_TIM234_SMCR_TS_ITR3                3
1410 #define  STM_TIM234_SMCR_TS_TI1F_ED             4
1411 #define  STM_TIM234_SMCR_TS_TI1FP1              5
1412 #define  STM_TIM234_SMCR_TS_TI2FP2              6
1413 #define  STM_TIM234_SMCR_TS_ETRF                7
1414 #define  STM_TIM234_SMCR_TS_MASK                7
1415 #define STM_TIM234_SMCR_OCCS    3
1416 #define STM_TIM234_SMCR_SMS     0
1417 #define  STM_TIM234_SMCR_SMS_DISABLE            0
1418 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_1     1
1419 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_2     2
1420 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_3     3
1421 #define  STM_TIM234_SMCR_SMS_RESET_MODE         4
1422 #define  STM_TIM234_SMCR_SMS_GATED_MODE         5
1423 #define  STM_TIM234_SMCR_SMS_TRIGGER_MODE       6
1424 #define  STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK     7
1425 #define  STM_TIM234_SMCR_SMS_MASK               7
1426
1427 #define STM_TIM234_SR_CC4OF     12
1428 #define STM_TIM234_SR_CC3OF     11
1429 #define STM_TIM234_SR_CC2OF     10
1430 #define STM_TIM234_SR_CC1OF     9
1431 #define STM_TIM234_SR_TIF       6
1432 #define STM_TIM234_SR_CC4IF     4
1433 #define STM_TIM234_SR_CC3IF     3
1434 #define STM_TIM234_SR_CC2IF     2
1435 #define STM_TIM234_SR_CC1IF     1
1436 #define STM_TIM234_SR_UIF       0
1437
1438 #define STM_TIM234_CCMR1_OC2CE  15
1439 #define STM_TIM234_CCMR1_OC2M   12
1440 #define  STM_TIM234_CCMR1_OC2M_FROZEN                   0
1441 #define  STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH        1
1442 #define  STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH         2
1443 #define  STM_TIM234_CCMR1_OC2M_TOGGLE                   3
1444 #define  STM_TIM234_CCMR1_OC2M_FORCE_LOW                4
1445 #define  STM_TIM234_CCMR1_OC2M_FORCE_HIGH               5
1446 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_1               6
1447 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_2               7
1448 #define  STM_TIM234_CCMR1_OC2M_MASK                     7
1449 #define STM_TIM234_CCMR1_OC2PE  11
1450 #define STM_TIM234_CCMR1_OC2FE  10
1451 #define STM_TIM234_CCMR1_CC2S   8
1452 #define  STM_TIM234_CCMR1_CC2S_OUTPUT                   0
1453 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI2                1
1454 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI1                2
1455 #define  STM_TIM234_CCMR1_CC2S_INPUT_TRC                3
1456 #define  STM_TIM234_CCMR1_CC2S_MASK                     3
1457
1458 #define STM_TIM234_CCMR1_OC1CE  7
1459 #define STM_TIM234_CCMR1_OC1M   4
1460 #define  STM_TIM234_CCMR1_OC1M_FROZEN                   0
1461 #define  STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH        1
1462 #define  STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH         2
1463 #define  STM_TIM234_CCMR1_OC1M_TOGGLE                   3
1464 #define  STM_TIM234_CCMR1_OC1M_FORCE_LOW                4
1465 #define  STM_TIM234_CCMR1_OC1M_FORCE_HIGH               5
1466 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_1               6
1467 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_2               7
1468 #define  STM_TIM234_CCMR1_OC1M_MASK                     7
1469 #define STM_TIM234_CCMR1_OC1PE  11
1470 #define STM_TIM234_CCMR1_OC1FE  2
1471 #define STM_TIM234_CCMR1_CC1S   0
1472 #define  STM_TIM234_CCMR1_CC1S_OUTPUT                   0
1473 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI1                1
1474 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI2                2
1475 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC                3
1476 #define  STM_TIM234_CCMR1_CC1S_MASK                     3
1477
1478 #define STM_TIM234_CCMR2_OC2CE  15
1479 #define STM_TIM234_CCMR2_OC4M   12
1480 #define  STM_TIM234_CCMR2_OC4M_FROZEN                   0
1481 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
1482 #define  STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH         2
1483 #define  STM_TIM234_CCMR2_OC4M_TOGGLE                   3
1484 #define  STM_TIM234_CCMR2_OC4M_FORCE_LOW                4
1485 #define  STM_TIM234_CCMR2_OC4M_FORCE_HIGH               5
1486 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_1               6
1487 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_2               7
1488 #define  STM_TIM234_CCMR2_OC4M_MASK                     7
1489 #define STM_TIM234_CCMR2_OC4PE  11
1490 #define STM_TIM234_CCMR2_OC4FE  10
1491 #define STM_TIM234_CCMR2_CC4S   8
1492 #define  STM_TIM234_CCMR2_CC4S_OUTPUT                   0
1493 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI4                1
1494 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI3                2
1495 #define  STM_TIM234_CCMR2_CC4S_INPUT_TRC                3
1496 #define  STM_TIM234_CCMR2_CC4S_MASK                     3
1497
1498 #define STM_TIM234_CCMR2_OC3CE  7
1499 #define STM_TIM234_CCMR2_OC3M   4
1500 #define  STM_TIM234_CCMR2_OC3M_FROZEN                   0
1501 #define  STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH        1
1502 #define  STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH         2
1503 #define  STM_TIM234_CCMR2_OC3M_TOGGLE                   3
1504 #define  STM_TIM234_CCMR2_OC3M_FORCE_LOW                4
1505 #define  STM_TIM234_CCMR2_OC3M_FORCE_HIGH               5
1506 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_1               6
1507 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_2               7
1508 #define  STM_TIM234_CCMR2_OC3M_MASK                     7
1509 #define STM_TIM234_CCMR2_OC3PE  11
1510 #define STM_TIM234_CCMR2_OC3FE  2
1511 #define STM_TIM234_CCMR2_CC3S   0
1512 #define  STM_TIM234_CCMR2_CC3S_OUTPUT                   0
1513 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI3                1
1514 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI4                2
1515 #define  STM_TIM234_CCMR2_CC3S_INPUT_TRC                3
1516 #define  STM_TIM234_CCMR2_CC3S_MASK                     3
1517
1518 #define STM_TIM234_CCER_CC4NP   15
1519 #define STM_TIM234_CCER_CC4P    13
1520 #define STM_TIM234_CCER_CC4E    12
1521 #define STM_TIM234_CCER_CC3NP   11
1522 #define STM_TIM234_CCER_CC3P    9
1523 #define STM_TIM234_CCER_CC3E    8
1524 #define STM_TIM234_CCER_CC2NP   7
1525 #define STM_TIM234_CCER_CC2P    5
1526 #define STM_TIM234_CCER_CC2E    4
1527 #define STM_TIM234_CCER_CC1NP   3
1528 #define STM_TIM234_CCER_CC1P    1
1529 #define STM_TIM234_CCER_CC1E    0
1530
1531 struct stm_usb {
1532         vuint32_t       epr[8];
1533         uint8_t         reserved_20[0x40 - 0x20];
1534         vuint32_t       cntr;
1535         vuint32_t       istr;
1536         vuint32_t       fnr;
1537         vuint32_t       daddr;
1538         vuint32_t       btable;
1539 };
1540
1541 #define STM_USB_EPR_CTR_RX      15
1542 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1543 #define STM_USB_EPR_DTOG_RX     14
1544 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1545 #define STM_USB_EPR_STAT_RX     12
1546 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1547 #define  STM_USB_EPR_STAT_RX_STALL                      1
1548 #define  STM_USB_EPR_STAT_RX_NAK                        2
1549 #define  STM_USB_EPR_STAT_RX_VALID                      3
1550 #define  STM_USB_EPR_STAT_RX_MASK                       3
1551 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1552 #define STM_USB_EPR_SETUP       11
1553 #define STM_USB_EPR_EP_TYPE     9
1554 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1555 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1556 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1557 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1558 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1559 #define STM_USB_EPR_EP_KIND     8
1560 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1561 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1562 #define STM_USB_EPR_CTR_TX      7
1563 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1564 #define STM_USB_EPR_DTOG_TX     6
1565 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1566 #define STM_USB_EPR_STAT_TX     4
1567 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1568 #define  STM_USB_EPR_STAT_TX_STALL                      1
1569 #define  STM_USB_EPR_STAT_TX_NAK                        2
1570 #define  STM_USB_EPR_STAT_TX_VALID                      3
1571 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1572 #define  STM_USB_EPR_STAT_TX_MASK                       3
1573 #define STM_USB_EPR_EA          0
1574 #define  STM_USB_EPR_EA_MASK                            0xf
1575
1576 #define STM_USB_CNTR_CTRM       15
1577 #define STM_USB_CNTR_PMAOVRM    14
1578 #define STM_USB_CNTR_ERRM       13
1579 #define STM_USB_CNTR_WKUPM      12
1580 #define STM_USB_CNTR_SUSPM      11
1581 #define STM_USB_CNTR_RESETM     10
1582 #define STM_USB_CNTR_SOFM       9
1583 #define STM_USB_CNTR_ESOFM      8
1584 #define STM_USB_CNTR_RESUME     4
1585 #define STM_USB_CNTR_FSUSP      3
1586 #define STM_USB_CNTR_LP_MODE    2
1587 #define STM_USB_CNTR_PDWN       1
1588 #define STM_USB_CNTR_FRES       0
1589
1590 #define STM_USB_ISTR_CTR        15
1591 #define STM_USB_ISTR_PMAOVR     14
1592 #define STM_USB_ISTR_ERR        13
1593 #define STM_USB_ISTR_WKUP       12
1594 #define STM_USB_ISTR_SUSP       11
1595 #define STM_USB_ISTR_RESET      10
1596 #define STM_USB_ISTR_SOF        9
1597 #define STM_USB_ISTR_ESOF       8
1598 #define STM_USB_ISTR_DIR        4
1599 #define STM_USB_ISTR_EP_ID      0
1600 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1601
1602 #define STM_USB_FNR_RXDP        15
1603 #define STM_USB_FNR_RXDM        14
1604 #define STM_USB_FNR_LCK         13
1605 #define STM_USB_FNR_LSOF        11
1606 #define  STM_USB_FNR_LSOF_MASK                  0x3
1607 #define STM_USB_FNR_FN          0
1608 #define  STM_USB_FNR_FN_MASK                    0x7ff
1609
1610 #define STM_USB_DADDR_EF        7
1611 #define STM_USB_DADDR_ADD       0
1612 #define  STM_USB_DADDR_ADD_MASK                 0x7f
1613
1614 extern struct stm_usb stm_usb;
1615
1616 union stm_usb_bdt {
1617         struct {
1618                 vuint32_t       addr_tx;
1619                 vuint32_t       count_tx;
1620                 vuint32_t       addr_rx;
1621                 vuint32_t       count_rx;
1622         } single;
1623         struct {
1624                 vuint32_t       addr;
1625                 vuint32_t       count;
1626         } double_tx[2];
1627         struct {
1628                 vuint32_t       addr;
1629                 vuint32_t       count;
1630         } double_rx[2];
1631 };
1632
1633 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
1634 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
1635 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
1636 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
1637 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
1638
1639 #define STM_USB_BDT_SIZE        8
1640
1641 extern uint8_t stm_usb_sram[];
1642
1643 struct stm_exti {
1644         vuint32_t       imr;
1645         vuint32_t       emr;
1646         vuint32_t       rtsr;
1647         vuint32_t       ftsr;
1648
1649         vuint32_t       swier;
1650         vuint32_t       pr;
1651 };
1652
1653 extern struct stm_exti stm_exti;
1654
1655 #endif /* _STM32L_H_ */