git.gag.com Git - fw/altos/blob - src/stm/stm32l.h

   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #ifndef _STM32L_H_
  19 #define _STM32L_H_
  20
  21 #include <stdint.h>
  22
  23 typedef volatile uint32_t       vuint32_t;
  24 typedef volatile void *         vvoid_t;
  25
  26 struct stm_gpio {
  27         vuint32_t       moder;
  28         vuint32_t       otyper;
  29         vuint32_t       ospeedr;
  30         vuint32_t       pupdr;
  31
  32         vuint32_t       idr;
  33         vuint32_t       odr;
  34         vuint32_t       bsrr;
  35         vuint32_t       lckr;
  36
  37         vuint32_t       afrl;
  38         vuint32_t       afrh;
  39 };
  40
  41 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  42 #define STM_MODER_MASK                  3
  43 #define STM_MODER_INPUT                 0
  44 #define STM_MODER_OUTPUT                1
  45 #define STM_MODER_ALTERNATE             2
  46 #define STM_MODER_ANALOG                3
  47
  48 static inline void
  49 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  50         gpio->moder = ((gpio->moder &
  51                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  52                        value << STM_MODER_SHIFT(pin));
  53 }
  54
  55 static inline uint32_t
  56 stm_moder_get(struct stm_gpio *gpio, int pin) {
  57         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  58 }
  59
  60 #define STM_OTYPER_SHIFT(pin)           (pin)
  61 #define STM_OTYPER_MASK                 1
  62 #define STM_OTYPER_PUSH_PULL            0
  63 #define STM_OTYPER_OPEN_DRAIN           1
  64
  65 static inline void
  66 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  67         gpio->otyper = ((gpio->otyper &
  68                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  69                         value << STM_OTYPER_SHIFT(pin));
  70 }
  71
  72 static inline uint32_t
  73 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  74         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  75 }
  76
  77 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  78 #define STM_OSPEEDR_MASK                3
  79 #define STM_OSPEEDR_400kHz              0
  80 #define STM_OSPEEDR_2MHz                1
  81 #define STM_OSPEEDR_10MHz               2
  82 #define STM_OSPEEDR_40MHz               3
  83
  84 static inline void
  85 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  86         gpio->ospeedr = ((gpio->ospeedr &
  87                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  88                        value << STM_OSPEEDR_SHIFT(pin));
  89 }
  90
  91 static inline uint32_t
  92 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  93         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  94 }
  95
  96 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
  97 #define STM_PUPDR_MASK                  3
  98 #define STM_PUPDR_NONE                  0
  99 #define STM_PUPDR_PULL_UP               1
 100 #define STM_PUPDR_PULL_DOWN             2
 101 #define STM_PUPDR_RESERVED              3
 102
 103 static inline void
 104 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 105         gpio->pupdr = ((gpio->pupdr &
 106                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 107                        value << STM_PUPDR_SHIFT(pin));
 108 }
 109
 110 static inline uint32_t
 111 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 112         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 113 }
 114
 115 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 116 #define STM_AFR_MASK                    0xf
 117 #define STM_AFR_NONE                    0
 118 #define STM_AFR_AF0                     0x0
 119 #define STM_AFR_AF1                     0x1
 120 #define STM_AFR_AF2                     0x2
 121 #define STM_AFR_AF3                     0x3
 122 #define STM_AFR_AF4                     0x4
 123 #define STM_AFR_AF5                     0x5
 124 #define STM_AFR_AF6                     0x6
 125 #define STM_AFR_AF7                     0x7
 126 #define STM_AFR_AF8                     0x8
 127 #define STM_AFR_AF9                     0x9
 128 #define STM_AFR_AF10                    0xa
 129 #define STM_AFR_AF11                    0xb
 130 #define STM_AFR_AF12                    0xc
 131 #define STM_AFR_AF13                    0xd
 132 #define STM_AFR_AF14                    0xe
 133 #define STM_AFR_AF15                    0xf
 134
 135 static inline void
 136 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 137         /*
 138          * Set alternate pin mode too
 139          */
 140         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 141         if (pin < 8)
 142                 gpio->afrl = ((gpio->afrl &
 143                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 144                               value << STM_AFR_SHIFT(pin));
 145         else {
 146                 pin -= 8;
 147                 gpio->afrh = ((gpio->afrh &
 148                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 149                               value << STM_AFR_SHIFT(pin));
 150         }
 151 }
 152
 153 static inline uint32_t
 154 stm_afr_get(struct stm_gpio *gpio, int pin) {
 155         if (pin < 8)
 156                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 157         else {
 158                 pin -= 8;
 159                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 160         }
 161 }
 162
 163 static inline void
 164 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 165         /* Use the bit set/reset register to do this atomically */
 166         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 167 }
 168
 169 static inline uint8_t
 170 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 171         return (gpio->idr >> pin) & 1;
 172 }
 173
 174 static inline uint16_t
 175 stm_gpio_get_all(struct stm_gpio *gpio) {
 176         return gpio->idr;
 177 }
 178
 179 extern struct stm_gpio stm_gpioa;
 180 extern struct stm_gpio stm_gpiob;
 181 extern struct stm_gpio stm_gpioc;
 182 extern struct stm_gpio stm_gpiod;
 183 extern struct stm_gpio stm_gpioe;
 184 extern struct stm_gpio stm_gpioh;
 185
 186 struct stm_usart {
 187         vuint32_t       sr;     /* status register */
 188         vuint32_t       dr;     /* data register */
 189         vuint32_t       brr;    /* baud rate register */
 190         vuint32_t       cr1;    /* control register 1 */
 191
 192         vuint32_t       cr2;    /* control register 2 */
 193         vuint32_t       cr3;    /* control register 3 */
 194         vuint32_t       gtpr;   /* guard time and prescaler */
 195 };
 196
 197 extern struct stm_usart stm_usart1;
 198 extern struct stm_usart stm_usart2;
 199 extern struct stm_usart stm_usart3;
 200
 201 #define STM_USART_SR_CTS        (9)     /* CTS flag */
 202 #define STM_USART_SR_LBD        (8)     /* LIN break detection flag */
 203 #define STM_USART_SR_TXE        (7)     /* Transmit data register empty */
 204 #define STM_USART_SR_TC         (6)     /* Transmission complete */
 205 #define STM_USART_SR_RXNE       (5)     /* Read data register not empty */
 206 #define STM_USART_SR_IDLE       (4)     /* IDLE line detected */
 207 #define STM_USART_SR_ORE        (3)     /* Overrun error */
 208 #define STM_USART_SR_NF         (2)     /* Noise detected flag */
 209 #define STM_USART_SR_FE         (1)     /* Framing error */
 210 #define STM_USART_SR_PE         (0)     /* Parity error */
 211
 212 #define STM_USART_CR1_OVER8     (15)    /* Oversampling mode */
 213 #define STM_USART_CR1_UE        (13)    /* USART enable */
 214 #define STM_USART_CR1_M         (12)    /* Word length */
 215 #define STM_USART_CR1_WAKE      (11)    /* Wakeup method */
 216 #define STM_USART_CR1_PCE       (10)    /* Parity control enable */
 217 #define STM_USART_CR1_PS        (9)     /* Parity selection */
 218 #define STM_USART_CR1_PEIE      (8)     /* PE interrupt enable */
 219 #define STM_USART_CR1_TXEIE     (7)     /* TXE interrupt enable */
 220 #define STM_USART_CR1_TCIE      (6)     /* Transmission complete interrupt enable */
 221 #define STM_USART_CR1_RXNEIE    (5)     /* RXNE interrupt enable */
 222 #define STM_USART_CR1_IDLEIE    (4)     /* IDLE interrupt enable */
 223 #define STM_USART_CR1_TE        (3)     /* Transmitter enable */
 224 #define STM_USART_CR1_RE        (2)     /* Receiver enable */
 225 #define STM_USART_CR1_RWU       (1)     /* Receiver wakeup */
 226 #define STM_USART_CR1_SBK       (0)     /* Send break */
 227
 228 #define STM_USART_CR2_LINEN     (14)    /* LIN mode enable */
 229 #define STM_USART_CR2_STOP      (12)    /* STOP bits */
 230 #define STM_USART_CR2_STOP_MASK 3
 231 #define STM_USART_CR2_STOP_1    0
 232 #define STM_USART_CR2_STOP_0_5  1
 233 #define STM_USART_CR2_STOP_2    2
 234 #define STM_USART_CR2_STOP_1_5  3
 235
 236 #define STM_USART_CR2_CLKEN     (11)    /* Clock enable */
 237 #define STM_USART_CR2_CPOL      (10)    /* Clock polarity */
 238 #define STM_USART_CR2_CPHA      (9)     /* Clock phase */
 239 #define STM_USART_CR2_LBCL      (8)     /* Last bit clock pulse */
 240 #define STM_USART_CR2_LBDIE     (6)     /* LIN break detection interrupt enable */
 241 #define STM_USART_CR2_LBDL      (5)     /* lin break detection length */
 242 #define STM_USART_CR2_ADD       (0)
 243 #define STM_USART_CR2_ADD_MASK  0xf
 244
 245 #define STM_USART_CR3_ONEBITE   (11)    /* One sample bit method enable */
 246 #define STM_USART_CR3_CTSIE     (10)    /* CTS interrupt enable */
 247 #define STM_USART_CR3_CTSE      (9)     /* CTS enable */
 248 #define STM_USART_CR3_RTSE      (8)     /* RTS enable */
 249 #define STM_USART_CR3_DMAT      (7)     /* DMA enable transmitter */
 250 #define STM_USART_CR3_DMAR      (6)     /* DMA enable receiver */
 251 #define STM_USART_CR3_SCEN      (5)     /* Smartcard mode enable */
 252 #define STM_USART_CR3_NACK      (4)     /* Smartcard NACK enable */
 253 #define STM_USART_CR3_HDSEL     (3)     /* Half-duplex selection */
 254 #define STM_USART_CR3_IRLP      (2)     /* IrDA low-power */
 255 #define STM_USART_CR3_IREN      (1)     /* IrDA mode enable */
 256 #define STM_USART_CR3_EIE       (0)     /* Error interrupt enable */
 257
 258 struct stm_tim {
 259 };
 260
 261 extern struct stm_tim stm_tim9;
 262
 263 struct stm_tim1011 {
 264         vuint32_t       cr1;
 265         uint32_t        unused_4;
 266         vuint32_t       smcr;
 267         vuint32_t       dier;
 268         vuint32_t       sr;
 269         vuint32_t       egr;
 270         vuint32_t       ccmr1;
 271         uint32_t        unused_1c;
 272         vuint32_t       ccer;
 273         vuint32_t       cnt;
 274         vuint32_t       psc;
 275         vuint32_t       arr;
 276         uint32_t        unused_30;
 277         vuint32_t       ccr1;
 278         uint32_t        unused_38;
 279         uint32_t        unused_3c;
 280         uint32_t        unused_40;
 281         uint32_t        unused_44;
 282         uint32_t        unused_48;
 283         uint32_t        unused_4c;
 284         vuint32_t       or;
 285 };
 286
 287 extern struct stm_tim1011 stm_tim10;
 288 extern struct stm_tim1011 stm_tim11;
 289
 290 #define STM_TIM1011_CR1_CKD     8
 291 #define  STM_TIM1011_CR1_CKD_1          0
 292 #define  STM_TIM1011_CR1_CKD_2          1
 293 #define  STM_TIM1011_CR1_CKD_4          2
 294 #define  STM_TIM1011_CR1_CKD_MASK       3
 295 #define STM_TIM1011_CR1_ARPE    7
 296 #define STM_TIM1011_CR1_URS     2
 297 #define STM_TIM1011_CR1_UDIS    1
 298 #define STM_TIM1011_CR1_CEN     0
 299
 300 #define STM_TIM1011_SMCR_ETP    15
 301 #define STM_TIM1011_SMCR_ECE    14
 302 #define STM_TIM1011_SMCR_ETPS   12
 303 #define  STM_TIM1011_SMCR_ETPS_OFF      0
 304 #define  STM_TIM1011_SMCR_ETPS_2        1
 305 #define  STM_TIM1011_SMCR_ETPS_4        2
 306 #define  STM_TIM1011_SMCR_ETPS_8        3
 307 #define  STM_TIM1011_SMCR_ETPS_MASK     3
 308 #define STM_TIM1011_SMCR_ETF    8
 309 #define  STM_TIM1011_SMCR_ETF_NONE              0
 310 #define  STM_TIM1011_SMCR_ETF_CK_INT_2          1
 311 #define  STM_TIM1011_SMCR_ETF_CK_INT_4          2
 312 #define  STM_TIM1011_SMCR_ETF_CK_INT_8          3
 313 #define  STM_TIM1011_SMCR_ETF_DTS_2_6           4
 314 #define  STM_TIM1011_SMCR_ETF_DTS_2_8           5
 315 #define  STM_TIM1011_SMCR_ETF_DTS_4_6           6
 316 #define  STM_TIM1011_SMCR_ETF_DTS_4_8           7
 317 #define  STM_TIM1011_SMCR_ETF_DTS_8_6           8
 318 #define  STM_TIM1011_SMCR_ETF_DTS_8_8           9
 319 #define  STM_TIM1011_SMCR_ETF_DTS_16_5          10
 320 #define  STM_TIM1011_SMCR_ETF_DTS_16_6          11
 321 #define  STM_TIM1011_SMCR_ETF_DTS_16_8          12
 322 #define  STM_TIM1011_SMCR_ETF_DTS_32_5          13
 323 #define  STM_TIM1011_SMCR_ETF_DTS_32_6          14
 324 #define  STM_TIM1011_SMCR_ETF_DTS_32_8          15
 325 #define  STM_TIM1011_SMCR_ETF_MASK              15
 326
 327 #define STM_TIM1011_DIER_CC1E   1
 328 #define STM_TIM1011_DIER_UIE    0
 329
 330 #define STM_TIM1011_SR_CC1OF    9
 331 #define STM_TIM1011_SR_CC1IF    1
 332 #define STM_TIM1011_SR_UIF      0
 333
 334 #define STM_TIM1011_EGR_CC1G    1
 335 #define STM_TIM1011_EGR_UG      0
 336
 337 #define STM_TIM1011_CCMR1_OC1CE 7
 338 #define STM_TIM1011_CCMR1_OC1M  4
 339 #define  STM_TIM1011_CCMR1_OC1M_FROZEN                  0
 340 #define  STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH   1
 341 #define  STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
 342 #define  STM_TIM1011_CCMR1_OC1M_TOGGLE                  3
 343 #define  STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE          4
 344 #define  STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE            5
 345 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_1              6
 346 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_2              7
 347 #define  STM_TIM1011_CCMR1_OC1M_MASK                    7
 348 #define STM_TIM1011_CCMR1_OC1PE 3
 349 #define STM_TIM1011_CCMR1_OC1FE 2
 350 #define STM_TIM1011_CCMR1_CC1S  0
 351 #define  STM_TIM1011_CCMR1_CC1S_OUTPUT                  0
 352 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI1               1
 353 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI2               2
 354 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TRC               3
 355 #define  STM_TIM1011_CCMR1_CC1S_MASK                    3
 356
 357 #define  STM_TIM1011_CCMR1_IC1F_NONE            0
 358 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_2        1
 359 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_4        2
 360 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_8        3
 361 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_6         4
 362 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_8         5
 363 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_6         6
 364 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_8         7
 365 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_6         8
 366 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_8         9
 367 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_5        10
 368 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_6        11
 369 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_8        12
 370 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_5        13
 371 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_6        14
 372 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_8        15
 373 #define  STM_TIM1011_CCMR1_IC1F_MASK            15
 374 #define STM_TIM1011_CCMR1_IC1PSC        2
 375 #define  STM_TIM1011_CCMR1_IC1PSC_1             0
 376 #define  STM_TIM1011_CCMR1_IC1PSC_2             1
 377 #define  STM_TIM1011_CCMR1_IC1PSC_4             2
 378 #define  STM_TIM1011_CCMR1_IC1PSC_8             3
 379 #define  STM_TIM1011_CCMR1_IC1PSC_MASK          3
 380 #define STM_TIM1011_CCMR1_CC1S          0
 381
 382 #define STM_TIM1011_CCER_CC1NP          3
 383 #define STM_TIM1011_CCER_CC1P           1
 384 #define STM_TIM1011_CCER_CC1E           0
 385
 386 #define STM_TIM1011_OR_TI1_RMP_RI       3
 387 #define STM_TIM1011_ETR_RMP             2
 388 #define STM_TIM1011_TI1_RMP             0
 389 #define  STM_TIM1011_TI1_RMP_GPIO               0
 390 #define  STM_TIM1011_TI1_RMP_LSI                1
 391 #define  STM_TIM1011_TI1_RMP_LSE                2
 392 #define  STM_TIM1011_TI1_RMP_RTC                3
 393 #define  STM_TIM1011_TI1_RMP_MASK               3
 394
 395 /* Flash interface */
 396
 397 struct stm_flash {
 398         vuint32_t       acr;
 399         vuint32_t       pecr;
 400         vuint32_t       pdkeyr;
 401         vuint32_t       pekeyr;
 402
 403         vuint32_t       prgkeyr;
 404         vuint32_t       optkeyr;
 405         vuint32_t       sr;
 406         vuint32_t       obr;
 407
 408         vuint32_t       wrpr;
 409 };
 410
 411 extern struct stm_flash stm_flash;
 412
 413 #define STM_FLASH_ACR_RUN_PD    (4)
 414 #define STM_FLASH_ACR_SLEEP_PD  (3)
 415 #define STM_FLASH_ACR_ACC64     (2)
 416 #define STM_FLASH_ACR_PRFEN     (1)
 417 #define STM_FLASH_ACR_LATENCY   (0)
 418
 419 #define STM_FLASH_PECR_OBL_LAUNCH       18
 420 #define STM_FLASH_PECR_ERRIE            17
 421 #define STM_FLASH_PECR_EOPIE            16
 422 #define STM_FLASH_PECR_FPRG             10
 423 #define STM_FLASH_PECR_ERASE            9
 424 #define STM_FLASH_PECR_FTDW             8
 425 #define STM_FLASH_PECR_DATA             4
 426 #define STM_FLASH_PECR_PROG             3
 427 #define STM_FLASH_PECR_OPTLOCK          2
 428 #define STM_FLASH_PECR_PRGLOCK          1
 429 #define STM_FLASH_PECR_PELOCK           0
 430
 431 #define STM_FLASH_SR_OPTVERR            11
 432 #define STM_FLASH_SR_SIZERR             10
 433 #define STM_FLASH_SR_PGAERR             9
 434 #define STM_FLASH_SR_WRPERR             8
 435 #define STM_FLASH_SR_READY              3
 436 #define STM_FLASH_SR_ENDHV              2
 437 #define STM_FLASH_SR_EOP                1
 438 #define STM_FLASH_SR_BSY                0
 439
 440 #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
 441 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
 442
 443 #define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
 444 #define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
 445
 446 struct stm_rcc {
 447         vuint32_t       cr;
 448         vuint32_t       icscr;
 449         vuint32_t       cfgr;
 450         vuint32_t       cir;
 451
 452         vuint32_t       ahbrstr;
 453         vuint32_t       apb2rstr;
 454         vuint32_t       apb1rstr;
 455         vuint32_t       ahbenr;
 456
 457         vuint32_t       apb2enr;
 458         vuint32_t       apb1enr;
 459         vuint32_t       ahblenr;
 460         vuint32_t       apb2lpenr;
 461
 462         vuint32_t       apb1lpenr;
 463         vuint32_t       csr;
 464 };
 465
 466 extern struct stm_rcc stm_rcc;
 467
 468 /* Nominal high speed internal oscillator frequency is 16MHz */
 469 #define STM_HSI_FREQ            16000000
 470
 471 #define STM_RCC_CR_RTCPRE       (29)
 472 #define  STM_RCC_CR_RTCPRE_HSE_DIV_2    0
 473 #define  STM_RCC_CR_RTCPRE_HSE_DIV_4    1
 474 #define  STM_RCC_CR_RTCPRE_HSE_DIV_8    2
 475 #define  STM_RCC_CR_RTCPRE_HSE_DIV_16   3
 476 #define  STM_RCC_CR_RTCPRE_HSE_MASK     3
 477
 478 #define STM_RCC_CR_CSSON        (28)
 479 #define STM_RCC_CR_PLLRDY       (25)
 480 #define STM_RCC_CR_PLLON        (24)
 481 #define STM_RCC_CR_HSEBYP       (18)
 482 #define STM_RCC_CR_HSERDY       (17)
 483 #define STM_RCC_CR_HSEON        (16)
 484 #define STM_RCC_CR_MSIRDY       (9)
 485 #define STM_RCC_CR_MSION        (8)
 486 #define STM_RCC_CR_HSIRDY       (1)
 487 #define STM_RCC_CR_HSION        (0)
 488
 489 #define STM_RCC_CFGR_MCOPRE     (28)
 490 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 491 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 492 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 493 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 494 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 495 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7
 496
 497 #define STM_RCC_CFGR_MCOSEL     (24)
 498 #define  STM_RCC_CFGR_MCOSEL_DISABLE    0
 499 #define  STM_RCC_CFGR_MCOSEL_SYSCLK     1
 500 #define  STM_RCC_CFGR_MCOSEL_HSI        2
 501 #define  STM_RCC_CFGR_MCOSEL_MSI        3
 502 #define  STM_RCC_CFGR_MCOSEL_HSE        4
 503 #define  STM_RCC_CFGR_MCOSEL_PLL        5
 504 #define  STM_RCC_CFGR_MCOSEL_LSI        6
 505 #define  STM_RCC_CFGR_MCOSEL_LSE        7
 506 #define  STM_RCC_CFGR_MCOSEL_MASK       7
 507
 508 #define STM_RCC_CFGR_PLLDIV     (22)
 509 #define  STM_RCC_CFGR_PLLDIV_2          1
 510 #define  STM_RCC_CFGR_PLLDIV_3          2
 511 #define  STM_RCC_CFGR_PLLDIV_4          3
 512 #define  STM_RCC_CFGR_PLLDIV_MASK       3
 513
 514 #define STM_RCC_CFGR_PLLMUL     (18)
 515 #define  STM_RCC_CFGR_PLLMUL_3          0
 516 #define  STM_RCC_CFGR_PLLMUL_4          1
 517 #define  STM_RCC_CFGR_PLLMUL_6          2
 518 #define  STM_RCC_CFGR_PLLMUL_8          3
 519 #define  STM_RCC_CFGR_PLLMUL_12         4
 520 #define  STM_RCC_CFGR_PLLMUL_16         5
 521 #define  STM_RCC_CFGR_PLLMUL_24         6
 522 #define  STM_RCC_CFGR_PLLMUL_32         7
 523 #define  STM_RCC_CFGR_PLLMUL_48         8
 524 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 525
 526 #define STM_RCC_CFGR_PLLSRC     (16)
 527
 528 #define STM_RCC_CFGR_PPRE2      (11)
 529 #define  STM_RCC_CFGR_PPRE2_DIV_1       0
 530 #define  STM_RCC_CFGR_PPRE2_DIV_2       4
 531 #define  STM_RCC_CFGR_PPRE2_DIV_4       5
 532 #define  STM_RCC_CFGR_PPRE2_DIV_8       6
 533 #define  STM_RCC_CFGR_PPRE2_DIV_16      7
 534 #define  STM_RCC_CFGR_PPRE2_MASK        7
 535
 536 #define STM_RCC_CFGR_PPRE1      (8)
 537 #define  STM_RCC_CFGR_PPRE1_DIV_1       0
 538 #define  STM_RCC_CFGR_PPRE1_DIV_2       4
 539 #define  STM_RCC_CFGR_PPRE1_DIV_4       5
 540 #define  STM_RCC_CFGR_PPRE1_DIV_8       6
 541 #define  STM_RCC_CFGR_PPRE1_DIV_16      7
 542 #define  STM_RCC_CFGR_PPRE1_MASK        7
 543
 544 #define STM_RCC_CFGR_HPRE       (4)
 545 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 546 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 547 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 548 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 549 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 550 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 551 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 552 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 553 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 554 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 555
 556 #define STM_RCC_CFGR_SWS        (2)
 557 #define  STM_RCC_CFGR_SWS_MSI           0
 558 #define  STM_RCC_CFGR_SWS_HSI           1
 559 #define  STM_RCC_CFGR_SWS_HSE           2
 560 #define  STM_RCC_CFGR_SWS_PLL           3
 561 #define  STM_RCC_CFGR_SWS_MASK          3
 562
 563 #define STM_RCC_CFGR_SW         (0)
 564 #define  STM_RCC_CFGR_SW_MSI            0
 565 #define  STM_RCC_CFGR_SW_HSI            1
 566 #define  STM_RCC_CFGR_SW_HSE            2
 567 #define  STM_RCC_CFGR_SW_PLL            3
 568 #define  STM_RCC_CFGR_SW_MASK           3
 569
 570 #define STM_RCC_AHBENR_DMA1EN           (24)
 571 #define STM_RCC_AHBENR_FLITFEN          (15)
 572 #define STM_RCC_AHBENR_CRCEN            (12)
 573 #define STM_RCC_AHBENR_GPIOHEN          (5)
 574 #define STM_RCC_AHBENR_GPIOEEN          (4)
 575 #define STM_RCC_AHBENR_GPIODEN          (3)
 576 #define STM_RCC_AHBENR_GPIOCEN          (2)
 577 #define STM_RCC_AHBENR_GPIOBEN          (1)
 578 #define STM_RCC_AHBENR_GPIOAEN          (0)
 579
 580 #define STM_RCC_APB2ENR_USART1EN        (14)
 581 #define STM_RCC_APB2ENR_SPI1EN          (12)
 582 #define STM_RCC_APB2ENR_ADC1EN          (9)
 583 #define STM_RCC_APB2ENR_TIM11EN         (4)
 584 #define STM_RCC_APB2ENR_TIM10EN         (3)
 585 #define STM_RCC_APB2ENR_TIM9EN          (2)
 586 #define STM_RCC_APB2ENR_SYSCFGEN        (0)
 587
 588 #define STM_RCC_APB1ENR_COMPEN          (31)
 589 #define STM_RCC_APB1ENR_DACEN           (29)
 590 #define STM_RCC_APB1ENR_PWREN           (28)
 591 #define STM_RCC_APB1ENR_USBEN           (23)
 592 #define STM_RCC_APB1ENR_I2C2EN          (22)
 593 #define STM_RCC_APB1ENR_I2C1EN          (21)
 594 #define STM_RCC_APB1ENR_USART3EN        (18)
 595 #define STM_RCC_APB1ENR_USART2EN        (17)
 596 #define STM_RCC_APB1ENR_SPI2EN          (14)
 597 #define STM_RCC_APB1ENR_WWDGEN          (11)
 598 #define STM_RCC_APB1ENR_LCDEN           (9)
 599 #define STM_RCC_APB1ENR_TIM7EN          (5)
 600 #define STM_RCC_APB1ENR_TIM6EN          (4)
 601 #define STM_RCC_APB1ENR_TIM4EN          (2)
 602 #define STM_RCC_APB1ENR_TIM3EN          (1)
 603 #define STM_RCC_APB1ENR_TIM2EN          (0)
 604
 605 #define STM_RCC_CSR_LPWRRSTF            (31)
 606 #define STM_RCC_CSR_WWDGRSTF            (30)
 607 #define STM_RCC_CSR_IWDGRSTF            (29)
 608 #define STM_RCC_CSR_SFTRSTF             (28)
 609 #define STM_RCC_CSR_PORRSTF             (27)
 610 #define STM_RCC_CSR_PINRSTF             (26)
 611 #define STM_RCC_CSR_OBLRSTF             (25)
 612 #define STM_RCC_CSR_RMVF                (24)
 613 #define STM_RCC_CSR_RTFRST              (23)
 614 #define STM_RCC_CSR_RTCEN               (22)
 615 #define STM_RCC_CSR_RTCSEL              (16)
 616
 617 #define  STM_RCC_CSR_RTCSEL_NONE                0
 618 #define  STM_RCC_CSR_RTCSEL_LSE                 1
 619 #define  STM_RCC_CSR_RTCSEL_LSI                 2
 620 #define  STM_RCC_CSR_RTCSEL_HSE                 3
 621 #define  STM_RCC_CSR_RTCSEL_MASK                3
 622
 623 #define STM_RCC_CSR_LSEBYP              (10)
 624 #define STM_RCC_CSR_LSERDY              (9)
 625 #define STM_RCC_CSR_LSEON               (8)
 626 #define STM_RCC_CSR_LSIRDY              (1)
 627 #define STM_RCC_CSR_LSION               (0)
 628
 629 struct stm_pwr {
 630         vuint32_t       cr;
 631         vuint32_t       csr;
 632 };
 633
 634 extern struct stm_pwr stm_pwr;
 635
 636 #define STM_PWR_CR_LPRUN        (14)
 637
 638 #define STM_PWR_CR_VOS          (11)
 639 #define  STM_PWR_CR_VOS_1_8             1
 640 #define  STM_PWR_CR_VOS_1_5             2
 641 #define  STM_PWR_CR_VOS_1_2             3
 642 #define  STM_PWR_CR_VOS_MASK            3
 643
 644 #define STM_PWR_CR_FWU          (10)
 645 #define STM_PWR_CR_ULP          (9)
 646 #define STM_PWR_CR_DBP          (8)
 647
 648 #define STM_PWR_CR_PLS          (5)
 649 #define  STM_PWR_CR_PLS_1_9     0
 650 #define  STM_PWR_CR_PLS_2_1     1
 651 #define  STM_PWR_CR_PLS_2_3     2
 652 #define  STM_PWR_CR_PLS_2_5     3
 653 #define  STM_PWR_CR_PLS_2_7     4
 654 #define  STM_PWR_CR_PLS_2_9     5
 655 #define  STM_PWR_CR_PLS_3_1     6
 656 #define  STM_PWR_CR_PLS_EXT     7
 657 #define  STM_PWR_CR_PLS_MASK    7
 658
 659 #define STM_PWR_CR_PVDE         (4)
 660 #define STM_PWR_CR_CSBF         (3)
 661 #define STM_PWR_CR_CWUF         (2)
 662 #define STM_PWR_CR_PDDS         (1)
 663 #define STM_PWR_CR_LPSDSR       (0)
 664
 665 #define STM_PWR_CSR_EWUP3       (10)
 666 #define STM_PWR_CSR_EWUP2       (9)
 667 #define STM_PWR_CSR_EWUP1       (8)
 668 #define STM_PWR_CSR_REGLPF      (5)
 669 #define STM_PWR_CSR_VOSF        (4)
 670 #define STM_PWR_CSR_VREFINTRDYF (3)
 671 #define STM_PWR_CSR_PVDO        (2)
 672 #define STM_PWR_CSR_SBF         (1)
 673 #define STM_PWR_CSR_WUF         (0)
 674
 675 struct stm_tim67 {
 676         vuint32_t       cr1;
 677         vuint32_t       cr2;
 678         uint32_t        _unused_08;
 679         vuint32_t       dier;
 680
 681         vuint32_t       sr;
 682         vuint32_t       egr;
 683         uint32_t        _unused_18;
 684         uint32_t        _unused_1c;
 685
 686         uint32_t        _unused_20;
 687         vuint32_t       cnt;
 688         vuint32_t       psc;
 689         vuint32_t       arr;
 690 };
 691
 692 extern struct stm_tim67 stm_tim6;
 693
 694 #define STM_TIM67_CR1_ARPE      (7)
 695 #define STM_TIM67_CR1_OPM       (3)
 696 #define STM_TIM67_CR1_URS       (2)
 697 #define STM_TIM67_CR1_UDIS      (1)
 698 #define STM_TIM67_CR1_CEN       (0)
 699
 700 #define STM_TIM67_CR2_MMS       (4)
 701 #define  STM_TIM67_CR2_MMS_RESET        0
 702 #define  STM_TIM67_CR2_MMS_ENABLE       1
 703 #define  STM_TIM67_CR2_MMS_UPDATE       2
 704 #define  STM_TIM67_CR2_MMS_MASK         7
 705
 706 #define STM_TIM67_DIER_UDE      (8)
 707 #define STM_TIM67_DIER_UIE      (0)
 708
 709 #define STM_TIM67_SR_UIF        (0)
 710
 711 #define STM_TIM67_EGR_UG        (0)
 712
 713 struct stm_lcd {
 714         vuint32_t       cr;
 715         vuint32_t       fcr;
 716         vuint32_t       sr;
 717         vuint32_t       clr;
 718         uint32_t        unused_0x10;
 719         vuint32_t       ram[8*2];
 720 };
 721
 722 extern struct stm_lcd stm_lcd;
 723
 724 #define STM_LCD_CR_MUX_SEG              (7)
 725
 726 #define STM_LCD_CR_BIAS                 (5)
 727 #define  STM_LCD_CR_BIAS_1_4            0
 728 #define  STM_LCD_CR_BIAS_1_2            1
 729 #define  STM_LCD_CR_BIAS_1_3            2
 730 #define  STM_LCD_CR_BIAS_MASK           3
 731
 732 #define STM_LCD_CR_DUTY                 (2)
 733 #define  STM_LCD_CR_DUTY_STATIC         0
 734 #define  STM_LCD_CR_DUTY_1_2            1
 735 #define  STM_LCD_CR_DUTY_1_3            2
 736 #define  STM_LCD_CR_DUTY_1_4            3
 737 #define  STM_LCD_CR_DUTY_1_8            4
 738 #define  STM_LCD_CR_DUTY_MASK           7
 739
 740 #define STM_LCD_CR_VSEL                 (1)
 741 #define STM_LCD_CR_LCDEN                (0)
 742
 743 #define STM_LCD_FCR_PS                  (22)
 744 #define  STM_LCD_FCR_PS_1               0x0
 745 #define  STM_LCD_FCR_PS_2               0x1
 746 #define  STM_LCD_FCR_PS_4               0x2
 747 #define  STM_LCD_FCR_PS_8               0x3
 748 #define  STM_LCD_FCR_PS_16              0x4
 749 #define  STM_LCD_FCR_PS_32              0x5
 750 #define  STM_LCD_FCR_PS_64              0x6
 751 #define  STM_LCD_FCR_PS_128             0x7
 752 #define  STM_LCD_FCR_PS_256             0x8
 753 #define  STM_LCD_FCR_PS_512             0x9
 754 #define  STM_LCD_FCR_PS_1024            0xa
 755 #define  STM_LCD_FCR_PS_2048            0xb
 756 #define  STM_LCD_FCR_PS_4096            0xc
 757 #define  STM_LCD_FCR_PS_8192            0xd
 758 #define  STM_LCD_FCR_PS_16384           0xe
 759 #define  STM_LCD_FCR_PS_32768           0xf
 760 #define  STM_LCD_FCR_PS_MASK            0xf
 761
 762 #define STM_LCD_FCR_DIV                 (18)
 763 #define STM_LCD_FCR_DIV_16              0x0
 764 #define STM_LCD_FCR_DIV_17              0x1
 765 #define STM_LCD_FCR_DIV_18              0x2
 766 #define STM_LCD_FCR_DIV_19              0x3
 767 #define STM_LCD_FCR_DIV_20              0x4
 768 #define STM_LCD_FCR_DIV_21              0x5
 769 #define STM_LCD_FCR_DIV_22              0x6
 770 #define STM_LCD_FCR_DIV_23              0x7
 771 #define STM_LCD_FCR_DIV_24              0x8
 772 #define STM_LCD_FCR_DIV_25              0x9
 773 #define STM_LCD_FCR_DIV_26              0xa
 774 #define STM_LCD_FCR_DIV_27              0xb
 775 #define STM_LCD_FCR_DIV_28              0xc
 776 #define STM_LCD_FCR_DIV_29              0xd
 777 #define STM_LCD_FCR_DIV_30              0xe
 778 #define STM_LCD_FCR_DIV_31              0xf
 779 #define STM_LCD_FCR_DIV_MASK            0xf
 780
 781 #define STM_LCD_FCR_BLINK               (16)
 782 #define  STM_LCD_FCR_BLINK_DISABLE              0
 783 #define  STM_LCD_FCR_BLINK_SEG0_COM0            1
 784 #define  STM_LCD_FCR_BLINK_SEG0_COMALL          2
 785 #define  STM_LCD_FCR_BLINK_SEGALL_COMALL        3
 786 #define  STM_LCD_FCR_BLINK_MASK                 3
 787
 788 #define STM_LCD_FCR_BLINKF              (13)
 789 #define  STM_LCD_FCR_BLINKF_8                   0
 790 #define  STM_LCD_FCR_BLINKF_16                  1
 791 #define  STM_LCD_FCR_BLINKF_32                  2
 792 #define  STM_LCD_FCR_BLINKF_64                  3
 793 #define  STM_LCD_FCR_BLINKF_128                 4
 794 #define  STM_LCD_FCR_BLINKF_256                 5
 795 #define  STM_LCD_FCR_BLINKF_512                 6
 796 #define  STM_LCD_FCR_BLINKF_1024                7
 797 #define  STM_LCD_FCR_BLINKF_MASK                7
 798
 799 #define STM_LCD_FCR_CC                  (10)
 800 #define  STM_LCD_FCR_CC_MASK                    7
 801
 802 #define STM_LCD_FCR_DEAD                (7)
 803 #define  STM_LCD_FCR_DEAD_MASK                  7
 804
 805 #define STM_LCD_FCR_PON                 (4)
 806 #define  STM_LCD_FCR_PON_MASK                   7
 807
 808 #define STM_LCD_FCR_UDDIE               (3)
 809 #define STM_LCD_FCR_SOFIE               (1)
 810 #define STM_LCD_FCR_HD                  (0)
 811
 812 #define STM_LCD_SR_FCRSF                (5)
 813 #define STM_LCD_SR_RDY                  (4)
 814 #define STM_LCD_SR_UDD                  (3)
 815 #define STM_LCD_SR_UDR                  (2)
 816 #define STM_LCD_SR_SOF                  (1)
 817 #define STM_LCD_SR_ENS                  (0)
 818
 819 #define STM_LCD_CLR_UDDC                (3)
 820 #define STM_LCD_CLR_SOFC                (1)
 821
 822 /* The SYSTICK starts at 0xe000e010 */
 823
 824 struct stm_systick {
 825         vuint32_t       csr;
 826         vuint32_t       rvr;
 827         vuint32_t       cvr;
 828         vuint32_t       calib;
 829 };
 830
 831 extern struct stm_systick stm_systick;
 832
 833 #define STM_SYSTICK_CSR_ENABLE          0
 834 #define STM_SYSTICK_CSR_TICKINT         1
 835 #define STM_SYSTICK_CSR_CLKSOURCE       2
 836 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               0
 837 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK                 1
 838 #define STM_SYSTICK_CSR_COUNTFLAG       16
 839
 840 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 841
 842 struct stm_nvic {
 843         vuint32_t       iser[8];        /* 0x000 0xe000e100 Set Enable Register */
 844
 845         uint8_t         _unused020[0x080 - 0x020];
 846
 847         vuint32_t       icer[8];        /* 0x080 0xe000e180 Clear Enable Register */
 848
 849         uint8_t         _unused0a0[0x100 - 0x0a0];
 850
 851         vuint32_t       ispr[8];        /* 0x100 0xe000e200 Set Pending Register */
 852
 853         uint8_t         _unused120[0x180 - 0x120];
 854
 855         vuint32_t       icpr[8];        /* 0x180 0xe000e280 Clear Pending Register */
 856
 857         uint8_t         _unused1a0[0x200 - 0x1a0];
 858
 859         vuint32_t       iabr[8];        /* 0x200 0xe000e300 Active Bit Register */
 860
 861         uint8_t         _unused220[0x300 - 0x220];
 862
 863         vuint32_t       ipr[60];        /* 0x300 0xe000e400 Priority Register */
 864
 865         uint8_t         _unused3f0[0xc00 - 0x3f0];
 866
 867         vuint32_t       cpuid_base;     /* 0xc00 0xe000ed00 CPUID Base Register */
 868         vuint32_t       ics;            /* 0xc04 0xe000ed04 Interrupt Control State Register */
 869         vuint32_t       vto;            /* 0xc08 0xe000ed08 Vector Table Offset Register */
 870         vuint32_t       ai_rc;          /* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */
 871         vuint32_t       sc;             /* 0xc10 0xe000ed10 System Control Register */
 872         vuint32_t       cc;             /* 0xc14 0xe000ed14 Configuration Control Register */
 873
 874         uint8_t         _unusedc18[0xe00 - 0xc18];
 875
 876         vuint32_t       stir;           /* 0xe00 */
 877 };
 878
 879 extern struct stm_nvic stm_nvic;
 880
 881 #define IRQ_REG(irq)    ((irq) >> 5)
 882 #define IRQ_BIT(irq)    ((irq) & 0x1f)
 883 #define IRQ_MASK(irq)   (1 << IRQ_BIT(irq))
 884 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
 885
 886 static inline void
 887 stm_nvic_set_enable(int irq) {
 888         stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
 889 }
 890
 891 static inline void
 892 stm_nvic_clear_enable(int irq) {
 893         stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
 894 }
 895
 896 static inline int
 897 stm_nvic_enabled(int irq) {
 898         return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
 899 }
 900
 901 static inline void
 902 stm_nvic_set_pending(int irq) {
 903         stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
 904 }
 905
 906 static inline void
 907 stm_nvic_clear_pending(int irq) {
 908         stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
 909 }
 910
 911 static inline int
 912 stm_nvic_pending(int irq) {
 913         return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
 914 }
 915
 916 static inline int
 917 stm_nvic_active(int irq) {
 918         return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
 919 }
 920
 921 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 922 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 923 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 924
 925 static inline void
 926 stm_nvic_set_priority(int irq, uint8_t prio) {
 927         int             n = IRQ_PRIO_REG(irq);
 928         uint32_t        v;
 929
 930         v = stm_nvic.ipr[n];
 931         v &= ~IRQ_PRIO_MASK(irq);
 932         v |= (prio) << IRQ_PRIO_BIT(irq);
 933         stm_nvic.ipr[n] = v;
 934 }
 935
 936 static inline uint8_t
 937 stm_nvic_get_priority(int irq) {
 938         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 939 }
 940
 941 struct stm_scb {
 942         vuint32_t       cpuid;
 943         vuint32_t       icsr;
 944         vuint32_t       vtor;
 945         vuint32_t       aircr;
 946
 947         vuint32_t       scr;
 948         vuint32_t       ccr;
 949         vuint32_t       shpr1;
 950         vuint32_t       shpr2;
 951
 952         vuint32_t       shpr3;
 953         vuint32_t       shcrs;
 954         vuint32_t       cfsr;
 955         vuint32_t       hfsr;
 956
 957         uint32_t        unused_30;
 958         vuint32_t       mmfar;
 959         vuint32_t       bfar;
 960 };
 961
 962 extern struct stm_scb stm_scb;
 963
 964 #define STM_SCB_AIRCR_VECTKEY           16
 965 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
 966 #define STM_SCB_AIRCR_PRIGROUP          8
 967 #define STM_SCB_AIRCR_SYSRESETREQ       2
 968 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
 969 #define STM_SCB_AIRCR_VECTRESET         0
 970
 971 struct stm_mpu {
 972         vuint32_t       typer;
 973         vuint32_t       cr;
 974         vuint32_t       rnr;
 975         vuint32_t       rbar;
 976
 977         vuint32_t       rasr;
 978         vuint32_t       rbar_a1;
 979         vuint32_t       rasr_a1;
 980         vuint32_t       rbar_a2;
 981         vuint32_t       rasr_a2;
 982         vuint32_t       rbar_a3;
 983         vuint32_t       rasr_a3;
 984 };
 985
 986 extern struct stm_mpu stm_mpu;
 987
 988 #define STM_MPU_TYPER_IREGION   16
 989 #define  STM_MPU_TYPER_IREGION_MASK     0xff
 990 #define STM_MPU_TYPER_DREGION   8
 991 #define  STM_MPU_TYPER_DREGION_MASK     0xff
 992 #define STM_MPU_TYPER_SEPARATE  0
 993
 994 #define STM_MPU_CR_PRIVDEFENA   2
 995 #define STM_MPU_CR_HFNMIENA     1
 996 #define STM_MPU_CR_ENABLE       0
 997
 998 #define STM_MPU_RNR_REGION      0
 999 #define STM_MPU_RNR_REGION_MASK         0xff
1000
1001 #define STM_MPU_RBAR_ADDR       5
1002 #define STM_MPU_RBAR_ADDR_MASK          0x7ffffff
1003
1004 #define STM_MPU_RBAR_VALID      4
1005 #define STM_MPU_RBAR_REGION     0
1006 #define STM_MPU_RBAR_REGION_MASK        0xf
1007
1008 #define STM_MPU_RASR_XN         28
1009 #define STM_MPU_RASR_AP         24
1010 #define  STM_MPU_RASR_AP_NONE_NONE      0
1011 #define  STM_MPU_RASR_AP_RW_NONE        1
1012 #define  STM_MPU_RASR_AP_RW_RO          2
1013 #define  STM_MPU_RASR_AP_RW_RW          3
1014 #define  STM_MPU_RASR_AP_RO_NONE        5
1015 #define  STM_MPU_RASR_AP_RO_RO          6
1016 #define  STM_MPU_RASR_AP_MASK           7
1017 #define STM_MPU_RASR_TEX        19
1018 #define  STM_MPU_RASR_TEX_MASK          7
1019 #define STM_MPU_RASR_S          18
1020 #define STM_MPU_RASR_C          17
1021 #define STM_MPU_RASR_B          16
1022 #define STM_MPU_RASR_SRD        8
1023 #define  STM_MPU_RASR_SRD_MASK          0xff
1024 #define STM_MPU_RASR_SIZE       1
1025 #define  STM_MPU_RASR_SIZE_MASK         0x1f
1026 #define STM_MPU_RASR_ENABLE     0
1027
1028 #define isr(name) void stm_ ## name ## _isr(void);
1029
1030 isr(nmi)
1031 isr(hardfault)
1032 isr(memmanage)
1033 isr(busfault)
1034 isr(usagefault)
1035 isr(svc)
1036 isr(debugmon)
1037 isr(pendsv)
1038 isr(systick)
1039 isr(wwdg)
1040 isr(pvd)
1041 isr(tamper_stamp)
1042 isr(rtc_wkup)
1043 isr(flash)
1044 isr(rcc)
1045 isr(exti0)
1046 isr(exti1)
1047 isr(exti2)
1048 isr(exti3)
1049 isr(exti4)
1050 isr(dma1_channel1)
1051 isr(dma1_channel2)
1052 isr(dma1_channel3)
1053 isr(dma1_channel4)
1054 isr(dma1_channel5)
1055 isr(dma1_channel6)
1056 isr(dma1_channel7)
1057 isr(adc1)
1058 isr(usb_hp)
1059 isr(usb_lp)
1060 isr(dac)
1061 isr(comp)
1062 isr(exti9_5)
1063 isr(lcd)
1064 isr(tim9)
1065 isr(tim10)
1066 isr(tim11)
1067 isr(tim2)
1068 isr(tim3)
1069 isr(tim4)
1070 isr(i2c1_ev)
1071 isr(i2c1_er)
1072 isr(i2c2_ev)
1073 isr(i2c2_er)
1074 isr(spi1)
1075 isr(spi2)
1076 isr(usart1)
1077 isr(usart2)
1078 isr(usart3)
1079 isr(exti15_10)
1080 isr(rtc_alarm)
1081 isr(usb_fs_wkup)
1082 isr(tim6)
1083 isr(tim7)
1084
1085 #undef isr
1086
1087 #define STM_ISR_WWDG_POS                0
1088 #define STM_ISR_PVD_POS                 1
1089 #define STM_ISR_TAMPER_STAMP_POS        2
1090 #define STM_ISR_RTC_WKUP_POS            3
1091 #define STM_ISR_FLASH_POS               4
1092 #define STM_ISR_RCC_POS                 5
1093 #define STM_ISR_EXTI0_POS               6
1094 #define STM_ISR_EXTI1_POS               7
1095 #define STM_ISR_EXTI2_POS               8
1096 #define STM_ISR_EXTI3_POS               9
1097 #define STM_ISR_EXTI4_POS               10
1098 #define STM_ISR_DMA1_CHANNEL1_POS       11
1099 #define STM_ISR_DMA2_CHANNEL1_POS       12
1100 #define STM_ISR_DMA3_CHANNEL1_POS       13
1101 #define STM_ISR_DMA4_CHANNEL1_POS       14
1102 #define STM_ISR_DMA5_CHANNEL1_POS       15
1103 #define STM_ISR_DMA6_CHANNEL1_POS       16
1104 #define STM_ISR_DMA7_CHANNEL1_POS       17
1105 #define STM_ISR_ADC1_POS                18
1106 #define STM_ISR_USB_HP_POS              19
1107 #define STM_ISR_USB_LP_POS              20
1108 #define STM_ISR_DAC_POS                 21
1109 #define STM_ISR_COMP_POS                22
1110 #define STM_ISR_EXTI9_5_POS             23
1111 #define STM_ISR_LCD_POS                 24
1112 #define STM_ISR_TIM9_POS                25
1113 #define STM_ISR_TIM10_POS               26
1114 #define STM_ISR_TIM11_POS               27
1115 #define STM_ISR_TIM2_POS                28
1116 #define STM_ISR_TIM3_POS                29
1117 #define STM_ISR_TIM4_POS                30
1118 #define STM_ISR_I2C1_EV_POS             31
1119 #define STM_ISR_I2C1_ER_POS             32
1120 #define STM_ISR_I2C2_EV_POS             33
1121 #define STM_ISR_I2C2_ER_POS             34
1122 #define STM_ISR_SPI1_POS                35
1123 #define STM_ISR_SPI2_POS                36
1124 #define STM_ISR_USART1_POS              37
1125 #define STM_ISR_USART2_POS              38
1126 #define STM_ISR_USART3_POS              39
1127 #define STM_ISR_EXTI15_10_POS           40
1128 #define STM_ISR_RTC_ALARM_POS           41
1129 #define STM_ISR_USB_FS_WKUP_POS         42
1130 #define STM_ISR_TIM6_POS                43
1131 #define STM_ISR_TIM7_POS                44
1132
1133 struct stm_syscfg {
1134         vuint32_t       memrmp;
1135         vuint32_t       pmc;
1136         vuint32_t       exticr[4];
1137 };
1138
1139 extern struct stm_syscfg stm_syscfg;
1140
1141 #define STM_SYSCFG_MEMRMP_MEM_MODE      0
1142 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH          0
1143 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH        1
1144 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SRAM                3
1145 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MASK                3
1146
1147 #define STM_SYSCFG_PMC_USB_PU           0
1148
1149 #define STM_SYSCFG_EXTICR_PA            0
1150 #define STM_SYSCFG_EXTICR_PB            1
1151 #define STM_SYSCFG_EXTICR_PC            2
1152 #define STM_SYSCFG_EXTICR_PD            3
1153 #define STM_SYSCFG_EXTICR_PE            4
1154 #define STM_SYSCFG_EXTICR_PH            5
1155
1156 static inline void
1157 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1158         uint8_t reg = pin >> 2;
1159         uint8_t shift = (pin & 3) << 2;
1160         uint8_t val = 0;
1161
1162         /* Enable SYSCFG */
1163         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
1164
1165         if (gpio == &stm_gpioa)
1166                 val = STM_SYSCFG_EXTICR_PA;
1167         else if (gpio == &stm_gpiob)
1168                 val = STM_SYSCFG_EXTICR_PB;
1169         else if (gpio == &stm_gpioc)
1170                 val = STM_SYSCFG_EXTICR_PC;
1171         else if (gpio == &stm_gpiod)
1172                 val = STM_SYSCFG_EXTICR_PD;
1173         else if (gpio == &stm_gpioe)
1174                 val = STM_SYSCFG_EXTICR_PE;
1175
1176         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
1177 }
1178
1179
1180 struct stm_dma_channel {
1181         vuint32_t       ccr;
1182         vuint32_t       cndtr;
1183         vvoid_t         cpar;
1184         vvoid_t         cmar;
1185         vuint32_t       reserved;
1186 };
1187
1188 #define STM_NUM_DMA     7
1189
1190 struct stm_dma {
1191         vuint32_t               isr;
1192         vuint32_t               ifcr;
1193         struct stm_dma_channel  channel[STM_NUM_DMA];
1194 };
1195
1196 extern struct stm_dma stm_dma;
1197
1198 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
1199  */
1200
1201 #define STM_DMA_INDEX(channel)          ((channel) - 1)
1202
1203 #define STM_DMA_ISR(index)              ((index) << 2)
1204 #define STM_DMA_ISR_MASK                        0xf
1205 #define STM_DMA_ISR_TEIF                        3
1206 #define STM_DMA_ISR_HTIF                        2
1207 #define STM_DMA_ISR_TCIF                        1
1208 #define STM_DMA_ISR_GIF                         0
1209
1210 #define STM_DMA_IFCR(index)             ((index) << 2)
1211 #define STM_DMA_IFCR_MASK                       0xf
1212 #define STM_DMA_IFCR_CTEIF                      3
1213 #define STM_DMA_IFCR_CHTIF                      2
1214 #define STM_DMA_IFCR_CTCIF                      1
1215 #define STM_DMA_IFCR_CGIF                       0
1216
1217 #define STM_DMA_CCR_MEM2MEM             (14)
1218
1219 #define STM_DMA_CCR_PL                  (12)
1220 #define  STM_DMA_CCR_PL_LOW                     (0)
1221 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
1222 #define  STM_DMA_CCR_PL_HIGH                    (2)
1223 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
1224 #define  STM_DMA_CCR_PL_MASK                    (3)
1225
1226 #define STM_DMA_CCR_MSIZE               (10)
1227 #define  STM_DMA_CCR_MSIZE_8                    (0)
1228 #define  STM_DMA_CCR_MSIZE_16                   (1)
1229 #define  STM_DMA_CCR_MSIZE_32                   (2)
1230 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
1231
1232 #define STM_DMA_CCR_PSIZE               (8)
1233 #define  STM_DMA_CCR_PSIZE_8                    (0)
1234 #define  STM_DMA_CCR_PSIZE_16                   (1)
1235 #define  STM_DMA_CCR_PSIZE_32                   (2)
1236 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
1237
1238 #define STM_DMA_CCR_MINC                (7)
1239 #define STM_DMA_CCR_PINC                (6)
1240 #define STM_DMA_CCR_CIRC                (5)
1241 #define STM_DMA_CCR_DIR                 (4)
1242 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
1243 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
1244 #define STM_DMA_CCR_TEIE                (3)
1245 #define STM_DMA_CCR_HTIE                (2)
1246 #define STM_DMA_CCR_TCIE                (1)
1247 #define STM_DMA_CCR_EN                  (0)
1248
1249 #define STM_DMA_CHANNEL_ADC1            1
1250 #define STM_DMA_CHANNEL_SPI1_RX         2
1251 #define STM_DMA_CHANNEL_SPI1_TX         3
1252 #define STM_DMA_CHANNEL_SPI2_RX         4
1253 #define STM_DMA_CHANNEL_SPI2_TX         5
1254 #define STM_DMA_CHANNEL_USART3_TX       2
1255 #define STM_DMA_CHANNEL_USART3_RX       3
1256 #define STM_DMA_CHANNEL_USART1_TX       4
1257 #define STM_DMA_CHANNEL_USART1_RX       5
1258 #define STM_DMA_CHANNEL_USART2_RX       6
1259 #define STM_DMA_CHANNEL_USART2_TX       7
1260 #define STM_DMA_CHANNEL_I2C2_TX         4
1261 #define STM_DMA_CHANNEL_I2C2_RX         5
1262 #define STM_DMA_CHANNEL_I2C1_TX         6
1263 #define STM_DMA_CHANNEL_I2C1_RX         7
1264 #define STM_DMA_CHANNEL_TIM2_CH3        1
1265 #define STM_DMA_CHANNEL_TIM2_UP         2
1266 #define STM_DMA_CHANNEL_TIM2_CH1        5
1267 #define STM_DMA_CHANNEL_TIM2_CH2        7
1268 #define STM_DMA_CHANNEL_TIM2_CH4        7
1269 #define STM_DMA_CHANNEL_TIM3_CH3        2
1270 #define STM_DMA_CHANNEL_TIM3_CH4        3
1271 #define STM_DMA_CHANNEL_TIM3_UP         3
1272 #define STM_DMA_CHANNEL_TIM3_CH1        6
1273 #define STM_DMA_CHANNEL_TIM3_TRIG       6
1274 #define STM_DMA_CHANNEL_TIM4_CH1        1
1275 #define STM_DMA_CHANNEL_TIM4_CH2        4
1276 #define STM_DMA_CHANNEL_TIM4_CH3        5
1277 #define STM_DMA_CHANNEL_TIM4_UP         7
1278 #define STM_DMA_CHANNEL_TIM6_UP_DA      2
1279 #define STM_DMA_CHANNEL_C_CHANNEL1      2
1280 #define STM_DMA_CHANNEL_TIM7_UP_DA      3
1281 #define STM_DMA_CHANNEL_C_CHANNEL2      3
1282
1283 /*
1284  * Only spi channel 1 and 2 can use DMA
1285  */
1286 #define STM_NUM_SPI     2
1287
1288 struct stm_spi {
1289         vuint32_t       cr1;
1290         vuint32_t       cr2;
1291         vuint32_t       sr;
1292         vuint32_t       dr;
1293         vuint32_t       crcpr;
1294         vuint32_t       rxcrcr;
1295         vuint32_t       txcrcr;
1296 };
1297
1298 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1299
1300 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1301  */
1302
1303 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1304
1305 #define STM_SPI_CR1_BIDIMODE            15
1306 #define STM_SPI_CR1_BIDIOE              14
1307 #define STM_SPI_CR1_CRCEN               13
1308 #define STM_SPI_CR1_CRCNEXT             12
1309 #define STM_SPI_CR1_DFF                 11
1310 #define STM_SPI_CR1_RXONLY              10
1311 #define STM_SPI_CR1_SSM                 9
1312 #define STM_SPI_CR1_SSI                 8
1313 #define STM_SPI_CR1_LSBFIRST            7
1314 #define STM_SPI_CR1_SPE                 6
1315 #define STM_SPI_CR1_BR                  3
1316 #define  STM_SPI_CR1_BR_PCLK_2                  0
1317 #define  STM_SPI_CR1_BR_PCLK_4                  1
1318 #define  STM_SPI_CR1_BR_PCLK_8                  2
1319 #define  STM_SPI_CR1_BR_PCLK_16                 3
1320 #define  STM_SPI_CR1_BR_PCLK_32                 4
1321 #define  STM_SPI_CR1_BR_PCLK_64                 5
1322 #define  STM_SPI_CR1_BR_PCLK_128                6
1323 #define  STM_SPI_CR1_BR_PCLK_256                7
1324 #define  STM_SPI_CR1_BR_MASK                    7
1325
1326 #define STM_SPI_CR1_MSTR                2
1327 #define STM_SPI_CR1_CPOL                1
1328 #define STM_SPI_CR1_CPHA                0
1329
1330 #define STM_SPI_CR2_TXEIE       7
1331 #define STM_SPI_CR2_RXNEIE      6
1332 #define STM_SPI_CR2_ERRIE       5
1333 #define STM_SPI_CR2_SSOE        2
1334 #define STM_SPI_CR2_TXDMAEN     1
1335 #define STM_SPI_CR2_RXDMAEN     0
1336
1337 #define STM_SPI_SR_BSY          7
1338 #define STM_SPI_SR_OVR          6
1339 #define STM_SPI_SR_MODF         5
1340 #define STM_SPI_SR_CRCERR       4
1341 #define STM_SPI_SR_TXE          1
1342 #define STM_SPI_SR_RXNE         0
1343
1344 struct stm_adc {
1345         vuint32_t       sr;
1346         vuint32_t       cr1;
1347         vuint32_t       cr2;
1348         vuint32_t       smpr1;
1349         vuint32_t       smpr2;
1350         vuint32_t       smpr3;
1351         vuint32_t       jofr1;
1352         vuint32_t       jofr2;
1353         vuint32_t       jofr3;
1354         vuint32_t       jofr4;
1355         vuint32_t       htr;
1356         vuint32_t       ltr;
1357         vuint32_t       sqr1;
1358         vuint32_t       sqr2;
1359         vuint32_t       sqr3;
1360         vuint32_t       sqr4;
1361         vuint32_t       sqr5;
1362         vuint32_t       jsqr;
1363         vuint32_t       jdr1;
1364         vuint32_t       jdr2;
1365         vuint32_t       jdr3;
1366         vuint32_t       jdr4;
1367         vuint32_t       dr;
1368         uint8_t         reserved[0x300 - 0x5c];
1369         vuint32_t       csr;
1370         vuint32_t       ccr;
1371 };
1372
1373 extern struct stm_adc stm_adc;
1374
1375 #define STM_ADC_SR_JCNR         9
1376 #define STM_ADC_SR_RCNR         8
1377 #define STM_ADC_SR_ADONS        6
1378 #define STM_ADC_SR_OVR          5
1379 #define STM_ADC_SR_STRT         4
1380 #define STM_ADC_SR_JSTRT        3
1381 #define STM_ADC_SR_JEOC         2
1382 #define STM_ADC_SR_EOC          1
1383 #define STM_ADC_SR_AWD          0
1384
1385 #define STM_ADC_CR1_OVRIE       26
1386 #define STM_ADC_CR1_RES         24
1387 #define  STM_ADC_CR1_RES_12             0
1388 #define  STM_ADC_CR1_RES_10             1
1389 #define  STM_ADC_CR1_RES_8              2
1390 #define  STM_ADC_CR1_RES_6              3
1391 #define  STM_ADC_CR1_RES_MASK           3
1392 #define STM_ADC_CR1_AWDEN       23
1393 #define STM_ADC_CR1_JAWDEN      22
1394 #define STM_ADC_CR1_PDI         17
1395 #define STM_ADC_CR1_PDD         16
1396 #define STM_ADC_CR1_DISCNUM     13
1397 #define  STM_ADC_CR1_DISCNUM_1          0
1398 #define  STM_ADC_CR1_DISCNUM_2          1
1399 #define  STM_ADC_CR1_DISCNUM_3          2
1400 #define  STM_ADC_CR1_DISCNUM_4          3
1401 #define  STM_ADC_CR1_DISCNUM_5          4
1402 #define  STM_ADC_CR1_DISCNUM_6          5
1403 #define  STM_ADC_CR1_DISCNUM_7          6
1404 #define  STM_ADC_CR1_DISCNUM_8          7
1405 #define  STM_ADC_CR1_DISCNUM_MASK       7
1406 #define STM_ADC_CR1_JDISCEN     12
1407 #define STM_ADC_CR1_DISCEN      11
1408 #define STM_ADC_CR1_JAUTO       10
1409 #define STM_ADC_CR1_AWDSGL      9
1410 #define STM_ADC_CR1_SCAN        8
1411 #define STM_ADC_CR1_JEOCIE      7
1412 #define STM_ADC_CR1_AWDIE       6
1413 #define STM_ADC_CR1_EOCIE       5
1414 #define STM_ADC_CR1_AWDCH       0
1415 #define  STM_ADC_CR1_AWDCH_MASK         0x1f
1416
1417 #define STM_ADC_CR2_SWSTART     30
1418 #define STM_ADC_CR2_EXTEN       28
1419 #define  STM_ADC_CR2_EXTEN_DISABLE      0
1420 #define  STM_ADC_CR2_EXTEN_RISING       1
1421 #define  STM_ADC_CR2_EXTEN_FALLING      2
1422 #define  STM_ADC_CR2_EXTEN_BOTH         3
1423 #define  STM_ADC_CR2_EXTEN_MASK         3
1424 #define STM_ADC_CR2_EXTSEL      24
1425 #define  STM_ADC_CR2_EXTSEL_TIM9_CC2    0
1426 #define  STM_ADC_CR2_EXTSEL_TIM9_TRGO   1
1427 #define  STM_ADC_CR2_EXTSEL_TIM2_CC3    2
1428 #define  STM_ADC_CR2_EXTSEL_TIM2_CC2    3
1429 #define  STM_ADC_CR2_EXTSEL_TIM3_TRGO   4
1430 #define  STM_ADC_CR2_EXTSEL_TIM4_CC4    5
1431 #define  STM_ADC_CR2_EXTSEL_TIM2_TRGO   6
1432 #define  STM_ADC_CR2_EXTSEL_TIM3_CC1    7
1433 #define  STM_ADC_CR2_EXTSEL_TIM3_CC3    8
1434 #define  STM_ADC_CR2_EXTSEL_TIM4_TRGO   9
1435 #define  STM_ADC_CR2_EXTSEL_TIM6_TRGO   10
1436 #define  STM_ADC_CR2_EXTSEL_EXTI_11     15
1437 #define  STM_ADC_CR2_EXTSEL_MASK        15
1438 #define STM_ADC_CR2_JWSTART     22
1439 #define STM_ADC_CR2_JEXTEN      20
1440 #define  STM_ADC_CR2_JEXTEN_DISABLE     0
1441 #define  STM_ADC_CR2_JEXTEN_RISING      1
1442 #define  STM_ADC_CR2_JEXTEN_FALLING     2
1443 #define  STM_ADC_CR2_JEXTEN_BOTH        3
1444 #define  STM_ADC_CR2_JEXTEN_MASK        3
1445 #define STM_ADC_CR2_JEXTSEL     16
1446 #define  STM_ADC_CR2_JEXTSEL_TIM9_CC1   0
1447 #define  STM_ADC_CR2_JEXTSEL_TIM9_TRGO  1
1448 #define  STM_ADC_CR2_JEXTSEL_TIM2_TRGO  2
1449 #define  STM_ADC_CR2_JEXTSEL_TIM2_CC1   3
1450 #define  STM_ADC_CR2_JEXTSEL_TIM3_CC4   4
1451 #define  STM_ADC_CR2_JEXTSEL_TIM4_TRGO  5
1452 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC1   6
1453 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC2   7
1454 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC3   8
1455 #define  STM_ADC_CR2_JEXTSEL_TIM10_CC1  9
1456 #define  STM_ADC_CR2_JEXTSEL_TIM7_TRGO  10
1457 #define  STM_ADC_CR2_JEXTSEL_EXTI_15    15
1458 #define  STM_ADC_CR2_JEXTSEL_MASK       15
1459 #define STM_ADC_CR2_ALIGN       11
1460 #define STM_ADC_CR2_EOCS        10
1461 #define STM_ADC_CR2_DDS         9
1462 #define STM_ADC_CR2_DMA         8
1463 #define STM_ADC_CR2_DELS        4
1464 #define  STM_ADC_CR2_DELS_NONE          0
1465 #define  STM_ADC_CR2_DELS_UNTIL_READ    1
1466 #define  STM_ADC_CR2_DELS_7             2
1467 #define  STM_ADC_CR2_DELS_15            3
1468 #define  STM_ADC_CR2_DELS_31            4
1469 #define  STM_ADC_CR2_DELS_63            5
1470 #define  STM_ADC_CR2_DELS_127           6
1471 #define  STM_ADC_CR2_DELS_255           7
1472 #define  STM_ADC_CR2_DELS_MASK          7
1473 #define STM_ADC_CR2_CONT        1
1474 #define STM_ADC_CR2_ADON        0
1475
1476 #define STM_ADC_CCR_TSVREFE     23
1477 #define STM_ADC_CCR_ADCPRE      16
1478 #define  STM_ADC_CCR_ADCPRE_HSI_1       0
1479 #define  STM_ADC_CCR_ADCPRE_HSI_2       1
1480 #define  STM_ADC_CCR_ADCPRE_HSI_4       2
1481 #define  STM_ADC_CCR_ADCPRE_MASK        3
1482
1483 struct stm_temp_cal {
1484         uint16_t        vref;
1485         uint16_t        ts_cal_cold;
1486         uint16_t        reserved;
1487         uint16_t        ts_cal_hot;
1488 };
1489
1490 extern struct stm_temp_cal      stm_temp_cal;
1491
1492 #define stm_temp_cal_cold       25
1493 #define stm_temp_cal_hot        110
1494
1495 struct stm_dbg_mcu {
1496         uint32_t        idcode;
1497 };
1498
1499 extern struct stm_dbg_mcu       stm_dbg_mcu;
1500
1501 static inline uint16_t
1502 stm_dev_id(void) {
1503         return stm_dbg_mcu.idcode & 0xfff;
1504 }
1505
1506 struct stm_flash_size {
1507         uint16_t        f_size;
1508 };
1509
1510 extern struct stm_flash_size    stm_flash_size_medium;
1511 extern struct stm_flash_size    stm_flash_size_large;
1512
1513 /* Returns flash size in bytes */
1514 extern uint32_t
1515 stm_flash_size(void);
1516
1517 struct stm_device_id {
1518         uint32_t        u_id0;
1519         uint32_t        u_id1;
1520         uint32_t        u_id2;
1521 };
1522
1523 extern struct stm_device_id     stm_device_id;
1524
1525 #define STM_NUM_I2C     2
1526
1527 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1528
1529 struct stm_i2c {
1530         vuint32_t       cr1;
1531         vuint32_t       cr2;
1532         vuint32_t       oar1;
1533         vuint32_t       oar2;
1534         vuint32_t       dr;
1535         vuint32_t       sr1;
1536         vuint32_t       sr2;
1537         vuint32_t       ccr;
1538         vuint32_t       trise;
1539 };
1540
1541 extern struct stm_i2c stm_i2c1, stm_i2c2;
1542
1543 #define STM_I2C_CR1_SWRST       15
1544 #define STM_I2C_CR1_ALERT       13
1545 #define STM_I2C_CR1_PEC         12
1546 #define STM_I2C_CR1_POS         11
1547 #define STM_I2C_CR1_ACK         10
1548 #define STM_I2C_CR1_STOP        9
1549 #define STM_I2C_CR1_START       8
1550 #define STM_I2C_CR1_NOSTRETCH   7
1551 #define STM_I2C_CR1_ENGC        6
1552 #define STM_I2C_CR1_ENPEC       5
1553 #define STM_I2C_CR1_ENARP       4
1554 #define STM_I2C_CR1_SMBTYPE     3
1555 #define STM_I2C_CR1_SMBUS       1
1556 #define STM_I2C_CR1_PE          0
1557
1558 #define STM_I2C_CR2_LAST        12
1559 #define STM_I2C_CR2_DMAEN       11
1560 #define STM_I2C_CR2_ITBUFEN     10
1561 #define STM_I2C_CR2_ITEVTEN     9
1562 #define STM_I2C_CR2_ITERREN     8
1563 #define STM_I2C_CR2_FREQ        0
1564 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1565 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1566 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1567 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1568 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1569 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1570
1571 #define STM_I2C_SR1_SMBALERT    15
1572 #define STM_I2C_SR1_TIMEOUT     14
1573 #define STM_I2C_SR1_PECERR      12
1574 #define STM_I2C_SR1_OVR         11
1575 #define STM_I2C_SR1_AF          10
1576 #define STM_I2C_SR1_ARLO        9
1577 #define STM_I2C_SR1_BERR        8
1578 #define STM_I2C_SR1_TXE         7
1579 #define STM_I2C_SR1_RXNE        6
1580 #define STM_I2C_SR1_STOPF       4
1581 #define STM_I2C_SR1_ADD10       3
1582 #define STM_I2C_SR1_BTF         2
1583 #define STM_I2C_SR1_ADDR        1
1584 #define STM_I2C_SR1_SB          0
1585
1586 #define STM_I2C_SR2_PEC         8
1587 #define  STM_I2C_SR2_PEC_MASK   0xff00
1588 #define STM_I2C_SR2_DUALF       7
1589 #define STM_I2C_SR2_SMBHOST     6
1590 #define STM_I2C_SR2_SMBDEFAULT  5
1591 #define STM_I2C_SR2_GENCALL     4
1592 #define STM_I2C_SR2_TRA         2
1593 #define STM_I2C_SR2_BUSY        1
1594 #define STM_I2C_SR2_MSL         0
1595
1596 #define STM_I2C_CCR_FS          15
1597 #define STM_I2C_CCR_DUTY        14
1598 #define STM_I2C_CCR_CCR         0
1599 #define  STM_I2C_CCR_MASK       0x7ff
1600
1601 struct stm_tim234 {
1602         vuint32_t       cr1;
1603         vuint32_t       cr2;
1604         vuint32_t       smcr;
1605         vuint32_t       dier;
1606
1607         vuint32_t       sr;
1608         vuint32_t       egr;
1609         vuint32_t       ccmr1;
1610         vuint32_t       ccmr2;
1611
1612         vuint32_t       ccer;
1613         vuint32_t       cnt;
1614         vuint32_t       psc;
1615         vuint32_t       arr;
1616
1617         uint32_t        reserved_30;
1618         vuint32_t       ccr1;
1619         vuint32_t       ccr2;
1620         vuint32_t       ccr3;
1621
1622         vuint32_t       ccr4;
1623         uint32_t        reserved_44;
1624         vuint32_t       dcr;
1625         vuint32_t       dmar;
1626
1627         uint32_t        reserved_50;
1628 };
1629
1630 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1631
1632 #define STM_TIM234_CR1_CKD      8
1633 #define  STM_TIM234_CR1_CKD_1           0
1634 #define  STM_TIM234_CR1_CKD_2           1
1635 #define  STM_TIM234_CR1_CKD_4           2
1636 #define  STM_TIM234_CR1_CKD_MASK        3
1637 #define STM_TIM234_CR1_ARPE     7
1638 #define STM_TIM234_CR1_CMS      5
1639 #define  STM_TIM234_CR1_CMS_EDGE        0
1640 #define  STM_TIM234_CR1_CMS_CENTER_1    1
1641 #define  STM_TIM234_CR1_CMS_CENTER_2    2
1642 #define  STM_TIM234_CR1_CMS_CENTER_3    3
1643 #define  STM_TIM234_CR1_CMS_MASK        3
1644 #define STM_TIM234_CR1_DIR      4
1645 #define  STM_TIM234_CR1_DIR_UP          0
1646 #define  STM_TIM234_CR1_DIR_DOWN        1
1647 #define STM_TIM234_CR1_OPM      3
1648 #define STM_TIM234_CR1_URS      2
1649 #define STM_TIM234_CR1_UDIS     1
1650 #define STM_TIM234_CR1_CEN      0
1651
1652 #define STM_TIM234_CR2_TI1S     7
1653 #define STM_TIM234_CR2_MMS      4
1654 #define  STM_TIM234_CR2_MMS_RESET               0
1655 #define  STM_TIM234_CR2_MMS_ENABLE              1
1656 #define  STM_TIM234_CR2_MMS_UPDATE              2
1657 #define  STM_TIM234_CR2_MMS_COMPARE_PULSE       3
1658 #define  STM_TIM234_CR2_MMS_COMPARE_OC1REF      4
1659 #define  STM_TIM234_CR2_MMS_COMPARE_OC2REF      5
1660 #define  STM_TIM234_CR2_MMS_COMPARE_OC3REF      6
1661 #define  STM_TIM234_CR2_MMS_COMPARE_OC4REF      7
1662 #define  STM_TIM234_CR2_MMS_MASK                7
1663 #define STM_TIM234_CR2_CCDS     3
1664
1665 #define STM_TIM234_SMCR_ETP     15
1666 #define STM_TIM234_SMCR_ECE     14
1667 #define STM_TIM234_SMCR_ETPS    12
1668 #define  STM_TIM234_SMCR_ETPS_OFF               0
1669 #define  STM_TIM234_SMCR_ETPS_DIV_2             1
1670 #define  STM_TIM234_SMCR_ETPS_DIV_4             2
1671 #define  STM_TIM234_SMCR_ETPS_DIV_8             3
1672 #define  STM_TIM234_SMCR_ETPS_MASK              3
1673 #define STM_TIM234_SMCR_ETF     8
1674 #define  STM_TIM234_SMCR_ETF_NONE               0
1675 #define  STM_TIM234_SMCR_ETF_INT_N_2            1
1676 #define  STM_TIM234_SMCR_ETF_INT_N_4            2
1677 #define  STM_TIM234_SMCR_ETF_INT_N_8            3
1678 #define  STM_TIM234_SMCR_ETF_DTS_2_N_6          4
1679 #define  STM_TIM234_SMCR_ETF_DTS_2_N_8          5
1680 #define  STM_TIM234_SMCR_ETF_DTS_4_N_6          6
1681 #define  STM_TIM234_SMCR_ETF_DTS_4_N_8          7
1682 #define  STM_TIM234_SMCR_ETF_DTS_8_N_6          8
1683 #define  STM_TIM234_SMCR_ETF_DTS_8_N_8          9
1684 #define  STM_TIM234_SMCR_ETF_DTS_16_N_5         10
1685 #define  STM_TIM234_SMCR_ETF_DTS_16_N_6         11
1686 #define  STM_TIM234_SMCR_ETF_DTS_16_N_8         12
1687 #define  STM_TIM234_SMCR_ETF_DTS_32_N_5         13
1688 #define  STM_TIM234_SMCR_ETF_DTS_32_N_6         14
1689 #define  STM_TIM234_SMCR_ETF_DTS_32_N_8         15
1690 #define  STM_TIM234_SMCR_ETF_MASK               15
1691 #define STM_TIM234_SMCR_MSM     7
1692 #define STM_TIM234_SMCR_TS      4
1693 #define  STM_TIM234_SMCR_TS_ITR0                0
1694 #define  STM_TIM234_SMCR_TS_ITR1                1
1695 #define  STM_TIM234_SMCR_TS_ITR2                2
1696 #define  STM_TIM234_SMCR_TS_ITR3                3
1697 #define  STM_TIM234_SMCR_TS_TI1F_ED             4
1698 #define  STM_TIM234_SMCR_TS_TI1FP1              5
1699 #define  STM_TIM234_SMCR_TS_TI2FP2              6
1700 #define  STM_TIM234_SMCR_TS_ETRF                7
1701 #define  STM_TIM234_SMCR_TS_MASK                7
1702 #define STM_TIM234_SMCR_OCCS    3
1703 #define STM_TIM234_SMCR_SMS     0
1704 #define  STM_TIM234_SMCR_SMS_DISABLE            0
1705 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_1     1
1706 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_2     2
1707 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_3     3
1708 #define  STM_TIM234_SMCR_SMS_RESET_MODE         4
1709 #define  STM_TIM234_SMCR_SMS_GATED_MODE         5
1710 #define  STM_TIM234_SMCR_SMS_TRIGGER_MODE       6
1711 #define  STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK     7
1712 #define  STM_TIM234_SMCR_SMS_MASK               7
1713
1714 #define STM_TIM234_SR_CC4OF     12
1715 #define STM_TIM234_SR_CC3OF     11
1716 #define STM_TIM234_SR_CC2OF     10
1717 #define STM_TIM234_SR_CC1OF     9
1718 #define STM_TIM234_SR_TIF       6
1719 #define STM_TIM234_SR_CC4IF     4
1720 #define STM_TIM234_SR_CC3IF     3
1721 #define STM_TIM234_SR_CC2IF     2
1722 #define STM_TIM234_SR_CC1IF     1
1723 #define STM_TIM234_SR_UIF       0
1724
1725 #define STM_TIM234_EGR_TG       6
1726 #define STM_TIM234_EGR_CC4G     4
1727 #define STM_TIM234_EGR_CC3G     3
1728 #define STM_TIM234_EGR_CC2G     2
1729 #define STM_TIM234_EGR_CC1G     1
1730 #define STM_TIM234_EGR_UG       0
1731
1732 #define STM_TIM234_CCMR1_OC2CE  15
1733 #define STM_TIM234_CCMR1_OC2M   12
1734 #define  STM_TIM234_CCMR1_OC2M_FROZEN                   0
1735 #define  STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH        1
1736 #define  STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH         2
1737 #define  STM_TIM234_CCMR1_OC2M_TOGGLE                   3
1738 #define  STM_TIM234_CCMR1_OC2M_FORCE_LOW                4
1739 #define  STM_TIM234_CCMR1_OC2M_FORCE_HIGH               5
1740 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_1               6
1741 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_2               7
1742 #define  STM_TIM234_CCMR1_OC2M_MASK                     7
1743 #define STM_TIM234_CCMR1_OC2PE  11
1744 #define STM_TIM234_CCMR1_OC2FE  10
1745 #define STM_TIM234_CCMR1_CC2S   8
1746 #define  STM_TIM234_CCMR1_CC2S_OUTPUT                   0
1747 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI2                1
1748 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI1                2
1749 #define  STM_TIM234_CCMR1_CC2S_INPUT_TRC                3
1750 #define  STM_TIM234_CCMR1_CC2S_MASK                     3
1751
1752 #define STM_TIM234_CCMR1_OC1CE  7
1753 #define STM_TIM234_CCMR1_OC1M   4
1754 #define  STM_TIM234_CCMR1_OC1M_FROZEN                   0
1755 #define  STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH        1
1756 #define  STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH         2
1757 #define  STM_TIM234_CCMR1_OC1M_TOGGLE                   3
1758 #define  STM_TIM234_CCMR1_OC1M_FORCE_LOW                4
1759 #define  STM_TIM234_CCMR1_OC1M_FORCE_HIGH               5
1760 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_1               6
1761 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_2               7
1762 #define  STM_TIM234_CCMR1_OC1M_MASK                     7
1763 #define STM_TIM234_CCMR1_OC1PE  11
1764 #define STM_TIM234_CCMR1_OC1FE  2
1765 #define STM_TIM234_CCMR1_CC1S   0
1766 #define  STM_TIM234_CCMR1_CC1S_OUTPUT                   0
1767 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI1                1
1768 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI2                2
1769 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC                3
1770 #define  STM_TIM234_CCMR1_CC1S_MASK                     3
1771
1772 #define STM_TIM234_CCMR2_OC4CE  15
1773 #define STM_TIM234_CCMR2_OC4M   12
1774 #define  STM_TIM234_CCMR2_OC4M_FROZEN                   0
1775 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
1776 #define  STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH         2
1777 #define  STM_TIM234_CCMR2_OC4M_TOGGLE                   3
1778 #define  STM_TIM234_CCMR2_OC4M_FORCE_LOW                4
1779 #define  STM_TIM234_CCMR2_OC4M_FORCE_HIGH               5
1780 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_1               6
1781 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_2               7
1782 #define  STM_TIM234_CCMR2_OC4M_MASK                     7
1783 #define STM_TIM234_CCMR2_OC4PE  11
1784 #define STM_TIM234_CCMR2_OC4FE  10
1785 #define STM_TIM234_CCMR2_CC4S   8
1786 #define  STM_TIM234_CCMR2_CC4S_OUTPUT                   0
1787 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI4                1
1788 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI3                2
1789 #define  STM_TIM234_CCMR2_CC4S_INPUT_TRC                3
1790 #define  STM_TIM234_CCMR2_CC4S_MASK                     3
1791
1792 #define STM_TIM234_CCMR2_OC3CE  7
1793 #define STM_TIM234_CCMR2_OC3M   4
1794 #define  STM_TIM234_CCMR2_OC3M_FROZEN                   0
1795 #define  STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH        1
1796 #define  STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH         2
1797 #define  STM_TIM234_CCMR2_OC3M_TOGGLE                   3
1798 #define  STM_TIM234_CCMR2_OC3M_FORCE_LOW                4
1799 #define  STM_TIM234_CCMR2_OC3M_FORCE_HIGH               5
1800 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_1               6
1801 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_2               7
1802 #define  STM_TIM234_CCMR2_OC3M_MASK                     7
1803 #define STM_TIM234_CCMR2_OC3PE  11
1804 #define STM_TIM234_CCMR2_OC3FE  2
1805 #define STM_TIM234_CCMR2_CC3S   0
1806 #define  STM_TIM234_CCMR2_CC3S_OUTPUT                   0
1807 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI3                1
1808 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI4                2
1809 #define  STM_TIM234_CCMR2_CC3S_INPUT_TRC                3
1810 #define  STM_TIM234_CCMR2_CC3S_MASK                     3
1811
1812 #define STM_TIM234_CCER_CC4NP   15
1813 #define STM_TIM234_CCER_CC4P    13
1814 #define STM_TIM234_CCER_CC4E    12
1815 #define STM_TIM234_CCER_CC3NP   11
1816 #define STM_TIM234_CCER_CC3P    9
1817 #define STM_TIM234_CCER_CC3E    8
1818 #define STM_TIM234_CCER_CC2NP   7
1819 #define STM_TIM234_CCER_CC2P    5
1820 #define STM_TIM234_CCER_CC2E    4
1821 #define STM_TIM234_CCER_CC1NP   3
1822 #define STM_TIM234_CCER_CC1P    1
1823 #define STM_TIM234_CCER_CC1E    0
1824
1825 struct stm_usb {
1826         vuint32_t       epr[8];
1827         uint8_t         reserved_20[0x40 - 0x20];
1828         vuint32_t       cntr;
1829         vuint32_t       istr;
1830         vuint32_t       fnr;
1831         vuint32_t       daddr;
1832         vuint32_t       btable;
1833 };
1834
1835 #define STM_USB_EPR_CTR_RX      15
1836 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1837 #define STM_USB_EPR_DTOG_RX     14
1838 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1839 #define STM_USB_EPR_STAT_RX     12
1840 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1841 #define  STM_USB_EPR_STAT_RX_STALL                      1
1842 #define  STM_USB_EPR_STAT_RX_NAK                        2
1843 #define  STM_USB_EPR_STAT_RX_VALID                      3
1844 #define  STM_USB_EPR_STAT_RX_MASK                       3
1845 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1846 #define STM_USB_EPR_SETUP       11
1847 #define STM_USB_EPR_EP_TYPE     9
1848 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1849 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1850 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1851 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1852 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1853 #define STM_USB_EPR_EP_KIND     8
1854 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1855 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1856 #define STM_USB_EPR_CTR_TX      7
1857 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1858 #define STM_USB_EPR_DTOG_TX     6
1859 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1860 #define STM_USB_EPR_STAT_TX     4
1861 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1862 #define  STM_USB_EPR_STAT_TX_STALL                      1
1863 #define  STM_USB_EPR_STAT_TX_NAK                        2
1864 #define  STM_USB_EPR_STAT_TX_VALID                      3
1865 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1866 #define  STM_USB_EPR_STAT_TX_MASK                       3
1867 #define STM_USB_EPR_EA          0
1868 #define  STM_USB_EPR_EA_MASK                            0xf
1869
1870 #define STM_USB_CNTR_CTRM       15
1871 #define STM_USB_CNTR_PMAOVRM    14
1872 #define STM_USB_CNTR_ERRM       13
1873 #define STM_USB_CNTR_WKUPM      12
1874 #define STM_USB_CNTR_SUSPM      11
1875 #define STM_USB_CNTR_RESETM     10
1876 #define STM_USB_CNTR_SOFM       9
1877 #define STM_USB_CNTR_ESOFM      8
1878 #define STM_USB_CNTR_RESUME     4
1879 #define STM_USB_CNTR_FSUSP      3
1880 #define STM_USB_CNTR_LP_MODE    2
1881 #define STM_USB_CNTR_PDWN       1
1882 #define STM_USB_CNTR_FRES       0
1883
1884 #define STM_USB_ISTR_CTR        15
1885 #define STM_USB_ISTR_PMAOVR     14
1886 #define STM_USB_ISTR_ERR        13
1887 #define STM_USB_ISTR_WKUP       12
1888 #define STM_USB_ISTR_SUSP       11
1889 #define STM_USB_ISTR_RESET      10
1890 #define STM_USB_ISTR_SOF        9
1891 #define STM_USB_ISTR_ESOF       8
1892 #define STM_USB_ISTR_DIR        4
1893 #define STM_USB_ISTR_EP_ID      0
1894 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1895
1896 #define STM_USB_FNR_RXDP        15
1897 #define STM_USB_FNR_RXDM        14
1898 #define STM_USB_FNR_LCK         13
1899 #define STM_USB_FNR_LSOF        11
1900 #define  STM_USB_FNR_LSOF_MASK                  0x3
1901 #define STM_USB_FNR_FN          0
1902 #define  STM_USB_FNR_FN_MASK                    0x7ff
1903
1904 #define STM_USB_DADDR_EF        7
1905 #define STM_USB_DADDR_ADD       0
1906 #define  STM_USB_DADDR_ADD_MASK                 0x7f
1907
1908 extern struct stm_usb stm_usb;
1909
1910 union stm_usb_bdt {
1911         struct {
1912                 vuint32_t       addr_tx;
1913                 vuint32_t       count_tx;
1914                 vuint32_t       addr_rx;
1915                 vuint32_t       count_rx;
1916         } single;
1917         struct {
1918                 vuint32_t       addr;
1919                 vuint32_t       count;
1920         } double_tx[2];
1921         struct {
1922                 vuint32_t       addr;
1923                 vuint32_t       count;
1924         } double_rx[2];
1925 };
1926
1927 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
1928 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
1929 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
1930 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
1931 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
1932
1933 #define STM_USB_BDT_SIZE        8
1934
1935 extern uint8_t stm_usb_sram[];
1936
1937 struct stm_exti {
1938         vuint32_t       imr;
1939         vuint32_t       emr;
1940         vuint32_t       rtsr;
1941         vuint32_t       ftsr;
1942
1943         vuint32_t       swier;
1944         vuint32_t       pr;
1945 };
1946
1947 extern struct stm_exti stm_exti;
1948
1949 #endif /* _STM32L_H_ */