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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #ifndef _STM32L_H_
  19 #define _STM32L_H_
  20
  21 #include <stdint.h>
  22
  23 typedef volatile uint32_t       vuint32_t;
  24 typedef volatile void *         vvoid_t;
  25
  26 struct stm_gpio {
  27         vuint32_t       moder;
  28         vuint32_t       otyper;
  29         vuint32_t       ospeedr;
  30         vuint32_t       pupdr;
  31
  32         vuint32_t       idr;
  33         vuint32_t       odr;
  34         vuint32_t       bsrr;
  35         vuint32_t       lckr;
  36
  37         vuint32_t       afrl;
  38         vuint32_t       afrh;
  39 };
  40
  41 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  42 #define STM_MODER_MASK                  3
  43 #define STM_MODER_INPUT                 0
  44 #define STM_MODER_OUTPUT                1
  45 #define STM_MODER_ALTERNATE             2
  46 #define STM_MODER_ANALOG                3
  47
  48 static inline void
  49 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  50         gpio->moder = ((gpio->moder &
  51                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  52                        value << STM_MODER_SHIFT(pin));
  53 }
  54
  55 static inline uint32_t
  56 stm_moder_get(struct stm_gpio *gpio, int pin) {
  57         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  58 }
  59
  60 #define STM_OTYPER_SHIFT(pin)           (pin)
  61 #define STM_OTYPER_MASK                 1
  62 #define STM_OTYPER_PUSH_PULL            0
  63 #define STM_OTYPER_OPEN_DRAIN           1
  64
  65 static inline void
  66 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  67         gpio->otyper = ((gpio->otyper &
  68                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  69                         value << STM_OTYPER_SHIFT(pin));
  70 }
  71
  72 static inline uint32_t
  73 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  74         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  75 }
  76
  77 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  78 #define STM_OSPEEDR_MASK                3
  79 #define STM_OSPEEDR_400kHz              0
  80 #define STM_OSPEEDR_2MHz                1
  81 #define STM_OSPEEDR_10MHz               2
  82 #define STM_OSPEEDR_40MHz               3
  83
  84 static inline void
  85 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  86         gpio->ospeedr = ((gpio->ospeedr &
  87                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  88                        value << STM_OSPEEDR_SHIFT(pin));
  89 }
  90
  91 static inline uint32_t
  92 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  93         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  94 }
  95
  96 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
  97 #define STM_PUPDR_MASK                  3
  98 #define STM_PUPDR_NONE                  0
  99 #define STM_PUPDR_PULL_UP               1
 100 #define STM_PUPDR_PULL_DOWN             2
 101 #define STM_PUPDR_RESERVED              3
 102
 103 static inline void
 104 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 105         gpio->pupdr = ((gpio->pupdr &
 106                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 107                        value << STM_PUPDR_SHIFT(pin));
 108 }
 109
 110 static inline uint32_t
 111 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 112         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 113 }
 114
 115 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 116 #define STM_AFR_MASK                    0xf
 117 #define STM_AFR_NONE                    0
 118 #define STM_AFR_AF0                     0x0
 119 #define STM_AFR_AF1                     0x1
 120 #define STM_AFR_AF2                     0x2
 121 #define STM_AFR_AF3                     0x3
 122 #define STM_AFR_AF4                     0x4
 123 #define STM_AFR_AF5                     0x5
 124 #define STM_AFR_AF6                     0x6
 125 #define STM_AFR_AF7                     0x7
 126 #define STM_AFR_AF8                     0x8
 127 #define STM_AFR_AF9                     0x9
 128 #define STM_AFR_AF10                    0xa
 129 #define STM_AFR_AF11                    0xb
 130 #define STM_AFR_AF12                    0xc
 131 #define STM_AFR_AF13                    0xd
 132 #define STM_AFR_AF14                    0xe
 133 #define STM_AFR_AF15                    0xf
 134
 135 static inline void
 136 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 137         /*
 138          * Set alternate pin mode too
 139          */
 140         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 141         if (pin < 8)
 142                 gpio->afrl = ((gpio->afrl &
 143                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 144                               value << STM_AFR_SHIFT(pin));
 145         else {
 146                 pin -= 8;
 147                 gpio->afrh = ((gpio->afrh &
 148                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 149                               value << STM_AFR_SHIFT(pin));
 150         }
 151 }
 152
 153 static inline uint32_t
 154 stm_afr_get(struct stm_gpio *gpio, int pin) {
 155         if (pin < 8)
 156                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 157         else {
 158                 pin -= 8;
 159                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 160         }
 161 }
 162
 163 static inline void
 164 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 165         /* Use the bit set/reset register to do this atomically */
 166         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 167 }
 168
 169 static inline void
 170 stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) {
 171         gpio->bsrr = bits;
 172 }
 173
 174 static inline void
 175 stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) {
 176         gpio->bsrr = ((uint32_t) bits) << 16;
 177 }
 178
 179 static inline uint8_t
 180 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 181         return (gpio->idr >> pin) & 1;
 182 }
 183
 184 static inline uint16_t
 185 stm_gpio_get_all(struct stm_gpio *gpio) {
 186         return gpio->idr;
 187 }
 188
 189 /*
 190  * We can't define these in registers.ld or our fancy
 191  * ao_enable_gpio macro will expand into a huge pile of code
 192  * as the compiler won't do correct constant folding and
 193  * dead-code elimination
 194
 195  extern struct stm_gpio stm_gpioa;
 196  extern struct stm_gpio stm_gpiob;
 197  extern struct stm_gpio stm_gpioc;
 198  extern struct stm_gpio stm_gpiod;
 199  extern struct stm_gpio stm_gpioe;
 200  extern struct stm_gpio stm_gpioh;
 201
 202 */
 203
 204 #define stm_gpioh  (*((struct stm_gpio *) 0x40021400))
 205 #define stm_gpioe  (*((struct stm_gpio *) 0x40021000))
 206 #define stm_gpiod  (*((struct stm_gpio *) 0x40020c00))
 207 #define stm_gpioc  (*((struct stm_gpio *) 0x40020800))
 208 #define stm_gpiob  (*((struct stm_gpio *) 0x40020400))
 209 #define stm_gpioa  (*((struct stm_gpio *) 0x40020000))
 210
 211 struct stm_usart {
 212         vuint32_t       sr;     /* status register */
 213         vuint32_t       dr;     /* data register */
 214         vuint32_t       brr;    /* baud rate register */
 215         vuint32_t       cr1;    /* control register 1 */
 216
 217         vuint32_t       cr2;    /* control register 2 */
 218         vuint32_t       cr3;    /* control register 3 */
 219         vuint32_t       gtpr;   /* guard time and prescaler */
 220 };
 221
 222 extern struct stm_usart stm_usart1;
 223 extern struct stm_usart stm_usart2;
 224 extern struct stm_usart stm_usart3;
 225
 226 #define STM_USART_SR_CTS        (9)     /* CTS flag */
 227 #define STM_USART_SR_LBD        (8)     /* LIN break detection flag */
 228 #define STM_USART_SR_TXE        (7)     /* Transmit data register empty */
 229 #define STM_USART_SR_TC         (6)     /* Transmission complete */
 230 #define STM_USART_SR_RXNE       (5)     /* Read data register not empty */
 231 #define STM_USART_SR_IDLE       (4)     /* IDLE line detected */
 232 #define STM_USART_SR_ORE        (3)     /* Overrun error */
 233 #define STM_USART_SR_NF         (2)     /* Noise detected flag */
 234 #define STM_USART_SR_FE         (1)     /* Framing error */
 235 #define STM_USART_SR_PE         (0)     /* Parity error */
 236
 237 #define STM_USART_CR1_OVER8     (15)    /* Oversampling mode */
 238 #define STM_USART_CR1_UE        (13)    /* USART enable */
 239 #define STM_USART_CR1_M         (12)    /* Word length */
 240 #define STM_USART_CR1_WAKE      (11)    /* Wakeup method */
 241 #define STM_USART_CR1_PCE       (10)    /* Parity control enable */
 242 #define STM_USART_CR1_PS        (9)     /* Parity selection */
 243 #define STM_USART_CR1_PEIE      (8)     /* PE interrupt enable */
 244 #define STM_USART_CR1_TXEIE     (7)     /* TXE interrupt enable */
 245 #define STM_USART_CR1_TCIE      (6)     /* Transmission complete interrupt enable */
 246 #define STM_USART_CR1_RXNEIE    (5)     /* RXNE interrupt enable */
 247 #define STM_USART_CR1_IDLEIE    (4)     /* IDLE interrupt enable */
 248 #define STM_USART_CR1_TE        (3)     /* Transmitter enable */
 249 #define STM_USART_CR1_RE        (2)     /* Receiver enable */
 250 #define STM_USART_CR1_RWU       (1)     /* Receiver wakeup */
 251 #define STM_USART_CR1_SBK       (0)     /* Send break */
 252
 253 #define STM_USART_CR2_LINEN     (14)    /* LIN mode enable */
 254 #define STM_USART_CR2_STOP      (12)    /* STOP bits */
 255 #define STM_USART_CR2_STOP_MASK 3
 256 #define STM_USART_CR2_STOP_1    0
 257 #define STM_USART_CR2_STOP_0_5  1
 258 #define STM_USART_CR2_STOP_2    2
 259 #define STM_USART_CR2_STOP_1_5  3
 260
 261 #define STM_USART_CR2_CLKEN     (11)    /* Clock enable */
 262 #define STM_USART_CR2_CPOL      (10)    /* Clock polarity */
 263 #define STM_USART_CR2_CPHA      (9)     /* Clock phase */
 264 #define STM_USART_CR2_LBCL      (8)     /* Last bit clock pulse */
 265 #define STM_USART_CR2_LBDIE     (6)     /* LIN break detection interrupt enable */
 266 #define STM_USART_CR2_LBDL      (5)     /* lin break detection length */
 267 #define STM_USART_CR2_ADD       (0)
 268 #define STM_USART_CR2_ADD_MASK  0xf
 269
 270 #define STM_USART_CR3_ONEBITE   (11)    /* One sample bit method enable */
 271 #define STM_USART_CR3_CTSIE     (10)    /* CTS interrupt enable */
 272 #define STM_USART_CR3_CTSE      (9)     /* CTS enable */
 273 #define STM_USART_CR3_RTSE      (8)     /* RTS enable */
 274 #define STM_USART_CR3_DMAT      (7)     /* DMA enable transmitter */
 275 #define STM_USART_CR3_DMAR      (6)     /* DMA enable receiver */
 276 #define STM_USART_CR3_SCEN      (5)     /* Smartcard mode enable */
 277 #define STM_USART_CR3_NACK      (4)     /* Smartcard NACK enable */
 278 #define STM_USART_CR3_HDSEL     (3)     /* Half-duplex selection */
 279 #define STM_USART_CR3_IRLP      (2)     /* IrDA low-power */
 280 #define STM_USART_CR3_IREN      (1)     /* IrDA mode enable */
 281 #define STM_USART_CR3_EIE       (0)     /* Error interrupt enable */
 282
 283 struct stm_tim {
 284 };
 285
 286 extern struct stm_tim stm_tim9;
 287
 288 struct stm_tim1011 {
 289         vuint32_t       cr1;
 290         uint32_t        unused_4;
 291         vuint32_t       smcr;
 292         vuint32_t       dier;
 293         vuint32_t       sr;
 294         vuint32_t       egr;
 295         vuint32_t       ccmr1;
 296         uint32_t        unused_1c;
 297         vuint32_t       ccer;
 298         vuint32_t       cnt;
 299         vuint32_t       psc;
 300         vuint32_t       arr;
 301         uint32_t        unused_30;
 302         vuint32_t       ccr1;
 303         uint32_t        unused_38;
 304         uint32_t        unused_3c;
 305         uint32_t        unused_40;
 306         uint32_t        unused_44;
 307         uint32_t        unused_48;
 308         uint32_t        unused_4c;
 309         vuint32_t       or;
 310 };
 311
 312 extern struct stm_tim1011 stm_tim10;
 313 extern struct stm_tim1011 stm_tim11;
 314
 315 #define STM_TIM1011_CR1_CKD     8
 316 #define  STM_TIM1011_CR1_CKD_1          0
 317 #define  STM_TIM1011_CR1_CKD_2          1
 318 #define  STM_TIM1011_CR1_CKD_4          2
 319 #define  STM_TIM1011_CR1_CKD_MASK       3
 320 #define STM_TIM1011_CR1_ARPE    7
 321 #define STM_TIM1011_CR1_URS     2
 322 #define STM_TIM1011_CR1_UDIS    1
 323 #define STM_TIM1011_CR1_CEN     0
 324
 325 #define STM_TIM1011_SMCR_ETP    15
 326 #define STM_TIM1011_SMCR_ECE    14
 327 #define STM_TIM1011_SMCR_ETPS   12
 328 #define  STM_TIM1011_SMCR_ETPS_OFF      0
 329 #define  STM_TIM1011_SMCR_ETPS_2        1
 330 #define  STM_TIM1011_SMCR_ETPS_4        2
 331 #define  STM_TIM1011_SMCR_ETPS_8        3
 332 #define  STM_TIM1011_SMCR_ETPS_MASK     3
 333 #define STM_TIM1011_SMCR_ETF    8
 334 #define  STM_TIM1011_SMCR_ETF_NONE              0
 335 #define  STM_TIM1011_SMCR_ETF_CK_INT_2          1
 336 #define  STM_TIM1011_SMCR_ETF_CK_INT_4          2
 337 #define  STM_TIM1011_SMCR_ETF_CK_INT_8          3
 338 #define  STM_TIM1011_SMCR_ETF_DTS_2_6           4
 339 #define  STM_TIM1011_SMCR_ETF_DTS_2_8           5
 340 #define  STM_TIM1011_SMCR_ETF_DTS_4_6           6
 341 #define  STM_TIM1011_SMCR_ETF_DTS_4_8           7
 342 #define  STM_TIM1011_SMCR_ETF_DTS_8_6           8
 343 #define  STM_TIM1011_SMCR_ETF_DTS_8_8           9
 344 #define  STM_TIM1011_SMCR_ETF_DTS_16_5          10
 345 #define  STM_TIM1011_SMCR_ETF_DTS_16_6          11
 346 #define  STM_TIM1011_SMCR_ETF_DTS_16_8          12
 347 #define  STM_TIM1011_SMCR_ETF_DTS_32_5          13
 348 #define  STM_TIM1011_SMCR_ETF_DTS_32_6          14
 349 #define  STM_TIM1011_SMCR_ETF_DTS_32_8          15
 350 #define  STM_TIM1011_SMCR_ETF_MASK              15
 351
 352 #define STM_TIM1011_DIER_CC1E   1
 353 #define STM_TIM1011_DIER_UIE    0
 354
 355 #define STM_TIM1011_SR_CC1OF    9
 356 #define STM_TIM1011_SR_CC1IF    1
 357 #define STM_TIM1011_SR_UIF      0
 358
 359 #define STM_TIM1011_EGR_CC1G    1
 360 #define STM_TIM1011_EGR_UG      0
 361
 362 #define STM_TIM1011_CCMR1_OC1CE 7
 363 #define STM_TIM1011_CCMR1_OC1M  4
 364 #define  STM_TIM1011_CCMR1_OC1M_FROZEN                  0
 365 #define  STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH   1
 366 #define  STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
 367 #define  STM_TIM1011_CCMR1_OC1M_TOGGLE                  3
 368 #define  STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE          4
 369 #define  STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE            5
 370 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_1              6
 371 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_2              7
 372 #define  STM_TIM1011_CCMR1_OC1M_MASK                    7
 373 #define STM_TIM1011_CCMR1_OC1PE 3
 374 #define STM_TIM1011_CCMR1_OC1FE 2
 375 #define STM_TIM1011_CCMR1_CC1S  0
 376 #define  STM_TIM1011_CCMR1_CC1S_OUTPUT                  0
 377 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI1               1
 378 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI2               2
 379 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TRC               3
 380 #define  STM_TIM1011_CCMR1_CC1S_MASK                    3
 381
 382 #define  STM_TIM1011_CCMR1_IC1F_NONE            0
 383 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_2        1
 384 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_4        2
 385 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_8        3
 386 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_6         4
 387 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_8         5
 388 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_6         6
 389 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_8         7
 390 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_6         8
 391 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_8         9
 392 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_5        10
 393 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_6        11
 394 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_8        12
 395 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_5        13
 396 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_6        14
 397 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_8        15
 398 #define  STM_TIM1011_CCMR1_IC1F_MASK            15
 399 #define STM_TIM1011_CCMR1_IC1PSC        2
 400 #define  STM_TIM1011_CCMR1_IC1PSC_1             0
 401 #define  STM_TIM1011_CCMR1_IC1PSC_2             1
 402 #define  STM_TIM1011_CCMR1_IC1PSC_4             2
 403 #define  STM_TIM1011_CCMR1_IC1PSC_8             3
 404 #define  STM_TIM1011_CCMR1_IC1PSC_MASK          3
 405 #define STM_TIM1011_CCMR1_CC1S          0
 406
 407 #define STM_TIM1011_CCER_CC1NP          3
 408 #define STM_TIM1011_CCER_CC1P           1
 409 #define STM_TIM1011_CCER_CC1E           0
 410
 411 #define STM_TIM1011_OR_TI1_RMP_RI       3
 412 #define STM_TIM1011_ETR_RMP             2
 413 #define STM_TIM1011_TI1_RMP             0
 414 #define  STM_TIM1011_TI1_RMP_GPIO               0
 415 #define  STM_TIM1011_TI1_RMP_LSI                1
 416 #define  STM_TIM1011_TI1_RMP_LSE                2
 417 #define  STM_TIM1011_TI1_RMP_RTC                3
 418 #define  STM_TIM1011_TI1_RMP_MASK               3
 419
 420 /* Flash interface */
 421
 422 struct stm_flash {
 423         vuint32_t       acr;
 424         vuint32_t       pecr;
 425         vuint32_t       pdkeyr;
 426         vuint32_t       pekeyr;
 427
 428         vuint32_t       prgkeyr;
 429         vuint32_t       optkeyr;
 430         vuint32_t       sr;
 431         vuint32_t       obr;
 432
 433         vuint32_t       wrpr;
 434 };
 435
 436 extern struct stm_flash stm_flash;
 437
 438 #define STM_FLASH_ACR_RUN_PD    (4)
 439 #define STM_FLASH_ACR_SLEEP_PD  (3)
 440 #define STM_FLASH_ACR_ACC64     (2)
 441 #define STM_FLASH_ACR_PRFEN     (1)
 442 #define STM_FLASH_ACR_LATENCY   (0)
 443
 444 #define STM_FLASH_PECR_OBL_LAUNCH       18
 445 #define STM_FLASH_PECR_ERRIE            17
 446 #define STM_FLASH_PECR_EOPIE            16
 447 #define STM_FLASH_PECR_FPRG             10
 448 #define STM_FLASH_PECR_ERASE            9
 449 #define STM_FLASH_PECR_FTDW             8
 450 #define STM_FLASH_PECR_DATA             4
 451 #define STM_FLASH_PECR_PROG             3
 452 #define STM_FLASH_PECR_OPTLOCK          2
 453 #define STM_FLASH_PECR_PRGLOCK          1
 454 #define STM_FLASH_PECR_PELOCK           0
 455
 456 #define STM_FLASH_SR_OPTVERR            11
 457 #define STM_FLASH_SR_SIZERR             10
 458 #define STM_FLASH_SR_PGAERR             9
 459 #define STM_FLASH_SR_WRPERR             8
 460 #define STM_FLASH_SR_READY              3
 461 #define STM_FLASH_SR_ENDHV              2
 462 #define STM_FLASH_SR_EOP                1
 463 #define STM_FLASH_SR_BSY                0
 464
 465 #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
 466 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
 467
 468 #define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
 469 #define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
 470
 471 struct stm_rcc {
 472         vuint32_t       cr;
 473         vuint32_t       icscr;
 474         vuint32_t       cfgr;
 475         vuint32_t       cir;
 476
 477         vuint32_t       ahbrstr;
 478         vuint32_t       apb2rstr;
 479         vuint32_t       apb1rstr;
 480         vuint32_t       ahbenr;
 481
 482         vuint32_t       apb2enr;
 483         vuint32_t       apb1enr;
 484         vuint32_t       ahblenr;
 485         vuint32_t       apb2lpenr;
 486
 487         vuint32_t       apb1lpenr;
 488         vuint32_t       csr;
 489 };
 490
 491 extern struct stm_rcc stm_rcc;
 492
 493 /* Nominal high speed internal oscillator frequency is 16MHz */
 494 #define STM_HSI_FREQ            16000000
 495
 496 #define STM_RCC_CR_RTCPRE       (29)
 497 #define  STM_RCC_CR_RTCPRE_HSE_DIV_2    0
 498 #define  STM_RCC_CR_RTCPRE_HSE_DIV_4    1
 499 #define  STM_RCC_CR_RTCPRE_HSE_DIV_8    2
 500 #define  STM_RCC_CR_RTCPRE_HSE_DIV_16   3
 501 #define  STM_RCC_CR_RTCPRE_HSE_MASK     3
 502
 503 #define STM_RCC_CR_CSSON        (28)
 504 #define STM_RCC_CR_PLLRDY       (25)
 505 #define STM_RCC_CR_PLLON        (24)
 506 #define STM_RCC_CR_HSEBYP       (18)
 507 #define STM_RCC_CR_HSERDY       (17)
 508 #define STM_RCC_CR_HSEON        (16)
 509 #define STM_RCC_CR_MSIRDY       (9)
 510 #define STM_RCC_CR_MSION        (8)
 511 #define STM_RCC_CR_HSIRDY       (1)
 512 #define STM_RCC_CR_HSION        (0)
 513
 514 #define STM_RCC_CFGR_MCOPRE     (28)
 515 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 516 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 517 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 518 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 519 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 520 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7
 521
 522 #define STM_RCC_CFGR_MCOSEL     (24)
 523 #define  STM_RCC_CFGR_MCOSEL_DISABLE    0
 524 #define  STM_RCC_CFGR_MCOSEL_SYSCLK     1
 525 #define  STM_RCC_CFGR_MCOSEL_HSI        2
 526 #define  STM_RCC_CFGR_MCOSEL_MSI        3
 527 #define  STM_RCC_CFGR_MCOSEL_HSE        4
 528 #define  STM_RCC_CFGR_MCOSEL_PLL        5
 529 #define  STM_RCC_CFGR_MCOSEL_LSI        6
 530 #define  STM_RCC_CFGR_MCOSEL_LSE        7
 531 #define  STM_RCC_CFGR_MCOSEL_MASK       7
 532
 533 #define STM_RCC_CFGR_PLLDIV     (22)
 534 #define  STM_RCC_CFGR_PLLDIV_2          1
 535 #define  STM_RCC_CFGR_PLLDIV_3          2
 536 #define  STM_RCC_CFGR_PLLDIV_4          3
 537 #define  STM_RCC_CFGR_PLLDIV_MASK       3
 538
 539 #define STM_RCC_CFGR_PLLMUL     (18)
 540 #define  STM_RCC_CFGR_PLLMUL_3          0
 541 #define  STM_RCC_CFGR_PLLMUL_4          1
 542 #define  STM_RCC_CFGR_PLLMUL_6          2
 543 #define  STM_RCC_CFGR_PLLMUL_8          3
 544 #define  STM_RCC_CFGR_PLLMUL_12         4
 545 #define  STM_RCC_CFGR_PLLMUL_16         5
 546 #define  STM_RCC_CFGR_PLLMUL_24         6
 547 #define  STM_RCC_CFGR_PLLMUL_32         7
 548 #define  STM_RCC_CFGR_PLLMUL_48         8
 549 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 550
 551 #define STM_RCC_CFGR_PLLSRC     (16)
 552
 553 #define STM_RCC_CFGR_PPRE2      (11)
 554 #define  STM_RCC_CFGR_PPRE2_DIV_1       0
 555 #define  STM_RCC_CFGR_PPRE2_DIV_2       4
 556 #define  STM_RCC_CFGR_PPRE2_DIV_4       5
 557 #define  STM_RCC_CFGR_PPRE2_DIV_8       6
 558 #define  STM_RCC_CFGR_PPRE2_DIV_16      7
 559 #define  STM_RCC_CFGR_PPRE2_MASK        7
 560
 561 #define STM_RCC_CFGR_PPRE1      (8)
 562 #define  STM_RCC_CFGR_PPRE1_DIV_1       0
 563 #define  STM_RCC_CFGR_PPRE1_DIV_2       4
 564 #define  STM_RCC_CFGR_PPRE1_DIV_4       5
 565 #define  STM_RCC_CFGR_PPRE1_DIV_8       6
 566 #define  STM_RCC_CFGR_PPRE1_DIV_16      7
 567 #define  STM_RCC_CFGR_PPRE1_MASK        7
 568
 569 #define STM_RCC_CFGR_HPRE       (4)
 570 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 571 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 572 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 573 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 574 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 575 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 576 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 577 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 578 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 579 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 580
 581 #define STM_RCC_CFGR_SWS        (2)
 582 #define  STM_RCC_CFGR_SWS_MSI           0
 583 #define  STM_RCC_CFGR_SWS_HSI           1
 584 #define  STM_RCC_CFGR_SWS_HSE           2
 585 #define  STM_RCC_CFGR_SWS_PLL           3
 586 #define  STM_RCC_CFGR_SWS_MASK          3
 587
 588 #define STM_RCC_CFGR_SW         (0)
 589 #define  STM_RCC_CFGR_SW_MSI            0
 590 #define  STM_RCC_CFGR_SW_HSI            1
 591 #define  STM_RCC_CFGR_SW_HSE            2
 592 #define  STM_RCC_CFGR_SW_PLL            3
 593 #define  STM_RCC_CFGR_SW_MASK           3
 594
 595 #define STM_RCC_AHBENR_DMA1EN           (24)
 596 #define STM_RCC_AHBENR_FLITFEN          (15)
 597 #define STM_RCC_AHBENR_CRCEN            (12)
 598 #define STM_RCC_AHBENR_GPIOHEN          (5)
 599 #define STM_RCC_AHBENR_GPIOEEN          (4)
 600 #define STM_RCC_AHBENR_GPIODEN          (3)
 601 #define STM_RCC_AHBENR_GPIOCEN          (2)
 602 #define STM_RCC_AHBENR_GPIOBEN          (1)
 603 #define STM_RCC_AHBENR_GPIOAEN          (0)
 604
 605 #define STM_RCC_APB2ENR_USART1EN        (14)
 606 #define STM_RCC_APB2ENR_SPI1EN          (12)
 607 #define STM_RCC_APB2ENR_ADC1EN          (9)
 608 #define STM_RCC_APB2ENR_TIM11EN         (4)
 609 #define STM_RCC_APB2ENR_TIM10EN         (3)
 610 #define STM_RCC_APB2ENR_TIM9EN          (2)
 611 #define STM_RCC_APB2ENR_SYSCFGEN        (0)
 612
 613 #define STM_RCC_APB1ENR_COMPEN          (31)
 614 #define STM_RCC_APB1ENR_DACEN           (29)
 615 #define STM_RCC_APB1ENR_PWREN           (28)
 616 #define STM_RCC_APB1ENR_USBEN           (23)
 617 #define STM_RCC_APB1ENR_I2C2EN          (22)
 618 #define STM_RCC_APB1ENR_I2C1EN          (21)
 619 #define STM_RCC_APB1ENR_USART3EN        (18)
 620 #define STM_RCC_APB1ENR_USART2EN        (17)
 621 #define STM_RCC_APB1ENR_SPI2EN          (14)
 622 #define STM_RCC_APB1ENR_WWDGEN          (11)
 623 #define STM_RCC_APB1ENR_LCDEN           (9)
 624 #define STM_RCC_APB1ENR_TIM7EN          (5)
 625 #define STM_RCC_APB1ENR_TIM6EN          (4)
 626 #define STM_RCC_APB1ENR_TIM4EN          (2)
 627 #define STM_RCC_APB1ENR_TIM3EN          (1)
 628 #define STM_RCC_APB1ENR_TIM2EN          (0)
 629
 630 #define STM_RCC_CSR_LPWRRSTF            (31)
 631 #define STM_RCC_CSR_WWDGRSTF            (30)
 632 #define STM_RCC_CSR_IWDGRSTF            (29)
 633 #define STM_RCC_CSR_SFTRSTF             (28)
 634 #define STM_RCC_CSR_PORRSTF             (27)
 635 #define STM_RCC_CSR_PINRSTF             (26)
 636 #define STM_RCC_CSR_OBLRSTF             (25)
 637 #define STM_RCC_CSR_RMVF                (24)
 638 #define STM_RCC_CSR_RTFRST              (23)
 639 #define STM_RCC_CSR_RTCEN               (22)
 640 #define STM_RCC_CSR_RTCSEL              (16)
 641
 642 #define  STM_RCC_CSR_RTCSEL_NONE                0
 643 #define  STM_RCC_CSR_RTCSEL_LSE                 1
 644 #define  STM_RCC_CSR_RTCSEL_LSI                 2
 645 #define  STM_RCC_CSR_RTCSEL_HSE                 3
 646 #define  STM_RCC_CSR_RTCSEL_MASK                3
 647
 648 #define STM_RCC_CSR_LSEBYP              (10)
 649 #define STM_RCC_CSR_LSERDY              (9)
 650 #define STM_RCC_CSR_LSEON               (8)
 651 #define STM_RCC_CSR_LSIRDY              (1)
 652 #define STM_RCC_CSR_LSION               (0)
 653
 654 struct stm_pwr {
 655         vuint32_t       cr;
 656         vuint32_t       csr;
 657 };
 658
 659 extern struct stm_pwr stm_pwr;
 660
 661 #define STM_PWR_CR_LPRUN        (14)
 662
 663 #define STM_PWR_CR_VOS          (11)
 664 #define  STM_PWR_CR_VOS_1_8             1
 665 #define  STM_PWR_CR_VOS_1_5             2
 666 #define  STM_PWR_CR_VOS_1_2             3
 667 #define  STM_PWR_CR_VOS_MASK            3
 668
 669 #define STM_PWR_CR_FWU          (10)
 670 #define STM_PWR_CR_ULP          (9)
 671 #define STM_PWR_CR_DBP          (8)
 672
 673 #define STM_PWR_CR_PLS          (5)
 674 #define  STM_PWR_CR_PLS_1_9     0
 675 #define  STM_PWR_CR_PLS_2_1     1
 676 #define  STM_PWR_CR_PLS_2_3     2
 677 #define  STM_PWR_CR_PLS_2_5     3
 678 #define  STM_PWR_CR_PLS_2_7     4
 679 #define  STM_PWR_CR_PLS_2_9     5
 680 #define  STM_PWR_CR_PLS_3_1     6
 681 #define  STM_PWR_CR_PLS_EXT     7
 682 #define  STM_PWR_CR_PLS_MASK    7
 683
 684 #define STM_PWR_CR_PVDE         (4)
 685 #define STM_PWR_CR_CSBF         (3)
 686 #define STM_PWR_CR_CWUF         (2)
 687 #define STM_PWR_CR_PDDS         (1)
 688 #define STM_PWR_CR_LPSDSR       (0)
 689
 690 #define STM_PWR_CSR_EWUP3       (10)
 691 #define STM_PWR_CSR_EWUP2       (9)
 692 #define STM_PWR_CSR_EWUP1       (8)
 693 #define STM_PWR_CSR_REGLPF      (5)
 694 #define STM_PWR_CSR_VOSF        (4)
 695 #define STM_PWR_CSR_VREFINTRDYF (3)
 696 #define STM_PWR_CSR_PVDO        (2)
 697 #define STM_PWR_CSR_SBF         (1)
 698 #define STM_PWR_CSR_WUF         (0)
 699
 700 struct stm_tim67 {
 701         vuint32_t       cr1;
 702         vuint32_t       cr2;
 703         uint32_t        _unused_08;
 704         vuint32_t       dier;
 705
 706         vuint32_t       sr;
 707         vuint32_t       egr;
 708         uint32_t        _unused_18;
 709         uint32_t        _unused_1c;
 710
 711         uint32_t        _unused_20;
 712         vuint32_t       cnt;
 713         vuint32_t       psc;
 714         vuint32_t       arr;
 715 };
 716
 717 extern struct stm_tim67 stm_tim6;
 718
 719 #define STM_TIM67_CR1_ARPE      (7)
 720 #define STM_TIM67_CR1_OPM       (3)
 721 #define STM_TIM67_CR1_URS       (2)
 722 #define STM_TIM67_CR1_UDIS      (1)
 723 #define STM_TIM67_CR1_CEN       (0)
 724
 725 #define STM_TIM67_CR2_MMS       (4)
 726 #define  STM_TIM67_CR2_MMS_RESET        0
 727 #define  STM_TIM67_CR2_MMS_ENABLE       1
 728 #define  STM_TIM67_CR2_MMS_UPDATE       2
 729 #define  STM_TIM67_CR2_MMS_MASK         7
 730
 731 #define STM_TIM67_DIER_UDE      (8)
 732 #define STM_TIM67_DIER_UIE      (0)
 733
 734 #define STM_TIM67_SR_UIF        (0)
 735
 736 #define STM_TIM67_EGR_UG        (0)
 737
 738 struct stm_lcd {
 739         vuint32_t       cr;
 740         vuint32_t       fcr;
 741         vuint32_t       sr;
 742         vuint32_t       clr;
 743         uint32_t        unused_0x10;
 744         vuint32_t       ram[8*2];
 745 };
 746
 747 extern struct stm_lcd stm_lcd;
 748
 749 #define STM_LCD_CR_MUX_SEG              (7)
 750
 751 #define STM_LCD_CR_BIAS                 (5)
 752 #define  STM_LCD_CR_BIAS_1_4            0
 753 #define  STM_LCD_CR_BIAS_1_2            1
 754 #define  STM_LCD_CR_BIAS_1_3            2
 755 #define  STM_LCD_CR_BIAS_MASK           3
 756
 757 #define STM_LCD_CR_DUTY                 (2)
 758 #define  STM_LCD_CR_DUTY_STATIC         0
 759 #define  STM_LCD_CR_DUTY_1_2            1
 760 #define  STM_LCD_CR_DUTY_1_3            2
 761 #define  STM_LCD_CR_DUTY_1_4            3
 762 #define  STM_LCD_CR_DUTY_1_8            4
 763 #define  STM_LCD_CR_DUTY_MASK           7
 764
 765 #define STM_LCD_CR_VSEL                 (1)
 766 #define STM_LCD_CR_LCDEN                (0)
 767
 768 #define STM_LCD_FCR_PS                  (22)
 769 #define  STM_LCD_FCR_PS_1               0x0
 770 #define  STM_LCD_FCR_PS_2               0x1
 771 #define  STM_LCD_FCR_PS_4               0x2
 772 #define  STM_LCD_FCR_PS_8               0x3
 773 #define  STM_LCD_FCR_PS_16              0x4
 774 #define  STM_LCD_FCR_PS_32              0x5
 775 #define  STM_LCD_FCR_PS_64              0x6
 776 #define  STM_LCD_FCR_PS_128             0x7
 777 #define  STM_LCD_FCR_PS_256             0x8
 778 #define  STM_LCD_FCR_PS_512             0x9
 779 #define  STM_LCD_FCR_PS_1024            0xa
 780 #define  STM_LCD_FCR_PS_2048            0xb
 781 #define  STM_LCD_FCR_PS_4096            0xc
 782 #define  STM_LCD_FCR_PS_8192            0xd
 783 #define  STM_LCD_FCR_PS_16384           0xe
 784 #define  STM_LCD_FCR_PS_32768           0xf
 785 #define  STM_LCD_FCR_PS_MASK            0xf
 786
 787 #define STM_LCD_FCR_DIV                 (18)
 788 #define STM_LCD_FCR_DIV_16              0x0
 789 #define STM_LCD_FCR_DIV_17              0x1
 790 #define STM_LCD_FCR_DIV_18              0x2
 791 #define STM_LCD_FCR_DIV_19              0x3
 792 #define STM_LCD_FCR_DIV_20              0x4
 793 #define STM_LCD_FCR_DIV_21              0x5
 794 #define STM_LCD_FCR_DIV_22              0x6
 795 #define STM_LCD_FCR_DIV_23              0x7
 796 #define STM_LCD_FCR_DIV_24              0x8
 797 #define STM_LCD_FCR_DIV_25              0x9
 798 #define STM_LCD_FCR_DIV_26              0xa
 799 #define STM_LCD_FCR_DIV_27              0xb
 800 #define STM_LCD_FCR_DIV_28              0xc
 801 #define STM_LCD_FCR_DIV_29              0xd
 802 #define STM_LCD_FCR_DIV_30              0xe
 803 #define STM_LCD_FCR_DIV_31              0xf
 804 #define STM_LCD_FCR_DIV_MASK            0xf
 805
 806 #define STM_LCD_FCR_BLINK               (16)
 807 #define  STM_LCD_FCR_BLINK_DISABLE              0
 808 #define  STM_LCD_FCR_BLINK_SEG0_COM0            1
 809 #define  STM_LCD_FCR_BLINK_SEG0_COMALL          2
 810 #define  STM_LCD_FCR_BLINK_SEGALL_COMALL        3
 811 #define  STM_LCD_FCR_BLINK_MASK                 3
 812
 813 #define STM_LCD_FCR_BLINKF              (13)
 814 #define  STM_LCD_FCR_BLINKF_8                   0
 815 #define  STM_LCD_FCR_BLINKF_16                  1
 816 #define  STM_LCD_FCR_BLINKF_32                  2
 817 #define  STM_LCD_FCR_BLINKF_64                  3
 818 #define  STM_LCD_FCR_BLINKF_128                 4
 819 #define  STM_LCD_FCR_BLINKF_256                 5
 820 #define  STM_LCD_FCR_BLINKF_512                 6
 821 #define  STM_LCD_FCR_BLINKF_1024                7
 822 #define  STM_LCD_FCR_BLINKF_MASK                7
 823
 824 #define STM_LCD_FCR_CC                  (10)
 825 #define  STM_LCD_FCR_CC_MASK                    7
 826
 827 #define STM_LCD_FCR_DEAD                (7)
 828 #define  STM_LCD_FCR_DEAD_MASK                  7
 829
 830 #define STM_LCD_FCR_PON                 (4)
 831 #define  STM_LCD_FCR_PON_MASK                   7
 832
 833 #define STM_LCD_FCR_UDDIE               (3)
 834 #define STM_LCD_FCR_SOFIE               (1)
 835 #define STM_LCD_FCR_HD                  (0)
 836
 837 #define STM_LCD_SR_FCRSF                (5)
 838 #define STM_LCD_SR_RDY                  (4)
 839 #define STM_LCD_SR_UDD                  (3)
 840 #define STM_LCD_SR_UDR                  (2)
 841 #define STM_LCD_SR_SOF                  (1)
 842 #define STM_LCD_SR_ENS                  (0)
 843
 844 #define STM_LCD_CLR_UDDC                (3)
 845 #define STM_LCD_CLR_SOFC                (1)
 846
 847 /* The SYSTICK starts at 0xe000e010 */
 848
 849 struct stm_systick {
 850         vuint32_t       csr;
 851         vuint32_t       rvr;
 852         vuint32_t       cvr;
 853         vuint32_t       calib;
 854 };
 855
 856 extern struct stm_systick stm_systick;
 857
 858 #define STM_SYSTICK_CSR_ENABLE          0
 859 #define STM_SYSTICK_CSR_TICKINT         1
 860 #define STM_SYSTICK_CSR_CLKSOURCE       2
 861 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               0
 862 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK                 1
 863 #define STM_SYSTICK_CSR_COUNTFLAG       16
 864
 865 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 866
 867 struct stm_nvic {
 868         vuint32_t       iser[8];        /* 0x000 0xe000e100 Set Enable Register */
 869
 870         uint8_t         _unused020[0x080 - 0x020];
 871
 872         vuint32_t       icer[8];        /* 0x080 0xe000e180 Clear Enable Register */
 873
 874         uint8_t         _unused0a0[0x100 - 0x0a0];
 875
 876         vuint32_t       ispr[8];        /* 0x100 0xe000e200 Set Pending Register */
 877
 878         uint8_t         _unused120[0x180 - 0x120];
 879
 880         vuint32_t       icpr[8];        /* 0x180 0xe000e280 Clear Pending Register */
 881
 882         uint8_t         _unused1a0[0x200 - 0x1a0];
 883
 884         vuint32_t       iabr[8];        /* 0x200 0xe000e300 Active Bit Register */
 885
 886         uint8_t         _unused220[0x300 - 0x220];
 887
 888         vuint32_t       ipr[60];        /* 0x300 0xe000e400 Priority Register */
 889
 890         uint8_t         _unused3f0[0xc00 - 0x3f0];
 891
 892         vuint32_t       cpuid_base;     /* 0xc00 0xe000ed00 CPUID Base Register */
 893         vuint32_t       ics;            /* 0xc04 0xe000ed04 Interrupt Control State Register */
 894         vuint32_t       vto;            /* 0xc08 0xe000ed08 Vector Table Offset Register */
 895         vuint32_t       ai_rc;          /* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */
 896         vuint32_t       sc;             /* 0xc10 0xe000ed10 System Control Register */
 897         vuint32_t       cc;             /* 0xc14 0xe000ed14 Configuration Control Register */
 898
 899         uint8_t         _unusedc18[0xe00 - 0xc18];
 900
 901         vuint32_t       stir;           /* 0xe00 */
 902 };
 903
 904 extern struct stm_nvic stm_nvic;
 905
 906 #define IRQ_REG(irq)    ((irq) >> 5)
 907 #define IRQ_BIT(irq)    ((irq) & 0x1f)
 908 #define IRQ_MASK(irq)   (1 << IRQ_BIT(irq))
 909 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
 910
 911 static inline void
 912 stm_nvic_set_enable(int irq) {
 913         stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
 914 }
 915
 916 static inline void
 917 stm_nvic_clear_enable(int irq) {
 918         stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
 919 }
 920
 921 static inline int
 922 stm_nvic_enabled(int irq) {
 923         return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
 924 }
 925
 926 static inline void
 927 stm_nvic_set_pending(int irq) {
 928         stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
 929 }
 930
 931 static inline void
 932 stm_nvic_clear_pending(int irq) {
 933         stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
 934 }
 935
 936 static inline int
 937 stm_nvic_pending(int irq) {
 938         return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
 939 }
 940
 941 static inline int
 942 stm_nvic_active(int irq) {
 943         return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
 944 }
 945
 946 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 947 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 948 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 949
 950 static inline void
 951 stm_nvic_set_priority(int irq, uint8_t prio) {
 952         int             n = IRQ_PRIO_REG(irq);
 953         uint32_t        v;
 954
 955         v = stm_nvic.ipr[n];
 956         v &= ~IRQ_PRIO_MASK(irq);
 957         v |= (prio) << IRQ_PRIO_BIT(irq);
 958         stm_nvic.ipr[n] = v;
 959 }
 960
 961 static inline uint8_t
 962 stm_nvic_get_priority(int irq) {
 963         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 964 }
 965
 966 struct stm_scb {
 967         vuint32_t       cpuid;
 968         vuint32_t       icsr;
 969         vuint32_t       vtor;
 970         vuint32_t       aircr;
 971
 972         vuint32_t       scr;
 973         vuint32_t       ccr;
 974         vuint32_t       shpr1;
 975         vuint32_t       shpr2;
 976
 977         vuint32_t       shpr3;
 978         vuint32_t       shcrs;
 979         vuint32_t       cfsr;
 980         vuint32_t       hfsr;
 981
 982         uint32_t        unused_30;
 983         vuint32_t       mmfar;
 984         vuint32_t       bfar;
 985 };
 986
 987 extern struct stm_scb stm_scb;
 988
 989 #define STM_SCB_AIRCR_VECTKEY           16
 990 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
 991 #define STM_SCB_AIRCR_PRIGROUP          8
 992 #define STM_SCB_AIRCR_SYSRESETREQ       2
 993 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
 994 #define STM_SCB_AIRCR_VECTRESET         0
 995
 996 struct stm_mpu {
 997         vuint32_t       typer;
 998         vuint32_t       cr;
 999         vuint32_t       rnr;
1000         vuint32_t       rbar;
1001
1002         vuint32_t       rasr;
1003         vuint32_t       rbar_a1;
1004         vuint32_t       rasr_a1;
1005         vuint32_t       rbar_a2;
1006         vuint32_t       rasr_a2;
1007         vuint32_t       rbar_a3;
1008         vuint32_t       rasr_a3;
1009 };
1010
1011 extern struct stm_mpu stm_mpu;
1012
1013 #define STM_MPU_TYPER_IREGION   16
1014 #define  STM_MPU_TYPER_IREGION_MASK     0xff
1015 #define STM_MPU_TYPER_DREGION   8
1016 #define  STM_MPU_TYPER_DREGION_MASK     0xff
1017 #define STM_MPU_TYPER_SEPARATE  0
1018
1019 #define STM_MPU_CR_PRIVDEFENA   2
1020 #define STM_MPU_CR_HFNMIENA     1
1021 #define STM_MPU_CR_ENABLE       0
1022
1023 #define STM_MPU_RNR_REGION      0
1024 #define STM_MPU_RNR_REGION_MASK         0xff
1025
1026 #define STM_MPU_RBAR_ADDR       5
1027 #define STM_MPU_RBAR_ADDR_MASK          0x7ffffff
1028
1029 #define STM_MPU_RBAR_VALID      4
1030 #define STM_MPU_RBAR_REGION     0
1031 #define STM_MPU_RBAR_REGION_MASK        0xf
1032
1033 #define STM_MPU_RASR_XN         28
1034 #define STM_MPU_RASR_AP         24
1035 #define  STM_MPU_RASR_AP_NONE_NONE      0
1036 #define  STM_MPU_RASR_AP_RW_NONE        1
1037 #define  STM_MPU_RASR_AP_RW_RO          2
1038 #define  STM_MPU_RASR_AP_RW_RW          3
1039 #define  STM_MPU_RASR_AP_RO_NONE        5
1040 #define  STM_MPU_RASR_AP_RO_RO          6
1041 #define  STM_MPU_RASR_AP_MASK           7
1042 #define STM_MPU_RASR_TEX        19
1043 #define  STM_MPU_RASR_TEX_MASK          7
1044 #define STM_MPU_RASR_S          18
1045 #define STM_MPU_RASR_C          17
1046 #define STM_MPU_RASR_B          16
1047 #define STM_MPU_RASR_SRD        8
1048 #define  STM_MPU_RASR_SRD_MASK          0xff
1049 #define STM_MPU_RASR_SIZE       1
1050 #define  STM_MPU_RASR_SIZE_MASK         0x1f
1051 #define STM_MPU_RASR_ENABLE     0
1052
1053 #define isr(name) void stm_ ## name ## _isr(void);
1054
1055 isr(nmi)
1056 isr(hardfault)
1057 isr(memmanage)
1058 isr(busfault)
1059 isr(usagefault)
1060 isr(svc)
1061 isr(debugmon)
1062 isr(pendsv)
1063 isr(systick)
1064 isr(wwdg)
1065 isr(pvd)
1066 isr(tamper_stamp)
1067 isr(rtc_wkup)
1068 isr(flash)
1069 isr(rcc)
1070 isr(exti0)
1071 isr(exti1)
1072 isr(exti2)
1073 isr(exti3)
1074 isr(exti4)
1075 isr(dma1_channel1)
1076 isr(dma1_channel2)
1077 isr(dma1_channel3)
1078 isr(dma1_channel4)
1079 isr(dma1_channel5)
1080 isr(dma1_channel6)
1081 isr(dma1_channel7)
1082 isr(adc1)
1083 isr(usb_hp)
1084 isr(usb_lp)
1085 isr(dac)
1086 isr(comp)
1087 isr(exti9_5)
1088 isr(lcd)
1089 isr(tim9)
1090 isr(tim10)
1091 isr(tim11)
1092 isr(tim2)
1093 isr(tim3)
1094 isr(tim4)
1095 isr(i2c1_ev)
1096 isr(i2c1_er)
1097 isr(i2c2_ev)
1098 isr(i2c2_er)
1099 isr(spi1)
1100 isr(spi2)
1101 isr(usart1)
1102 isr(usart2)
1103 isr(usart3)
1104 isr(exti15_10)
1105 isr(rtc_alarm)
1106 isr(usb_fs_wkup)
1107 isr(tim6)
1108 isr(tim7)
1109
1110 #undef isr
1111
1112 #define STM_ISR_WWDG_POS                0
1113 #define STM_ISR_PVD_POS                 1
1114 #define STM_ISR_TAMPER_STAMP_POS        2
1115 #define STM_ISR_RTC_WKUP_POS            3
1116 #define STM_ISR_FLASH_POS               4
1117 #define STM_ISR_RCC_POS                 5
1118 #define STM_ISR_EXTI0_POS               6
1119 #define STM_ISR_EXTI1_POS               7
1120 #define STM_ISR_EXTI2_POS               8
1121 #define STM_ISR_EXTI3_POS               9
1122 #define STM_ISR_EXTI4_POS               10
1123 #define STM_ISR_DMA1_CHANNEL1_POS       11
1124 #define STM_ISR_DMA2_CHANNEL1_POS       12
1125 #define STM_ISR_DMA3_CHANNEL1_POS       13
1126 #define STM_ISR_DMA4_CHANNEL1_POS       14
1127 #define STM_ISR_DMA5_CHANNEL1_POS       15
1128 #define STM_ISR_DMA6_CHANNEL1_POS       16
1129 #define STM_ISR_DMA7_CHANNEL1_POS       17
1130 #define STM_ISR_ADC1_POS                18
1131 #define STM_ISR_USB_HP_POS              19
1132 #define STM_ISR_USB_LP_POS              20
1133 #define STM_ISR_DAC_POS                 21
1134 #define STM_ISR_COMP_POS                22
1135 #define STM_ISR_EXTI9_5_POS             23
1136 #define STM_ISR_LCD_POS                 24
1137 #define STM_ISR_TIM9_POS                25
1138 #define STM_ISR_TIM10_POS               26
1139 #define STM_ISR_TIM11_POS               27
1140 #define STM_ISR_TIM2_POS                28
1141 #define STM_ISR_TIM3_POS                29
1142 #define STM_ISR_TIM4_POS                30
1143 #define STM_ISR_I2C1_EV_POS             31
1144 #define STM_ISR_I2C1_ER_POS             32
1145 #define STM_ISR_I2C2_EV_POS             33
1146 #define STM_ISR_I2C2_ER_POS             34
1147 #define STM_ISR_SPI1_POS                35
1148 #define STM_ISR_SPI2_POS                36
1149 #define STM_ISR_USART1_POS              37
1150 #define STM_ISR_USART2_POS              38
1151 #define STM_ISR_USART3_POS              39
1152 #define STM_ISR_EXTI15_10_POS           40
1153 #define STM_ISR_RTC_ALARM_POS           41
1154 #define STM_ISR_USB_FS_WKUP_POS         42
1155 #define STM_ISR_TIM6_POS                43
1156 #define STM_ISR_TIM7_POS                44
1157
1158 struct stm_syscfg {
1159         vuint32_t       memrmp;
1160         vuint32_t       pmc;
1161         vuint32_t       exticr[4];
1162 };
1163
1164 extern struct stm_syscfg stm_syscfg;
1165
1166 #define STM_SYSCFG_MEMRMP_MEM_MODE      0
1167 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH          0
1168 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH        1
1169 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SRAM                3
1170 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MASK                3
1171
1172 #define STM_SYSCFG_PMC_USB_PU           0
1173
1174 #define STM_SYSCFG_EXTICR_PA            0
1175 #define STM_SYSCFG_EXTICR_PB            1
1176 #define STM_SYSCFG_EXTICR_PC            2
1177 #define STM_SYSCFG_EXTICR_PD            3
1178 #define STM_SYSCFG_EXTICR_PE            4
1179 #define STM_SYSCFG_EXTICR_PH            5
1180
1181 static inline void
1182 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1183         uint8_t reg = pin >> 2;
1184         uint8_t shift = (pin & 3) << 2;
1185         uint8_t val = 0;
1186
1187         /* Enable SYSCFG */
1188         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
1189
1190         if (gpio == &stm_gpioa)
1191                 val = STM_SYSCFG_EXTICR_PA;
1192         else if (gpio == &stm_gpiob)
1193                 val = STM_SYSCFG_EXTICR_PB;
1194         else if (gpio == &stm_gpioc)
1195                 val = STM_SYSCFG_EXTICR_PC;
1196         else if (gpio == &stm_gpiod)
1197                 val = STM_SYSCFG_EXTICR_PD;
1198         else if (gpio == &stm_gpioe)
1199                 val = STM_SYSCFG_EXTICR_PE;
1200
1201         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
1202 }
1203
1204
1205 struct stm_dma_channel {
1206         vuint32_t       ccr;
1207         vuint32_t       cndtr;
1208         vvoid_t         cpar;
1209         vvoid_t         cmar;
1210         vuint32_t       reserved;
1211 };
1212
1213 #define STM_NUM_DMA     7
1214
1215 struct stm_dma {
1216         vuint32_t               isr;
1217         vuint32_t               ifcr;
1218         struct stm_dma_channel  channel[STM_NUM_DMA];
1219 };
1220
1221 extern struct stm_dma stm_dma;
1222
1223 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
1224  */
1225
1226 #define STM_DMA_INDEX(channel)          ((channel) - 1)
1227
1228 #define STM_DMA_ISR(index)              ((index) << 2)
1229 #define STM_DMA_ISR_MASK                        0xf
1230 #define STM_DMA_ISR_TEIF                        3
1231 #define STM_DMA_ISR_HTIF                        2
1232 #define STM_DMA_ISR_TCIF                        1
1233 #define STM_DMA_ISR_GIF                         0
1234
1235 #define STM_DMA_IFCR(index)             ((index) << 2)
1236 #define STM_DMA_IFCR_MASK                       0xf
1237 #define STM_DMA_IFCR_CTEIF                      3
1238 #define STM_DMA_IFCR_CHTIF                      2
1239 #define STM_DMA_IFCR_CTCIF                      1
1240 #define STM_DMA_IFCR_CGIF                       0
1241
1242 #define STM_DMA_CCR_MEM2MEM             (14)
1243
1244 #define STM_DMA_CCR_PL                  (12)
1245 #define  STM_DMA_CCR_PL_LOW                     (0)
1246 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
1247 #define  STM_DMA_CCR_PL_HIGH                    (2)
1248 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
1249 #define  STM_DMA_CCR_PL_MASK                    (3)
1250
1251 #define STM_DMA_CCR_MSIZE               (10)
1252 #define  STM_DMA_CCR_MSIZE_8                    (0)
1253 #define  STM_DMA_CCR_MSIZE_16                   (1)
1254 #define  STM_DMA_CCR_MSIZE_32                   (2)
1255 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
1256
1257 #define STM_DMA_CCR_PSIZE               (8)
1258 #define  STM_DMA_CCR_PSIZE_8                    (0)
1259 #define  STM_DMA_CCR_PSIZE_16                   (1)
1260 #define  STM_DMA_CCR_PSIZE_32                   (2)
1261 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
1262
1263 #define STM_DMA_CCR_MINC                (7)
1264 #define STM_DMA_CCR_PINC                (6)
1265 #define STM_DMA_CCR_CIRC                (5)
1266 #define STM_DMA_CCR_DIR                 (4)
1267 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
1268 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
1269 #define STM_DMA_CCR_TEIE                (3)
1270 #define STM_DMA_CCR_HTIE                (2)
1271 #define STM_DMA_CCR_TCIE                (1)
1272 #define STM_DMA_CCR_EN                  (0)
1273
1274 #define STM_DMA_CHANNEL_ADC1            1
1275 #define STM_DMA_CHANNEL_SPI1_RX         2
1276 #define STM_DMA_CHANNEL_SPI1_TX         3
1277 #define STM_DMA_CHANNEL_SPI2_RX         4
1278 #define STM_DMA_CHANNEL_SPI2_TX         5
1279 #define STM_DMA_CHANNEL_USART3_TX       2
1280 #define STM_DMA_CHANNEL_USART3_RX       3
1281 #define STM_DMA_CHANNEL_USART1_TX       4
1282 #define STM_DMA_CHANNEL_USART1_RX       5
1283 #define STM_DMA_CHANNEL_USART2_RX       6
1284 #define STM_DMA_CHANNEL_USART2_TX       7
1285 #define STM_DMA_CHANNEL_I2C2_TX         4
1286 #define STM_DMA_CHANNEL_I2C2_RX         5
1287 #define STM_DMA_CHANNEL_I2C1_TX         6
1288 #define STM_DMA_CHANNEL_I2C1_RX         7
1289 #define STM_DMA_CHANNEL_TIM2_CH3        1
1290 #define STM_DMA_CHANNEL_TIM2_UP         2
1291 #define STM_DMA_CHANNEL_TIM2_CH1        5
1292 #define STM_DMA_CHANNEL_TIM2_CH2        7
1293 #define STM_DMA_CHANNEL_TIM2_CH4        7
1294 #define STM_DMA_CHANNEL_TIM3_CH3        2
1295 #define STM_DMA_CHANNEL_TIM3_CH4        3
1296 #define STM_DMA_CHANNEL_TIM3_UP         3
1297 #define STM_DMA_CHANNEL_TIM3_CH1        6
1298 #define STM_DMA_CHANNEL_TIM3_TRIG       6
1299 #define STM_DMA_CHANNEL_TIM4_CH1        1
1300 #define STM_DMA_CHANNEL_TIM4_CH2        4
1301 #define STM_DMA_CHANNEL_TIM4_CH3        5
1302 #define STM_DMA_CHANNEL_TIM4_UP         7
1303 #define STM_DMA_CHANNEL_TIM6_UP_DA      2
1304 #define STM_DMA_CHANNEL_C_CHANNEL1      2
1305 #define STM_DMA_CHANNEL_TIM7_UP_DA      3
1306 #define STM_DMA_CHANNEL_C_CHANNEL2      3
1307
1308 /*
1309  * Only spi channel 1 and 2 can use DMA
1310  */
1311 #define STM_NUM_SPI     2
1312
1313 struct stm_spi {
1314         vuint32_t       cr1;
1315         vuint32_t       cr2;
1316         vuint32_t       sr;
1317         vuint32_t       dr;
1318         vuint32_t       crcpr;
1319         vuint32_t       rxcrcr;
1320         vuint32_t       txcrcr;
1321 };
1322
1323 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1324
1325 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1326  */
1327
1328 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1329
1330 #define STM_SPI_CR1_BIDIMODE            15
1331 #define STM_SPI_CR1_BIDIOE              14
1332 #define STM_SPI_CR1_CRCEN               13
1333 #define STM_SPI_CR1_CRCNEXT             12
1334 #define STM_SPI_CR1_DFF                 11
1335 #define STM_SPI_CR1_RXONLY              10
1336 #define STM_SPI_CR1_SSM                 9
1337 #define STM_SPI_CR1_SSI                 8
1338 #define STM_SPI_CR1_LSBFIRST            7
1339 #define STM_SPI_CR1_SPE                 6
1340 #define STM_SPI_CR1_BR                  3
1341 #define  STM_SPI_CR1_BR_PCLK_2                  0
1342 #define  STM_SPI_CR1_BR_PCLK_4                  1
1343 #define  STM_SPI_CR1_BR_PCLK_8                  2
1344 #define  STM_SPI_CR1_BR_PCLK_16                 3
1345 #define  STM_SPI_CR1_BR_PCLK_32                 4
1346 #define  STM_SPI_CR1_BR_PCLK_64                 5
1347 #define  STM_SPI_CR1_BR_PCLK_128                6
1348 #define  STM_SPI_CR1_BR_PCLK_256                7
1349 #define  STM_SPI_CR1_BR_MASK                    7
1350
1351 #define STM_SPI_CR1_MSTR                2
1352 #define STM_SPI_CR1_CPOL                1
1353 #define STM_SPI_CR1_CPHA                0
1354
1355 #define STM_SPI_CR2_TXEIE       7
1356 #define STM_SPI_CR2_RXNEIE      6
1357 #define STM_SPI_CR2_ERRIE       5
1358 #define STM_SPI_CR2_SSOE        2
1359 #define STM_SPI_CR2_TXDMAEN     1
1360 #define STM_SPI_CR2_RXDMAEN     0
1361
1362 #define STM_SPI_SR_FRE          8
1363 #define STM_SPI_SR_BSY          7
1364 #define STM_SPI_SR_OVR          6
1365 #define STM_SPI_SR_MODF         5
1366 #define STM_SPI_SR_CRCERR       4
1367 #define STM_SPI_SR_UDR          3
1368 #define STM_SPI_SR_CHSIDE       2
1369 #define STM_SPI_SR_TXE          1
1370 #define STM_SPI_SR_RXNE         0
1371
1372 struct stm_adc {
1373         vuint32_t       sr;
1374         vuint32_t       cr1;
1375         vuint32_t       cr2;
1376         vuint32_t       smpr1;
1377         vuint32_t       smpr2;
1378         vuint32_t       smpr3;
1379         vuint32_t       jofr1;
1380         vuint32_t       jofr2;
1381         vuint32_t       jofr3;
1382         vuint32_t       jofr4;
1383         vuint32_t       htr;
1384         vuint32_t       ltr;
1385         vuint32_t       sqr1;
1386         vuint32_t       sqr2;
1387         vuint32_t       sqr3;
1388         vuint32_t       sqr4;
1389         vuint32_t       sqr5;
1390         vuint32_t       jsqr;
1391         vuint32_t       jdr1;
1392         vuint32_t       jdr2;
1393         vuint32_t       jdr3;
1394         vuint32_t       jdr4;
1395         vuint32_t       dr;
1396         uint8_t         reserved[0x300 - 0x5c];
1397         vuint32_t       csr;
1398         vuint32_t       ccr;
1399 };
1400
1401 extern struct stm_adc stm_adc;
1402
1403 #define STM_ADC_SR_JCNR         9
1404 #define STM_ADC_SR_RCNR         8
1405 #define STM_ADC_SR_ADONS        6
1406 #define STM_ADC_SR_OVR          5
1407 #define STM_ADC_SR_STRT         4
1408 #define STM_ADC_SR_JSTRT        3
1409 #define STM_ADC_SR_JEOC         2
1410 #define STM_ADC_SR_EOC          1
1411 #define STM_ADC_SR_AWD          0
1412
1413 #define STM_ADC_CR1_OVRIE       26
1414 #define STM_ADC_CR1_RES         24
1415 #define  STM_ADC_CR1_RES_12             0
1416 #define  STM_ADC_CR1_RES_10             1
1417 #define  STM_ADC_CR1_RES_8              2
1418 #define  STM_ADC_CR1_RES_6              3
1419 #define  STM_ADC_CR1_RES_MASK           3
1420 #define STM_ADC_CR1_AWDEN       23
1421 #define STM_ADC_CR1_JAWDEN      22
1422 #define STM_ADC_CR1_PDI         17
1423 #define STM_ADC_CR1_PDD         16
1424 #define STM_ADC_CR1_DISCNUM     13
1425 #define  STM_ADC_CR1_DISCNUM_1          0
1426 #define  STM_ADC_CR1_DISCNUM_2          1
1427 #define  STM_ADC_CR1_DISCNUM_3          2
1428 #define  STM_ADC_CR1_DISCNUM_4          3
1429 #define  STM_ADC_CR1_DISCNUM_5          4
1430 #define  STM_ADC_CR1_DISCNUM_6          5
1431 #define  STM_ADC_CR1_DISCNUM_7          6
1432 #define  STM_ADC_CR1_DISCNUM_8          7
1433 #define  STM_ADC_CR1_DISCNUM_MASK       7
1434 #define STM_ADC_CR1_JDISCEN     12
1435 #define STM_ADC_CR1_DISCEN      11
1436 #define STM_ADC_CR1_JAUTO       10
1437 #define STM_ADC_CR1_AWDSGL      9
1438 #define STM_ADC_CR1_SCAN        8
1439 #define STM_ADC_CR1_JEOCIE      7
1440 #define STM_ADC_CR1_AWDIE       6
1441 #define STM_ADC_CR1_EOCIE       5
1442 #define STM_ADC_CR1_AWDCH       0
1443 #define  STM_ADC_CR1_AWDCH_MASK         0x1f
1444
1445 #define STM_ADC_CR2_SWSTART     30
1446 #define STM_ADC_CR2_EXTEN       28
1447 #define  STM_ADC_CR2_EXTEN_DISABLE      0
1448 #define  STM_ADC_CR2_EXTEN_RISING       1
1449 #define  STM_ADC_CR2_EXTEN_FALLING      2
1450 #define  STM_ADC_CR2_EXTEN_BOTH         3
1451 #define  STM_ADC_CR2_EXTEN_MASK         3
1452 #define STM_ADC_CR2_EXTSEL      24
1453 #define  STM_ADC_CR2_EXTSEL_TIM9_CC2    0
1454 #define  STM_ADC_CR2_EXTSEL_TIM9_TRGO   1
1455 #define  STM_ADC_CR2_EXTSEL_TIM2_CC3    2
1456 #define  STM_ADC_CR2_EXTSEL_TIM2_CC2    3
1457 #define  STM_ADC_CR2_EXTSEL_TIM3_TRGO   4
1458 #define  STM_ADC_CR2_EXTSEL_TIM4_CC4    5
1459 #define  STM_ADC_CR2_EXTSEL_TIM2_TRGO   6
1460 #define  STM_ADC_CR2_EXTSEL_TIM3_CC1    7
1461 #define  STM_ADC_CR2_EXTSEL_TIM3_CC3    8
1462 #define  STM_ADC_CR2_EXTSEL_TIM4_TRGO   9
1463 #define  STM_ADC_CR2_EXTSEL_TIM6_TRGO   10
1464 #define  STM_ADC_CR2_EXTSEL_EXTI_11     15
1465 #define  STM_ADC_CR2_EXTSEL_MASK        15
1466 #define STM_ADC_CR2_JWSTART     22
1467 #define STM_ADC_CR2_JEXTEN      20
1468 #define  STM_ADC_CR2_JEXTEN_DISABLE     0
1469 #define  STM_ADC_CR2_JEXTEN_RISING      1
1470 #define  STM_ADC_CR2_JEXTEN_FALLING     2
1471 #define  STM_ADC_CR2_JEXTEN_BOTH        3
1472 #define  STM_ADC_CR2_JEXTEN_MASK        3
1473 #define STM_ADC_CR2_JEXTSEL     16
1474 #define  STM_ADC_CR2_JEXTSEL_TIM9_CC1   0
1475 #define  STM_ADC_CR2_JEXTSEL_TIM9_TRGO  1
1476 #define  STM_ADC_CR2_JEXTSEL_TIM2_TRGO  2
1477 #define  STM_ADC_CR2_JEXTSEL_TIM2_CC1   3
1478 #define  STM_ADC_CR2_JEXTSEL_TIM3_CC4   4
1479 #define  STM_ADC_CR2_JEXTSEL_TIM4_TRGO  5
1480 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC1   6
1481 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC2   7
1482 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC3   8
1483 #define  STM_ADC_CR2_JEXTSEL_TIM10_CC1  9
1484 #define  STM_ADC_CR2_JEXTSEL_TIM7_TRGO  10
1485 #define  STM_ADC_CR2_JEXTSEL_EXTI_15    15
1486 #define  STM_ADC_CR2_JEXTSEL_MASK       15
1487 #define STM_ADC_CR2_ALIGN       11
1488 #define STM_ADC_CR2_EOCS        10
1489 #define STM_ADC_CR2_DDS         9
1490 #define STM_ADC_CR2_DMA         8
1491 #define STM_ADC_CR2_DELS        4
1492 #define  STM_ADC_CR2_DELS_NONE          0
1493 #define  STM_ADC_CR2_DELS_UNTIL_READ    1
1494 #define  STM_ADC_CR2_DELS_7             2
1495 #define  STM_ADC_CR2_DELS_15            3
1496 #define  STM_ADC_CR2_DELS_31            4
1497 #define  STM_ADC_CR2_DELS_63            5
1498 #define  STM_ADC_CR2_DELS_127           6
1499 #define  STM_ADC_CR2_DELS_255           7
1500 #define  STM_ADC_CR2_DELS_MASK          7
1501 #define STM_ADC_CR2_CONT        1
1502 #define STM_ADC_CR2_ADON        0
1503
1504 #define STM_ADC_CCR_TSVREFE     23
1505 #define STM_ADC_CCR_ADCPRE      16
1506 #define  STM_ADC_CCR_ADCPRE_HSI_1       0
1507 #define  STM_ADC_CCR_ADCPRE_HSI_2       1
1508 #define  STM_ADC_CCR_ADCPRE_HSI_4       2
1509 #define  STM_ADC_CCR_ADCPRE_MASK        3
1510
1511 struct stm_temp_cal {
1512         uint16_t        vref;
1513         uint16_t        ts_cal_cold;
1514         uint16_t        reserved;
1515         uint16_t        ts_cal_hot;
1516 };
1517
1518 extern struct stm_temp_cal      stm_temp_cal;
1519
1520 #define stm_temp_cal_cold       25
1521 #define stm_temp_cal_hot        110
1522
1523 struct stm_dbg_mcu {
1524         uint32_t        idcode;
1525 };
1526
1527 extern struct stm_dbg_mcu       stm_dbg_mcu;
1528
1529 static inline uint16_t
1530 stm_dev_id(void) {
1531         return stm_dbg_mcu.idcode & 0xfff;
1532 }
1533
1534 struct stm_flash_size {
1535         uint16_t        f_size;
1536 };
1537
1538 extern struct stm_flash_size    stm_flash_size_medium;
1539 extern struct stm_flash_size    stm_flash_size_large;
1540
1541 /* Returns flash size in bytes */
1542 extern uint32_t
1543 stm_flash_size(void);
1544
1545 struct stm_device_id {
1546         uint32_t        u_id0;
1547         uint32_t        u_id1;
1548         uint32_t        u_id2;
1549 };
1550
1551 extern struct stm_device_id     stm_device_id;
1552
1553 #define STM_NUM_I2C     2
1554
1555 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1556
1557 struct stm_i2c {
1558         vuint32_t       cr1;
1559         vuint32_t       cr2;
1560         vuint32_t       oar1;
1561         vuint32_t       oar2;
1562         vuint32_t       dr;
1563         vuint32_t       sr1;
1564         vuint32_t       sr2;
1565         vuint32_t       ccr;
1566         vuint32_t       trise;
1567 };
1568
1569 extern struct stm_i2c stm_i2c1, stm_i2c2;
1570
1571 #define STM_I2C_CR1_SWRST       15
1572 #define STM_I2C_CR1_ALERT       13
1573 #define STM_I2C_CR1_PEC         12
1574 #define STM_I2C_CR1_POS         11
1575 #define STM_I2C_CR1_ACK         10
1576 #define STM_I2C_CR1_STOP        9
1577 #define STM_I2C_CR1_START       8
1578 #define STM_I2C_CR1_NOSTRETCH   7
1579 #define STM_I2C_CR1_ENGC        6
1580 #define STM_I2C_CR1_ENPEC       5
1581 #define STM_I2C_CR1_ENARP       4
1582 #define STM_I2C_CR1_SMBTYPE     3
1583 #define STM_I2C_CR1_SMBUS       1
1584 #define STM_I2C_CR1_PE          0
1585
1586 #define STM_I2C_CR2_LAST        12
1587 #define STM_I2C_CR2_DMAEN       11
1588 #define STM_I2C_CR2_ITBUFEN     10
1589 #define STM_I2C_CR2_ITEVTEN     9
1590 #define STM_I2C_CR2_ITERREN     8
1591 #define STM_I2C_CR2_FREQ        0
1592 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1593 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1594 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1595 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1596 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1597 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1598
1599 #define STM_I2C_SR1_SMBALERT    15
1600 #define STM_I2C_SR1_TIMEOUT     14
1601 #define STM_I2C_SR1_PECERR      12
1602 #define STM_I2C_SR1_OVR         11
1603 #define STM_I2C_SR1_AF          10
1604 #define STM_I2C_SR1_ARLO        9
1605 #define STM_I2C_SR1_BERR        8
1606 #define STM_I2C_SR1_TXE         7
1607 #define STM_I2C_SR1_RXNE        6
1608 #define STM_I2C_SR1_STOPF       4
1609 #define STM_I2C_SR1_ADD10       3
1610 #define STM_I2C_SR1_BTF         2
1611 #define STM_I2C_SR1_ADDR        1
1612 #define STM_I2C_SR1_SB          0
1613
1614 #define STM_I2C_SR2_PEC         8
1615 #define  STM_I2C_SR2_PEC_MASK   0xff00
1616 #define STM_I2C_SR2_DUALF       7
1617 #define STM_I2C_SR2_SMBHOST     6
1618 #define STM_I2C_SR2_SMBDEFAULT  5
1619 #define STM_I2C_SR2_GENCALL     4
1620 #define STM_I2C_SR2_TRA         2
1621 #define STM_I2C_SR2_BUSY        1
1622 #define STM_I2C_SR2_MSL         0
1623
1624 #define STM_I2C_CCR_FS          15
1625 #define STM_I2C_CCR_DUTY        14
1626 #define STM_I2C_CCR_CCR         0
1627 #define  STM_I2C_CCR_MASK       0x7ff
1628
1629 struct stm_tim234 {
1630         vuint32_t       cr1;
1631         vuint32_t       cr2;
1632         vuint32_t       smcr;
1633         vuint32_t       dier;
1634
1635         vuint32_t       sr;
1636         vuint32_t       egr;
1637         vuint32_t       ccmr1;
1638         vuint32_t       ccmr2;
1639
1640         vuint32_t       ccer;
1641         vuint32_t       cnt;
1642         vuint32_t       psc;
1643         vuint32_t       arr;
1644
1645         uint32_t        reserved_30;
1646         vuint32_t       ccr1;
1647         vuint32_t       ccr2;
1648         vuint32_t       ccr3;
1649
1650         vuint32_t       ccr4;
1651         uint32_t        reserved_44;
1652         vuint32_t       dcr;
1653         vuint32_t       dmar;
1654
1655         uint32_t        reserved_50;
1656 };
1657
1658 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1659
1660 #define STM_TIM234_CR1_CKD      8
1661 #define  STM_TIM234_CR1_CKD_1           0
1662 #define  STM_TIM234_CR1_CKD_2           1
1663 #define  STM_TIM234_CR1_CKD_4           2
1664 #define  STM_TIM234_CR1_CKD_MASK        3
1665 #define STM_TIM234_CR1_ARPE     7
1666 #define STM_TIM234_CR1_CMS      5
1667 #define  STM_TIM234_CR1_CMS_EDGE        0
1668 #define  STM_TIM234_CR1_CMS_CENTER_1    1
1669 #define  STM_TIM234_CR1_CMS_CENTER_2    2
1670 #define  STM_TIM234_CR1_CMS_CENTER_3    3
1671 #define  STM_TIM234_CR1_CMS_MASK        3
1672 #define STM_TIM234_CR1_DIR      4
1673 #define  STM_TIM234_CR1_DIR_UP          0
1674 #define  STM_TIM234_CR1_DIR_DOWN        1
1675 #define STM_TIM234_CR1_OPM      3
1676 #define STM_TIM234_CR1_URS      2
1677 #define STM_TIM234_CR1_UDIS     1
1678 #define STM_TIM234_CR1_CEN      0
1679
1680 #define STM_TIM234_CR2_TI1S     7
1681 #define STM_TIM234_CR2_MMS      4
1682 #define  STM_TIM234_CR2_MMS_RESET               0
1683 #define  STM_TIM234_CR2_MMS_ENABLE              1
1684 #define  STM_TIM234_CR2_MMS_UPDATE              2
1685 #define  STM_TIM234_CR2_MMS_COMPARE_PULSE       3
1686 #define  STM_TIM234_CR2_MMS_COMPARE_OC1REF      4
1687 #define  STM_TIM234_CR2_MMS_COMPARE_OC2REF      5
1688 #define  STM_TIM234_CR2_MMS_COMPARE_OC3REF      6
1689 #define  STM_TIM234_CR2_MMS_COMPARE_OC4REF      7
1690 #define  STM_TIM234_CR2_MMS_MASK                7
1691 #define STM_TIM234_CR2_CCDS     3
1692
1693 #define STM_TIM234_SMCR_ETP     15
1694 #define STM_TIM234_SMCR_ECE     14
1695 #define STM_TIM234_SMCR_ETPS    12
1696 #define  STM_TIM234_SMCR_ETPS_OFF               0
1697 #define  STM_TIM234_SMCR_ETPS_DIV_2             1
1698 #define  STM_TIM234_SMCR_ETPS_DIV_4             2
1699 #define  STM_TIM234_SMCR_ETPS_DIV_8             3
1700 #define  STM_TIM234_SMCR_ETPS_MASK              3
1701 #define STM_TIM234_SMCR_ETF     8
1702 #define  STM_TIM234_SMCR_ETF_NONE               0
1703 #define  STM_TIM234_SMCR_ETF_INT_N_2            1
1704 #define  STM_TIM234_SMCR_ETF_INT_N_4            2
1705 #define  STM_TIM234_SMCR_ETF_INT_N_8            3
1706 #define  STM_TIM234_SMCR_ETF_DTS_2_N_6          4
1707 #define  STM_TIM234_SMCR_ETF_DTS_2_N_8          5
1708 #define  STM_TIM234_SMCR_ETF_DTS_4_N_6          6
1709 #define  STM_TIM234_SMCR_ETF_DTS_4_N_8          7
1710 #define  STM_TIM234_SMCR_ETF_DTS_8_N_6          8
1711 #define  STM_TIM234_SMCR_ETF_DTS_8_N_8          9
1712 #define  STM_TIM234_SMCR_ETF_DTS_16_N_5         10
1713 #define  STM_TIM234_SMCR_ETF_DTS_16_N_6         11
1714 #define  STM_TIM234_SMCR_ETF_DTS_16_N_8         12
1715 #define  STM_TIM234_SMCR_ETF_DTS_32_N_5         13
1716 #define  STM_TIM234_SMCR_ETF_DTS_32_N_6         14
1717 #define  STM_TIM234_SMCR_ETF_DTS_32_N_8         15
1718 #define  STM_TIM234_SMCR_ETF_MASK               15
1719 #define STM_TIM234_SMCR_MSM     7
1720 #define STM_TIM234_SMCR_TS      4
1721 #define  STM_TIM234_SMCR_TS_ITR0                0
1722 #define  STM_TIM234_SMCR_TS_ITR1                1
1723 #define  STM_TIM234_SMCR_TS_ITR2                2
1724 #define  STM_TIM234_SMCR_TS_ITR3                3
1725 #define  STM_TIM234_SMCR_TS_TI1F_ED             4
1726 #define  STM_TIM234_SMCR_TS_TI1FP1              5
1727 #define  STM_TIM234_SMCR_TS_TI2FP2              6
1728 #define  STM_TIM234_SMCR_TS_ETRF                7
1729 #define  STM_TIM234_SMCR_TS_MASK                7
1730 #define STM_TIM234_SMCR_OCCS    3
1731 #define STM_TIM234_SMCR_SMS     0
1732 #define  STM_TIM234_SMCR_SMS_DISABLE            0
1733 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_1     1
1734 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_2     2
1735 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_3     3
1736 #define  STM_TIM234_SMCR_SMS_RESET_MODE         4
1737 #define  STM_TIM234_SMCR_SMS_GATED_MODE         5
1738 #define  STM_TIM234_SMCR_SMS_TRIGGER_MODE       6
1739 #define  STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK     7
1740 #define  STM_TIM234_SMCR_SMS_MASK               7
1741
1742 #define STM_TIM234_SR_CC4OF     12
1743 #define STM_TIM234_SR_CC3OF     11
1744 #define STM_TIM234_SR_CC2OF     10
1745 #define STM_TIM234_SR_CC1OF     9
1746 #define STM_TIM234_SR_TIF       6
1747 #define STM_TIM234_SR_CC4IF     4
1748 #define STM_TIM234_SR_CC3IF     3
1749 #define STM_TIM234_SR_CC2IF     2
1750 #define STM_TIM234_SR_CC1IF     1
1751 #define STM_TIM234_SR_UIF       0
1752
1753 #define STM_TIM234_EGR_TG       6
1754 #define STM_TIM234_EGR_CC4G     4
1755 #define STM_TIM234_EGR_CC3G     3
1756 #define STM_TIM234_EGR_CC2G     2
1757 #define STM_TIM234_EGR_CC1G     1
1758 #define STM_TIM234_EGR_UG       0
1759
1760 #define STM_TIM234_CCMR1_OC2CE  15
1761 #define STM_TIM234_CCMR1_OC2M   12
1762 #define  STM_TIM234_CCMR1_OC2M_FROZEN                   0
1763 #define  STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH        1
1764 #define  STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH         2
1765 #define  STM_TIM234_CCMR1_OC2M_TOGGLE                   3
1766 #define  STM_TIM234_CCMR1_OC2M_FORCE_LOW                4
1767 #define  STM_TIM234_CCMR1_OC2M_FORCE_HIGH               5
1768 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_1               6
1769 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_2               7
1770 #define  STM_TIM234_CCMR1_OC2M_MASK                     7
1771 #define STM_TIM234_CCMR1_OC2PE  11
1772 #define STM_TIM234_CCMR1_OC2FE  10
1773 #define STM_TIM234_CCMR1_CC2S   8
1774 #define  STM_TIM234_CCMR1_CC2S_OUTPUT                   0
1775 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI2                1
1776 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI1                2
1777 #define  STM_TIM234_CCMR1_CC2S_INPUT_TRC                3
1778 #define  STM_TIM234_CCMR1_CC2S_MASK                     3
1779
1780 #define STM_TIM234_CCMR1_OC1CE  7
1781 #define STM_TIM234_CCMR1_OC1M   4
1782 #define  STM_TIM234_CCMR1_OC1M_FROZEN                   0
1783 #define  STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH        1
1784 #define  STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH         2
1785 #define  STM_TIM234_CCMR1_OC1M_TOGGLE                   3
1786 #define  STM_TIM234_CCMR1_OC1M_FORCE_LOW                4
1787 #define  STM_TIM234_CCMR1_OC1M_FORCE_HIGH               5
1788 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_1               6
1789 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_2               7
1790 #define  STM_TIM234_CCMR1_OC1M_MASK                     7
1791 #define STM_TIM234_CCMR1_OC1PE  3
1792 #define STM_TIM234_CCMR1_OC1FE  2
1793 #define STM_TIM234_CCMR1_CC1S   0
1794 #define  STM_TIM234_CCMR1_CC1S_OUTPUT                   0
1795 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI1                1
1796 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI2                2
1797 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC                3
1798 #define  STM_TIM234_CCMR1_CC1S_MASK                     3
1799
1800 #define STM_TIM234_CCMR2_OC4CE  15
1801 #define STM_TIM234_CCMR2_OC4M   12
1802 #define  STM_TIM234_CCMR2_OC4M_FROZEN                   0
1803 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
1804 #define  STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH         2
1805 #define  STM_TIM234_CCMR2_OC4M_TOGGLE                   3
1806 #define  STM_TIM234_CCMR2_OC4M_FORCE_LOW                4
1807 #define  STM_TIM234_CCMR2_OC4M_FORCE_HIGH               5
1808 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_1               6
1809 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_2               7
1810 #define  STM_TIM234_CCMR2_OC4M_MASK                     7
1811 #define STM_TIM234_CCMR2_OC4PE  11
1812 #define STM_TIM234_CCMR2_OC4FE  10
1813 #define STM_TIM234_CCMR2_CC4S   8
1814 #define  STM_TIM234_CCMR2_CC4S_OUTPUT                   0
1815 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI4                1
1816 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI3                2
1817 #define  STM_TIM234_CCMR2_CC4S_INPUT_TRC                3
1818 #define  STM_TIM234_CCMR2_CC4S_MASK                     3
1819
1820 #define STM_TIM234_CCMR2_OC3CE  7
1821 #define STM_TIM234_CCMR2_OC3M   4
1822 #define  STM_TIM234_CCMR2_OC3M_FROZEN                   0
1823 #define  STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH        1
1824 #define  STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH         2
1825 #define  STM_TIM234_CCMR2_OC3M_TOGGLE                   3
1826 #define  STM_TIM234_CCMR2_OC3M_FORCE_LOW                4
1827 #define  STM_TIM234_CCMR2_OC3M_FORCE_HIGH               5
1828 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_1               6
1829 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_2               7
1830 #define  STM_TIM234_CCMR2_OC3M_MASK                     7
1831 #define STM_TIM234_CCMR2_OC3PE  3
1832 #define STM_TIM234_CCMR2_OC3FE  2
1833 #define STM_TIM234_CCMR2_CC3S   0
1834 #define  STM_TIM234_CCMR2_CC3S_OUTPUT                   0
1835 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI3                1
1836 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI4                2
1837 #define  STM_TIM234_CCMR2_CC3S_INPUT_TRC                3
1838 #define  STM_TIM234_CCMR2_CC3S_MASK                     3
1839
1840 #define STM_TIM234_CCER_CC4NP   15
1841 #define STM_TIM234_CCER_CC4P    13
1842 #define STM_TIM234_CCER_CC4E    12
1843 #define STM_TIM234_CCER_CC3NP   11
1844 #define STM_TIM234_CCER_CC3P    9
1845 #define STM_TIM234_CCER_CC3E    8
1846 #define STM_TIM234_CCER_CC2NP   7
1847 #define STM_TIM234_CCER_CC2P    5
1848 #define STM_TIM234_CCER_CC2E    4
1849 #define STM_TIM234_CCER_CC1NP   3
1850 #define STM_TIM234_CCER_CC1P    1
1851 #define STM_TIM234_CCER_CC1E    0
1852
1853 struct stm_usb {
1854         vuint32_t       epr[8];
1855         uint8_t         reserved_20[0x40 - 0x20];
1856         vuint32_t       cntr;
1857         vuint32_t       istr;
1858         vuint32_t       fnr;
1859         vuint32_t       daddr;
1860         vuint32_t       btable;
1861 };
1862
1863 #define STM_USB_EPR_CTR_RX      15
1864 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1865 #define STM_USB_EPR_DTOG_RX     14
1866 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1867 #define STM_USB_EPR_STAT_RX     12
1868 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1869 #define  STM_USB_EPR_STAT_RX_STALL                      1
1870 #define  STM_USB_EPR_STAT_RX_NAK                        2
1871 #define  STM_USB_EPR_STAT_RX_VALID                      3
1872 #define  STM_USB_EPR_STAT_RX_MASK                       3
1873 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1874 #define STM_USB_EPR_SETUP       11
1875 #define STM_USB_EPR_EP_TYPE     9
1876 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1877 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1878 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1879 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1880 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1881 #define STM_USB_EPR_EP_KIND     8
1882 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1883 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1884 #define STM_USB_EPR_CTR_TX      7
1885 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1886 #define STM_USB_EPR_DTOG_TX     6
1887 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1888 #define STM_USB_EPR_STAT_TX     4
1889 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1890 #define  STM_USB_EPR_STAT_TX_STALL                      1
1891 #define  STM_USB_EPR_STAT_TX_NAK                        2
1892 #define  STM_USB_EPR_STAT_TX_VALID                      3
1893 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1894 #define  STM_USB_EPR_STAT_TX_MASK                       3
1895 #define STM_USB_EPR_EA          0
1896 #define  STM_USB_EPR_EA_MASK                            0xf
1897
1898 #define STM_USB_CNTR_CTRM       15
1899 #define STM_USB_CNTR_PMAOVRM    14
1900 #define STM_USB_CNTR_ERRM       13
1901 #define STM_USB_CNTR_WKUPM      12
1902 #define STM_USB_CNTR_SUSPM      11
1903 #define STM_USB_CNTR_RESETM     10
1904 #define STM_USB_CNTR_SOFM       9
1905 #define STM_USB_CNTR_ESOFM      8
1906 #define STM_USB_CNTR_RESUME     4
1907 #define STM_USB_CNTR_FSUSP      3
1908 #define STM_USB_CNTR_LP_MODE    2
1909 #define STM_USB_CNTR_PDWN       1
1910 #define STM_USB_CNTR_FRES       0
1911
1912 #define STM_USB_ISTR_CTR        15
1913 #define STM_USB_ISTR_PMAOVR     14
1914 #define STM_USB_ISTR_ERR        13
1915 #define STM_USB_ISTR_WKUP       12
1916 #define STM_USB_ISTR_SUSP       11
1917 #define STM_USB_ISTR_RESET      10
1918 #define STM_USB_ISTR_SOF        9
1919 #define STM_USB_ISTR_ESOF       8
1920 #define STM_USB_ISTR_DIR        4
1921 #define STM_USB_ISTR_EP_ID      0
1922 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1923
1924 #define STM_USB_FNR_RXDP        15
1925 #define STM_USB_FNR_RXDM        14
1926 #define STM_USB_FNR_LCK         13
1927 #define STM_USB_FNR_LSOF        11
1928 #define  STM_USB_FNR_LSOF_MASK                  0x3
1929 #define STM_USB_FNR_FN          0
1930 #define  STM_USB_FNR_FN_MASK                    0x7ff
1931
1932 #define STM_USB_DADDR_EF        7
1933 #define STM_USB_DADDR_ADD       0
1934 #define  STM_USB_DADDR_ADD_MASK                 0x7f
1935
1936 extern struct stm_usb stm_usb;
1937
1938 union stm_usb_bdt {
1939         struct {
1940                 vuint32_t       addr_tx;
1941                 vuint32_t       count_tx;
1942                 vuint32_t       addr_rx;
1943                 vuint32_t       count_rx;
1944         } single;
1945         struct {
1946                 vuint32_t       addr;
1947                 vuint32_t       count;
1948         } double_tx[2];
1949         struct {
1950                 vuint32_t       addr;
1951                 vuint32_t       count;
1952         } double_rx[2];
1953 };
1954
1955 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
1956 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
1957 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
1958 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
1959 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
1960
1961 #define STM_USB_BDT_SIZE        8
1962
1963 extern uint8_t stm_usb_sram[];
1964
1965 struct stm_exti {
1966         vuint32_t       imr;
1967         vuint32_t       emr;
1968         vuint32_t       rtsr;
1969         vuint32_t       ftsr;
1970
1971         vuint32_t       swier;
1972         vuint32_t       pr;
1973 };
1974
1975 extern struct stm_exti stm_exti;
1976
1977 #endif /* _STM32L_H_ */