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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #ifndef _STM32L_H_
  19 #define _STM32L_H_
  20
  21 #include <stdint.h>
  22
  23 typedef volatile uint32_t       vuint32_t;
  24 typedef volatile void *         vvoid_t;
  25
  26 struct stm_gpio {
  27         vuint32_t       moder;
  28         vuint32_t       otyper;
  29         vuint32_t       ospeedr;
  30         vuint32_t       pupdr;
  31
  32         vuint32_t       idr;
  33         vuint32_t       odr;
  34         vuint32_t       bsrr;
  35         vuint32_t       lckr;
  36
  37         vuint32_t       afrl;
  38         vuint32_t       afrh;
  39 };
  40
  41 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  42 #define STM_MODER_MASK                  3
  43 #define STM_MODER_INPUT                 0
  44 #define STM_MODER_OUTPUT                1
  45 #define STM_MODER_ALTERNATE             2
  46 #define STM_MODER_ANALOG                3
  47
  48 static inline void
  49 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  50         gpio->moder = ((gpio->moder &
  51                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  52                        value << STM_MODER_SHIFT(pin));
  53 }
  54
  55 static inline vuint32_t
  56 stm_moder_get(struct stm_gpio *gpio, int pin) {
  57         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  58 }
  59
  60 #define STM_OTYPER_SHIFT(pin)           (pin)
  61 #define STM_OTYPER_MASK                 1
  62 #define STM_OTYPER_PUSH_PULL            0
  63 #define STM_OTYPER_OPEN_DRAIN           1
  64
  65 static inline void
  66 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  67         gpio->otyper = ((gpio->otyper &
  68                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  69                         value << STM_OTYPER_SHIFT(pin));
  70 }
  71
  72 static inline vuint32_t
  73 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  74         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  75 }
  76
  77 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  78 #define STM_OSPEEDR_MASK                3
  79 #define STM_OSPEEDR_400kHz              0
  80 #define STM_OSPEEDR_2MHz                1
  81 #define STM_OSPEEDR_10MHz               2
  82 #define STM_OSPEEDR_40MHz               3
  83
  84 static inline void
  85 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  86         gpio->ospeedr = ((gpio->ospeedr &
  87                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  88                        value << STM_OSPEEDR_SHIFT(pin));
  89 }
  90
  91 static inline vuint32_t
  92 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  93         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  94 }
  95
  96 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
  97 #define STM_PUPDR_MASK                  3
  98 #define STM_PUPDR_NONE                  0
  99 #define STM_PUPDR_PULL_UP               1
 100 #define STM_PUPDR_PULL_DOWN             2
 101 #define STM_PUPDR_RESERVED              3
 102
 103 static inline void
 104 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 105         gpio->pupdr = ((gpio->pupdr &
 106                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 107                        value << STM_PUPDR_SHIFT(pin));
 108 }
 109
 110 static inline uint32_t
 111 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 112         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 113 }
 114
 115 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 116 #define STM_AFR_MASK                    0xf
 117 #define STM_AFR_NONE                    0
 118 #define STM_AFR_AF0                     0x0
 119 #define STM_AFR_AF1                     0x1
 120 #define STM_AFR_AF2                     0x2
 121 #define STM_AFR_AF3                     0x3
 122 #define STM_AFR_AF4                     0x4
 123 #define STM_AFR_AF5                     0x5
 124 #define STM_AFR_AF6                     0x6
 125 #define STM_AFR_AF7                     0x7
 126 #define STM_AFR_AF8                     0x8
 127 #define STM_AFR_AF9                     0x9
 128 #define STM_AFR_AF10                    0xa
 129 #define STM_AFR_AF11                    0xb
 130 #define STM_AFR_AF12                    0xc
 131 #define STM_AFR_AF13                    0xd
 132 #define STM_AFR_AF14                    0xe
 133 #define STM_AFR_AF15                    0xf
 134
 135 static inline void
 136 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 137         /*
 138          * Set alternate pin mode too
 139          */
 140         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 141         if (pin < 8)
 142                 gpio->afrl = ((gpio->afrl &
 143                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 144                               value << STM_AFR_SHIFT(pin));
 145         else {
 146                 pin -= 8;
 147                 gpio->afrh = ((gpio->afrh &
 148                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 149                               value << STM_AFR_SHIFT(pin));
 150         }
 151 }
 152
 153 static inline uint32_t
 154 stm_afr_get(struct stm_gpio *gpio, int pin) {
 155         if (pin < 8)
 156                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 157         else {
 158                 pin -= 8;
 159                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 160         }
 161 }
 162
 163 static inline void
 164 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 165         /* Use the bit set/reset register to do this atomically */
 166         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 167 }
 168
 169 static inline uint8_t
 170 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 171         return (gpio->idr >> pin) & 1;
 172 }
 173
 174 extern struct stm_gpio stm_gpioa;
 175 extern struct stm_gpio stm_gpiob;
 176 extern struct stm_gpio stm_gpioc;
 177 extern struct stm_gpio stm_gpiod;
 178 extern struct stm_gpio stm_gpioe;
 179 extern struct stm_gpio stm_gpioh;
 180
 181 struct stm_usart {
 182         vuint32_t       sr;     /* status register */
 183         vuint32_t       dr;     /* data register */
 184         vuint32_t       brr;    /* baud rate register */
 185         vuint32_t       cr1;    /* control register 1 */
 186
 187         vuint32_t       cr2;    /* control register 2 */
 188         vuint32_t       cr3;    /* control register 3 */
 189         vuint32_t       gtpr;   /* guard time and prescaler */
 190 };
 191
 192 extern struct stm_usart stm_usart1;
 193 extern struct stm_usart stm_usart2;
 194 extern struct stm_usart stm_usart3;
 195
 196 #define STM_USART_SR_CTS        (9)     /* CTS flag */
 197 #define STM_USART_SR_LBD        (8)     /* LIN break detection flag */
 198 #define STM_USART_SR_TXE        (7)     /* Transmit data register empty */
 199 #define STM_USART_SR_TC         (6)     /* Transmission complete */
 200 #define STM_USART_SR_RXNE       (5)     /* Read data register not empty */
 201 #define STM_USART_SR_IDLE       (4)     /* IDLE line detected */
 202 #define STM_USART_SR_ORE        (3)     /* Overrun error */
 203 #define STM_USART_SR_NF         (2)     /* Noise detected flag */
 204 #define STM_USART_SR_FE         (1)     /* Framing error */
 205 #define STM_USART_SR_PE         (0)     /* Parity error */
 206
 207 #define STM_USART_CR1_OVER8     (15)    /* Oversampling mode */
 208 #define STM_USART_CR1_UE        (13)    /* USART enable */
 209 #define STM_USART_CR1_M         (12)    /* Word length */
 210 #define STM_USART_CR1_WAKE      (11)    /* Wakeup method */
 211 #define STM_USART_CR1_PCE       (10)    /* Parity control enable */
 212 #define STM_USART_CR1_PS        (9)     /* Parity selection */
 213 #define STM_USART_CR1_PEIE      (8)     /* PE interrupt enable */
 214 #define STM_USART_CR1_TXEIE     (7)     /* TXE interrupt enable */
 215 #define STM_USART_CR1_TCIE      (6)     /* Transmission complete interrupt enable */
 216 #define STM_USART_CR1_RXNEIE    (5)     /* RXNE interrupt enable */
 217 #define STM_USART_CR1_IDLEIE    (4)     /* IDLE interrupt enable */
 218 #define STM_USART_CR1_TE        (3)     /* Transmitter enable */
 219 #define STM_USART_CR1_RE        (2)     /* Receiver enable */
 220 #define STM_USART_CR1_RWU       (1)     /* Receiver wakeup */
 221 #define STM_USART_CR1_SBK       (0)     /* Send break */
 222
 223 #define STM_USART_CR2_LINEN     (14)    /* LIN mode enable */
 224 #define STM_USART_CR2_STOP      (12)    /* STOP bits */
 225 #define STM_USART_CR2_STOP_MASK 3
 226 #define STM_USART_CR2_STOP_1    0
 227 #define STM_USART_CR2_STOP_0_5  1
 228 #define STM_USART_CR2_STOP_2    2
 229 #define STM_USART_CR2_STOP_1_5  3
 230
 231 #define STM_USART_CR2_CLKEN     (11)    /* Clock enable */
 232 #define STM_USART_CR2_CPOL      (10)    /* Clock polarity */
 233 #define STM_USART_CR2_CPHA      (9)     /* Clock phase */
 234 #define STM_USART_CR2_LBCL      (8)     /* Last bit clock pulse */
 235 #define STM_USART_CR2_LBDIE     (6)     /* LIN break detection interrupt enable */
 236 #define STM_USART_CR2_LBDL      (5)     /* lin break detection length */
 237 #define STM_USART_CR2_ADD       (0)
 238 #define STM_USART_CR2_ADD_MASK  0xf
 239
 240 #define STM_USART_CR3_ONEBITE   (11)    /* One sample bit method enable */
 241 #define STM_USART_CR3_CTSIE     (10)    /* CTS interrupt enable */
 242 #define STM_USART_CR3_CTSE      (9)     /* CTS enable */
 243 #define STM_USART_CR3_RTSE      (8)     /* RTS enable */
 244 #define STM_USART_CR3_DMAT      (7)     /* DMA enable transmitter */
 245 #define STM_USART_CR3_DMAR      (6)     /* DMA enable receiver */
 246 #define STM_USART_CR3_SCEN      (5)     /* Smartcard mode enable */
 247 #define STM_USART_CR3_NACK      (4)     /* Smartcard NACK enable */
 248 #define STM_USART_CR3_HDSEL     (3)     /* Half-duplex selection */
 249 #define STM_USART_CR3_IRLP      (2)     /* IrDA low-power */
 250 #define STM_USART_CR3_IREN      (1)     /* IrDA mode enable */
 251 #define STM_USART_CR3_EIE       (0)     /* Error interrupt enable */
 252
 253 struct stm_tim {
 254 };
 255
 256 extern struct stm_tim stm_tim9;
 257
 258 struct stm_tim1011 {
 259         vuint32_t       cr1;
 260         uint32_t        unused_4;
 261         vuint32_t       smcr;
 262         vuint32_t       dier;
 263         vuint32_t       sr;
 264         vuint32_t       egr;
 265         vuint32_t       ccmr1;
 266         uint32_t        unused_1c;
 267         vuint32_t       ccer;
 268         vuint32_t       cnt;
 269         vuint32_t       psc;
 270         vuint32_t       arr;
 271         uint32_t        unused_30;
 272         vuint32_t       ccr1;
 273         uint32_t        unused_38;
 274         uint32_t        unused_3c;
 275         uint32_t        unused_40;
 276         uint32_t        unused_44;
 277         uint32_t        unused_48;
 278         uint32_t        unused_4c;
 279         vuint32_t       or;
 280 };
 281
 282 extern struct stm_tim1011 stm_tim10;
 283 extern struct stm_tim1011 stm_tim11;
 284
 285 #define STM_TIM1011_CR1_CKD     8
 286 #define  STM_TIM1011_CR1_CKD_1          0
 287 #define  STM_TIM1011_CR1_CKD_2          1
 288 #define  STM_TIM1011_CR1_CKD_4          2
 289 #define  STM_TIM1011_CR1_CKD_MASK       3
 290 #define STM_TIM1011_CR1_ARPE    7
 291 #define STM_TIM1011_CR1_URS     2
 292 #define STM_TIM1011_CR1_UDIS    1
 293 #define STM_TIM1011_CR1_CEN     0
 294
 295 #define STM_TIM1011_SMCR_ETP    15
 296 #define STM_TIM1011_SMCR_ECE    14
 297 #define STM_TIM1011_SMCR_ETPS   12
 298 #define  STM_TIM1011_SMCR_ETPS_OFF      0
 299 #define  STM_TIM1011_SMCR_ETPS_2        1
 300 #define  STM_TIM1011_SMCR_ETPS_4        2
 301 #define  STM_TIM1011_SMCR_ETPS_8        3
 302 #define  STM_TIM1011_SMCR_ETPS_MASK     3
 303 #define STM_TIM1011_SMCR_ETF    8
 304 #define  STM_TIM1011_SMCR_ETF_NONE              0
 305 #define  STM_TIM1011_SMCR_ETF_CK_INT_2          1
 306 #define  STM_TIM1011_SMCR_ETF_CK_INT_4          2
 307 #define  STM_TIM1011_SMCR_ETF_CK_INT_8          3
 308 #define  STM_TIM1011_SMCR_ETF_DTS_2_6           4
 309 #define  STM_TIM1011_SMCR_ETF_DTS_2_8           5
 310 #define  STM_TIM1011_SMCR_ETF_DTS_4_6           6
 311 #define  STM_TIM1011_SMCR_ETF_DTS_4_8           7
 312 #define  STM_TIM1011_SMCR_ETF_DTS_8_6           8
 313 #define  STM_TIM1011_SMCR_ETF_DTS_8_8           9
 314 #define  STM_TIM1011_SMCR_ETF_DTS_16_5          10
 315 #define  STM_TIM1011_SMCR_ETF_DTS_16_6          11
 316 #define  STM_TIM1011_SMCR_ETF_DTS_16_8          12
 317 #define  STM_TIM1011_SMCR_ETF_DTS_32_5          13
 318 #define  STM_TIM1011_SMCR_ETF_DTS_32_6          14
 319 #define  STM_TIM1011_SMCR_ETF_DTS_32_8          15
 320 #define  STM_TIM1011_SMCR_ETF_MASK              15
 321
 322 #define STM_TIM1011_DIER_CC1E   1
 323 #define STM_TIM1011_DIER_UIE    0
 324
 325 #define STM_TIM1011_SR_CC1OF    9
 326 #define STM_TIM1011_SR_CC1IF    1
 327 #define STM_TIM1011_SR_UIF      0
 328
 329 #define STM_TIM1011_EGR_CC1G    1
 330 #define STM_TIM1011_EGR_UG      0
 331
 332 #define STM_TIM1011_CCMR1_OC1CE 7
 333 #define STM_TIM1011_CCMR1_OC1M  4
 334 #define  STM_TIM1011_CCMR1_OC1M_FROZEN                  0
 335 #define  STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH   1
 336 #define  STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
 337 #define  STM_TIM1011_CCMR1_OC1M_TOGGLE                  3
 338 #define  STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE          4
 339 #define  STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE            5
 340 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_1              6
 341 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_2              7
 342 #define  STM_TIM1011_CCMR1_OC1M_MASK                    7
 343 #define STM_TIM1011_CCMR1_OC1PE 3
 344 #define STM_TIM1011_CCMR1_OC1FE 2
 345 #define STM_TIM1011_CCMR1_CC1S  0
 346 #define  STM_TIM1011_CCMR1_CC1S_OUTPUT                  0
 347 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI1               1
 348 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI2               2
 349 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TRC               3
 350 #define  STM_TIM1011_CCMR1_CC1S_MASK                    3
 351
 352 #define  STM_TIM1011_CCMR1_IC1F_NONE            0
 353 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_2        1
 354 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_4        2
 355 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_8        3
 356 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_6         4
 357 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_8         5
 358 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_6         6
 359 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_8         7
 360 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_6         8
 361 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_8         9
 362 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_5        10
 363 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_6        11
 364 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_8        12
 365 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_5        13
 366 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_6        14
 367 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_8        15
 368 #define  STM_TIM1011_CCMR1_IC1F_MASK            15
 369 #define STM_TIM1011_CCMR1_IC1PSC        2
 370 #define  STM_TIM1011_CCMR1_IC1PSC_1             0
 371 #define  STM_TIM1011_CCMR1_IC1PSC_2             1
 372 #define  STM_TIM1011_CCMR1_IC1PSC_4             2
 373 #define  STM_TIM1011_CCMR1_IC1PSC_8             3
 374 #define  STM_TIM1011_CCMR1_IC1PSC_MASK          3
 375 #define STM_TIM1011_CCMR1_CC1S          0
 376
 377 #define STM_TIM1011_CCER_CC1NP          3
 378 #define STM_TIM1011_CCER_CC1P           1
 379 #define STM_TIM1011_CCER_CC1E           0
 380
 381 #define STM_TIM1011_OR_TI1_RMP_RI       3
 382 #define STM_TIM1011_ETR_RMP             2
 383 #define STM_TIM1011_TI1_RMP             0
 384 #define  STM_TIM1011_TI1_RMP_GPIO               0
 385 #define  STM_TIM1011_TI1_RMP_LSI                1
 386 #define  STM_TIM1011_TI1_RMP_LSE                2
 387 #define  STM_TIM1011_TI1_RMP_RTC                3
 388 #define  STM_TIM1011_TI1_RMP_MASK               3
 389
 390 /* Flash interface */
 391
 392 struct stm_flash {
 393         vuint32_t       acr;
 394         vuint32_t       pecr;
 395         vuint32_t       pdkeyr;
 396         vuint32_t       pekeyr;
 397
 398         vuint32_t       prgkeyr;
 399         vuint32_t       optkeyr;
 400         vuint32_t       sr;
 401         vuint32_t       obr;
 402
 403         vuint32_t       wrpr;
 404 };
 405
 406 extern struct stm_flash stm_flash;
 407
 408 #define STM_FLASH_ACR_RUN_PD    (4)
 409 #define STM_FLASH_ACR_SLEEP_PD  (3)
 410 #define STM_FLASH_ACR_ACC64     (2)
 411 #define STM_FLASH_ACR_PRFEN     (1)
 412 #define STM_FLASH_ACR_LATENCY   (0)
 413
 414 #define STM_FLASH_PECR_OBL_LAUNCH       18
 415 #define STM_FLASH_PECR_ERRIE            17
 416 #define STM_FLASH_PECR_EOPIE            16
 417 #define STM_FLASH_PECR_FPRG             10
 418 #define STM_FLASH_PECR_ERASE            9
 419 #define STM_FLASH_PECR_FTDW             8
 420 #define STM_FLASH_PECR_DATA             4
 421 #define STM_FLASH_PECR_PROG             3
 422 #define STM_FLASH_PECR_OPTLOCK          2
 423 #define STM_FLASH_PECR_PRGLOCK          1
 424 #define STM_FLASH_PECR_PELOCK           0
 425
 426 #define STM_FLASH_SR_OPTVERR            11
 427 #define STM_FLASH_SR_SIZERR             10
 428 #define STM_FLASH_SR_PGAERR             9
 429 #define STM_FLASH_SR_WRPERR             8
 430 #define STM_FLASH_SR_READY              3
 431 #define STM_FLASH_SR_ENDHV              2
 432 #define STM_FLASH_SR_EOP                1
 433 #define STM_FLASH_SR_BSY                0
 434
 435 #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
 436 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
 437
 438 struct stm_rcc {
 439         vuint32_t       cr;
 440         vuint32_t       icscr;
 441         vuint32_t       cfgr;
 442         vuint32_t       cir;
 443
 444         vuint32_t       ahbrstr;
 445         vuint32_t       apb2rstr;
 446         vuint32_t       apb1rstr;
 447         vuint32_t       ahbenr;
 448
 449         vuint32_t       apb2enr;
 450         vuint32_t       apb1enr;
 451         vuint32_t       ahblenr;
 452         vuint32_t       apb2lpenr;
 453
 454         vuint32_t       apb1lpenr;
 455         vuint32_t       csr;
 456 };
 457
 458 extern struct stm_rcc stm_rcc;
 459
 460 /* Nominal high speed internal oscillator frequency is 16MHz */
 461 #define STM_HSI_FREQ            16000000
 462
 463 #define STM_RCC_CR_RTCPRE       (29)
 464 #define  STM_RCC_CR_RTCPRE_HSE_DIV_2    0
 465 #define  STM_RCC_CR_RTCPRE_HSE_DIV_4    1
 466 #define  STM_RCC_CR_RTCPRE_HSE_DIV_8    2
 467 #define  STM_RCC_CR_RTCPRE_HSE_DIV_16   3
 468 #define  STM_RCC_CR_RTCPRE_HSE_MASK     3
 469
 470 #define STM_RCC_CR_CSSON        (28)
 471 #define STM_RCC_CR_PLLRDY       (25)
 472 #define STM_RCC_CR_PLLON        (24)
 473 #define STM_RCC_CR_HSEBYP       (18)
 474 #define STM_RCC_CR_HSERDY       (17)
 475 #define STM_RCC_CR_HSEON        (16)
 476 #define STM_RCC_CR_MSIRDY       (9)
 477 #define STM_RCC_CR_MSION        (8)
 478 #define STM_RCC_CR_HSIRDY       (1)
 479 #define STM_RCC_CR_HSION        (0)
 480
 481 #define STM_RCC_CFGR_MCOPRE     (28)
 482 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 483 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 484 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 485 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 486 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 487 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7
 488
 489 #define STM_RCC_CFGR_MCOSEL     (24)
 490 #define  STM_RCC_CFGR_MCOSEL_DISABLE    0
 491 #define  STM_RCC_CFGR_MCOSEL_SYSCLK     1
 492 #define  STM_RCC_CFGR_MCOSEL_HSI        2
 493 #define  STM_RCC_CFGR_MCOSEL_MSI        3
 494 #define  STM_RCC_CFGR_MCOSEL_HSE        4
 495 #define  STM_RCC_CFGR_MCOSEL_PLL        5
 496 #define  STM_RCC_CFGR_MCOSEL_LSI        6
 497 #define  STM_RCC_CFGR_MCOSEL_LSE        7
 498 #define  STM_RCC_CFGR_MCOSEL_MASK       7
 499
 500 #define STM_RCC_CFGR_PLLDIV     (22)
 501 #define  STM_RCC_CFGR_PLLDIV_2          1
 502 #define  STM_RCC_CFGR_PLLDIV_3          2
 503 #define  STM_RCC_CFGR_PLLDIV_4          3
 504 #define  STM_RCC_CFGR_PLLDIV_MASK       3
 505
 506 #define STM_RCC_CFGR_PLLMUL     (18)
 507 #define  STM_RCC_CFGR_PLLMUL_3          0
 508 #define  STM_RCC_CFGR_PLLMUL_4          1
 509 #define  STM_RCC_CFGR_PLLMUL_6          2
 510 #define  STM_RCC_CFGR_PLLMUL_8          3
 511 #define  STM_RCC_CFGR_PLLMUL_12         4
 512 #define  STM_RCC_CFGR_PLLMUL_16         5
 513 #define  STM_RCC_CFGR_PLLMUL_24         6
 514 #define  STM_RCC_CFGR_PLLMUL_32         7
 515 #define  STM_RCC_CFGR_PLLMUL_48         8
 516 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 517
 518 #define STM_RCC_CFGR_PLLSRC     (16)
 519
 520 #define STM_RCC_CFGR_PPRE2      (11)
 521 #define  STM_RCC_CFGR_PPRE2_DIV_1       0
 522 #define  STM_RCC_CFGR_PPRE2_DIV_2       4
 523 #define  STM_RCC_CFGR_PPRE2_DIV_4       5
 524 #define  STM_RCC_CFGR_PPRE2_DIV_8       6
 525 #define  STM_RCC_CFGR_PPRE2_DIV_16      7
 526 #define  STM_RCC_CFGR_PPRE2_MASK        7
 527
 528 #define STM_RCC_CFGR_PPRE1      (8)
 529 #define  STM_RCC_CFGR_PPRE1_DIV_1       0
 530 #define  STM_RCC_CFGR_PPRE1_DIV_2       4
 531 #define  STM_RCC_CFGR_PPRE1_DIV_4       5
 532 #define  STM_RCC_CFGR_PPRE1_DIV_8       6
 533 #define  STM_RCC_CFGR_PPRE1_DIV_16      7
 534 #define  STM_RCC_CFGR_PPRE1_MASK        7
 535
 536 #define STM_RCC_CFGR_HPRE       (4)
 537 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 538 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 539 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 540 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 541 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 542 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 543 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 544 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 545 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 546 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 547
 548 #define STM_RCC_CFGR_SWS        (2)
 549 #define  STM_RCC_CFGR_SWS_MSI           0
 550 #define  STM_RCC_CFGR_SWS_HSI           1
 551 #define  STM_RCC_CFGR_SWS_HSE           2
 552 #define  STM_RCC_CFGR_SWS_PLL           3
 553 #define  STM_RCC_CFGR_SWS_MASK          3
 554
 555 #define STM_RCC_CFGR_SW         (0)
 556 #define  STM_RCC_CFGR_SW_MSI            0
 557 #define  STM_RCC_CFGR_SW_HSI            1
 558 #define  STM_RCC_CFGR_SW_HSE            2
 559 #define  STM_RCC_CFGR_SW_PLL            3
 560 #define  STM_RCC_CFGR_SW_MASK           3
 561
 562 #define STM_RCC_AHBENR_DMA1EN           (24)
 563 #define STM_RCC_AHBENR_FLITFEN          (15)
 564 #define STM_RCC_AHBENR_CRCEN            (12)
 565 #define STM_RCC_AHBENR_GPIOHEN          (5)
 566 #define STM_RCC_AHBENR_GPIOEEN          (4)
 567 #define STM_RCC_AHBENR_GPIODEN          (3)
 568 #define STM_RCC_AHBENR_GPIOCEN          (2)
 569 #define STM_RCC_AHBENR_GPIOBEN          (1)
 570 #define STM_RCC_AHBENR_GPIOAEN          (0)
 571
 572 #define STM_RCC_APB2ENR_USART1EN        (14)
 573 #define STM_RCC_APB2ENR_SPI1EN          (12)
 574 #define STM_RCC_APB2ENR_ADC1EN          (9)
 575 #define STM_RCC_APB2ENR_TIM11EN         (4)
 576 #define STM_RCC_APB2ENR_TIM10EN         (3)
 577 #define STM_RCC_APB2ENR_TIM9EN          (2)
 578 #define STM_RCC_APB2ENR_SYSCFGEN        (0)
 579
 580 #define STM_RCC_APB1ENR_COMPEN          (31)
 581 #define STM_RCC_APB1ENR_DACEN           (29)
 582 #define STM_RCC_APB1ENR_PWREN           (28)
 583 #define STM_RCC_APB1ENR_USBEN           (23)
 584 #define STM_RCC_APB1ENR_I2C2EN          (22)
 585 #define STM_RCC_APB1ENR_I2C1EN          (21)
 586 #define STM_RCC_APB1ENR_USART3EN        (18)
 587 #define STM_RCC_APB1ENR_USART2EN        (17)
 588 #define STM_RCC_APB1ENR_SPI2EN          (14)
 589 #define STM_RCC_APB1ENR_WWDGEN          (11)
 590 #define STM_RCC_APB1ENR_LCDEN           (9)
 591 #define STM_RCC_APB1ENR_TIM7EN          (5)
 592 #define STM_RCC_APB1ENR_TIM6EN          (4)
 593 #define STM_RCC_APB1ENR_TIM4EN          (2)
 594 #define STM_RCC_APB1ENR_TIM3EN          (1)
 595 #define STM_RCC_APB1ENR_TIM2EN          (0)
 596
 597 #define STM_RCC_CSR_LPWRRSTF            (31)
 598 #define STM_RCC_CSR_WWDGRSTF            (30)
 599 #define STM_RCC_CSR_IWDGRSTF            (29)
 600 #define STM_RCC_CSR_SFTRSTF             (28)
 601 #define STM_RCC_CSR_PORRSTF             (27)
 602 #define STM_RCC_CSR_PINRSTF             (26)
 603 #define STM_RCC_CSR_OBLRSTF             (25)
 604 #define STM_RCC_CSR_RMVF                (24)
 605 #define STM_RCC_CSR_RTFRST              (23)
 606 #define STM_RCC_CSR_RTCEN               (22)
 607 #define STM_RCC_CSR_RTCSEL              (16)
 608
 609 #define  STM_RCC_CSR_RTCSEL_NONE                0
 610 #define  STM_RCC_CSR_RTCSEL_LSE                 1
 611 #define  STM_RCC_CSR_RTCSEL_LSI                 2
 612 #define  STM_RCC_CSR_RTCSEL_HSE                 3
 613 #define  STM_RCC_CSR_RTCSEL_MASK                3
 614
 615 #define STM_RCC_CSR_LSEBYP              (10)
 616 #define STM_RCC_CSR_LSERDY              (9)
 617 #define STM_RCC_CSR_LSEON               (8)
 618 #define STM_RCC_CSR_LSIRDY              (1)
 619 #define STM_RCC_CSR_LSION               (0)
 620
 621 struct stm_pwr {
 622         vuint32_t       cr;
 623         vuint32_t       csr;
 624 };
 625
 626 extern struct stm_pwr stm_pwr;
 627
 628 #define STM_PWR_CR_LPRUN        (14)
 629
 630 #define STM_PWR_CR_VOS          (11)
 631 #define  STM_PWR_CR_VOS_1_8             1
 632 #define  STM_PWR_CR_VOS_1_5             2
 633 #define  STM_PWR_CR_VOS_1_2             3
 634 #define  STM_PWR_CR_VOS_MASK            3
 635
 636 #define STM_PWR_CR_FWU          (10)
 637 #define STM_PWR_CR_ULP          (9)
 638 #define STM_PWR_CR_DBP          (8)
 639
 640 #define STM_PWR_CR_PLS          (5)
 641 #define  STM_PWR_CR_PLS_1_9     0
 642 #define  STM_PWR_CR_PLS_2_1     1
 643 #define  STM_PWR_CR_PLS_2_3     2
 644 #define  STM_PWR_CR_PLS_2_5     3
 645 #define  STM_PWR_CR_PLS_2_7     4
 646 #define  STM_PWR_CR_PLS_2_9     5
 647 #define  STM_PWR_CR_PLS_3_1     6
 648 #define  STM_PWR_CR_PLS_EXT     7
 649 #define  STM_PWR_CR_PLS_MASK    7
 650
 651 #define STM_PWR_CR_PVDE         (4)
 652 #define STM_PWR_CR_CSBF         (3)
 653 #define STM_PWR_CR_CWUF         (2)
 654 #define STM_PWR_CR_PDDS         (1)
 655 #define STM_PWR_CR_LPSDSR       (0)
 656
 657 #define STM_PWR_CSR_EWUP3       (10)
 658 #define STM_PWR_CSR_EWUP2       (9)
 659 #define STM_PWR_CSR_EWUP1       (8)
 660 #define STM_PWR_CSR_REGLPF      (5)
 661 #define STM_PWR_CSR_VOSF        (4)
 662 #define STM_PWR_CSR_VREFINTRDYF (3)
 663 #define STM_PWR_CSR_PVDO        (2)
 664 #define STM_PWR_CSR_SBF         (1)
 665 #define STM_PWR_CSR_WUF         (0)
 666
 667 struct stm_tim67 {
 668         vuint32_t       cr1;
 669         vuint32_t       cr2;
 670         uint32_t        _unused_08;
 671         vuint32_t       dier;
 672
 673         vuint32_t       sr;
 674         vuint32_t       egr;
 675         uint32_t        _unused_18;
 676         uint32_t        _unused_1c;
 677
 678         uint32_t        _unused_20;
 679         vuint32_t       cnt;
 680         vuint32_t       psc;
 681         vuint32_t       arr;
 682 };
 683
 684 extern struct stm_tim67 stm_tim6;
 685
 686 #define STM_TIM67_CR1_ARPE      (7)
 687 #define STM_TIM67_CR1_OPM       (3)
 688 #define STM_TIM67_CR1_URS       (2)
 689 #define STM_TIM67_CR1_UDIS      (1)
 690 #define STM_TIM67_CR1_CEN       (0)
 691
 692 #define STM_TIM67_CR2_MMS       (4)
 693 #define  STM_TIM67_CR2_MMS_RESET        0
 694 #define  STM_TIM67_CR2_MMS_ENABLE       1
 695 #define  STM_TIM67_CR2_MMS_UPDATE       2
 696 #define  STM_TIM67_CR2_MMS_MASK         7
 697
 698 #define STM_TIM67_DIER_UDE      (8)
 699 #define STM_TIM67_DIER_UIE      (0)
 700
 701 #define STM_TIM67_SR_UIF        (0)
 702
 703 #define STM_TIM67_EGR_UG        (0)
 704
 705 struct stm_lcd {
 706         vuint32_t       cr;
 707         vuint32_t       fcr;
 708         vuint32_t       sr;
 709         vuint32_t       clr;
 710         uint32_t        unused_0x10;
 711         vuint32_t       ram[8*2];
 712 };
 713
 714 extern struct stm_lcd stm_lcd;
 715
 716 #define STM_LCD_CR_MUX_SEG              (7)
 717
 718 #define STM_LCD_CR_BIAS                 (5)
 719 #define  STM_LCD_CR_BIAS_1_4            0
 720 #define  STM_LCD_CR_BIAS_1_2            1
 721 #define  STM_LCD_CR_BIAS_1_3            2
 722 #define  STM_LCD_CR_BIAS_MASK           3
 723
 724 #define STM_LCD_CR_DUTY                 (2)
 725 #define  STM_LCD_CR_DUTY_STATIC         0
 726 #define  STM_LCD_CR_DUTY_1_2            1
 727 #define  STM_LCD_CR_DUTY_1_3            2
 728 #define  STM_LCD_CR_DUTY_1_4            3
 729 #define  STM_LCD_CR_DUTY_1_8            4
 730 #define  STM_LCD_CR_DUTY_MASK           7
 731
 732 #define STM_LCD_CR_VSEL                 (1)
 733 #define STM_LCD_CR_LCDEN                (0)
 734
 735 #define STM_LCD_FCR_PS                  (22)
 736 #define  STM_LCD_FCR_PS_1               0x0
 737 #define  STM_LCD_FCR_PS_2               0x1
 738 #define  STM_LCD_FCR_PS_4               0x2
 739 #define  STM_LCD_FCR_PS_8               0x3
 740 #define  STM_LCD_FCR_PS_16              0x4
 741 #define  STM_LCD_FCR_PS_32              0x5
 742 #define  STM_LCD_FCR_PS_64              0x6
 743 #define  STM_LCD_FCR_PS_128             0x7
 744 #define  STM_LCD_FCR_PS_256             0x8
 745 #define  STM_LCD_FCR_PS_512             0x9
 746 #define  STM_LCD_FCR_PS_1024            0xa
 747 #define  STM_LCD_FCR_PS_2048            0xb
 748 #define  STM_LCD_FCR_PS_4096            0xc
 749 #define  STM_LCD_FCR_PS_8192            0xd
 750 #define  STM_LCD_FCR_PS_16384           0xe
 751 #define  STM_LCD_FCR_PS_32768           0xf
 752 #define  STM_LCD_FCR_PS_MASK            0xf
 753
 754 #define STM_LCD_FCR_DIV                 (18)
 755 #define STM_LCD_FCR_DIV_16              0x0
 756 #define STM_LCD_FCR_DIV_17              0x1
 757 #define STM_LCD_FCR_DIV_18              0x2
 758 #define STM_LCD_FCR_DIV_19              0x3
 759 #define STM_LCD_FCR_DIV_20              0x4
 760 #define STM_LCD_FCR_DIV_21              0x5
 761 #define STM_LCD_FCR_DIV_22              0x6
 762 #define STM_LCD_FCR_DIV_23              0x7
 763 #define STM_LCD_FCR_DIV_24              0x8
 764 #define STM_LCD_FCR_DIV_25              0x9
 765 #define STM_LCD_FCR_DIV_26              0xa
 766 #define STM_LCD_FCR_DIV_27              0xb
 767 #define STM_LCD_FCR_DIV_28              0xc
 768 #define STM_LCD_FCR_DIV_29              0xd
 769 #define STM_LCD_FCR_DIV_30              0xe
 770 #define STM_LCD_FCR_DIV_31              0xf
 771 #define STM_LCD_FCR_DIV_MASK            0xf
 772
 773 #define STM_LCD_FCR_BLINK               (16)
 774 #define  STM_LCD_FCR_BLINK_DISABLE              0
 775 #define  STM_LCD_FCR_BLINK_SEG0_COM0            1
 776 #define  STM_LCD_FCR_BLINK_SEG0_COMALL          2
 777 #define  STM_LCD_FCR_BLINK_SEGALL_COMALL        3
 778 #define  STM_LCD_FCR_BLINK_MASK                 3
 779
 780 #define STM_LCD_FCR_BLINKF              (13)
 781 #define  STM_LCD_FCR_BLINKF_8                   0
 782 #define  STM_LCD_FCR_BLINKF_16                  1
 783 #define  STM_LCD_FCR_BLINKF_32                  2
 784 #define  STM_LCD_FCR_BLINKF_64                  3
 785 #define  STM_LCD_FCR_BLINKF_128                 4
 786 #define  STM_LCD_FCR_BLINKF_256                 5
 787 #define  STM_LCD_FCR_BLINKF_512                 6
 788 #define  STM_LCD_FCR_BLINKF_1024                7
 789 #define  STM_LCD_FCR_BLINKF_MASK                7
 790
 791 #define STM_LCD_FCR_CC                  (10)
 792 #define  STM_LCD_FCR_CC_MASK                    7
 793
 794 #define STM_LCD_FCR_DEAD                (7)
 795 #define  STM_LCD_FCR_DEAD_MASK                  7
 796
 797 #define STM_LCD_FCR_PON                 (4)
 798 #define  STM_LCD_FCR_PON_MASK                   7
 799
 800 #define STM_LCD_FCR_UDDIE               (3)
 801 #define STM_LCD_FCR_SOFIE               (1)
 802 #define STM_LCD_FCR_HD                  (0)
 803
 804 #define STM_LCD_SR_FCRSF                (5)
 805 #define STM_LCD_SR_RDY                  (4)
 806 #define STM_LCD_SR_UDD                  (3)
 807 #define STM_LCD_SR_UDR                  (2)
 808 #define STM_LCD_SR_SOF                  (1)
 809 #define STM_LCD_SR_ENS                  (0)
 810
 811 #define STM_LCD_CLR_UDDC                (3)
 812 #define STM_LCD_CLR_SOFC                (1)
 813
 814 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 815
 816 struct stm_nvic {
 817         vuint32_t       iser[8];        /* 0x000 0xe000e100 Set Enable Register */
 818
 819         uint8_t         _unused020[0x080 - 0x020];
 820
 821         vuint32_t       icer[8];        /* 0x080 0xe000e180 Clear Enable Register */
 822
 823         uint8_t         _unused0a0[0x100 - 0x0a0];
 824
 825         vuint32_t       ispr[8];        /* 0x100 0xe000e200 Set Pending Register */
 826
 827         uint8_t         _unused120[0x180 - 0x120];
 828
 829         vuint32_t       icpr[8];        /* 0x180 0xe000e280 Clear Pending Register */
 830
 831         uint8_t         _unused1a0[0x200 - 0x1a0];
 832
 833         vuint32_t       iabr[8];        /* 0x200 0xe000e300 Active Bit Register */
 834
 835         uint8_t         _unused220[0x300 - 0x220];
 836
 837         vuint32_t       ipr[60];        /* 0x300 0xe000e400 Priority Register */
 838
 839         uint8_t         _unused3f0[0xc00 - 0x3f0];
 840
 841         vuint32_t       cpuid_base;     /* 0xc00 0xe000ed00 CPUID Base Register */
 842         vuint32_t       ics;            /* 0xc04 0xe000ed04 Interrupt Control State Register */
 843         vuint32_t       vto;            /* 0xc08 0xe000ed08 Vector Table Offset Register */
 844         vuint32_t       ai_rc;          /* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */
 845         vuint32_t       sc;             /* 0xc10 0xe000ed10 System Control Register */
 846         vuint32_t       cc;             /* 0xc14 0xe000ed14 Configuration Control Register */
 847
 848         uint8_t         _unusedc18[0xe00 - 0xc18];
 849
 850         vuint32_t       stir;           /* 0xe00 */
 851 };
 852
 853 extern struct stm_nvic stm_nvic;
 854
 855 #define IRQ_REG(irq)    ((irq) >> 5)
 856 #define IRQ_BIT(irq)    ((irq) & 0x1f)
 857 #define IRQ_MASK(irq)   (1 << IRQ_BIT(irq))
 858 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
 859
 860 static inline void
 861 stm_nvic_set_enable(int irq) {
 862         stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
 863 }
 864
 865 static inline void
 866 stm_nvic_clear_enable(int irq) {
 867         stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
 868 }
 869
 870 static inline int
 871 stm_nvic_enabled(int irq) {
 872         return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
 873 }
 874
 875 static inline void
 876 stm_nvic_set_pending(int irq) {
 877         stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
 878 }
 879
 880 static inline void
 881 stm_nvic_clear_pending(int irq) {
 882         stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
 883 }
 884
 885 static inline int
 886 stm_nvic_pending(int irq) {
 887         return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
 888 }
 889
 890 static inline int
 891 stm_nvic_active(int irq) {
 892         return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
 893 }
 894
 895 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 896 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 897 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 898
 899 static inline void
 900 stm_nvic_set_priority(int irq, uint8_t prio) {
 901         int             n = IRQ_PRIO_REG(irq);
 902         uint32_t        v;
 903
 904         v = stm_nvic.ipr[n];
 905         v &= ~IRQ_PRIO_MASK(irq);
 906         v |= (prio) << IRQ_PRIO_BIT(irq);
 907         stm_nvic.ipr[n] = v;
 908 }
 909
 910 static inline uint8_t
 911 stm_nvic_get_priority(int irq) {
 912         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 913 }
 914
 915 struct stm_scb {
 916         vuint32_t       cpuid;
 917         vuint32_t       icsr;
 918         vuint32_t       vtor;
 919         vuint32_t       aircr;
 920
 921         vuint32_t       scr;
 922         vuint32_t       ccr;
 923         vuint32_t       shpr1;
 924         vuint32_t       shpr2;
 925
 926         vuint32_t       shpr3;
 927         vuint32_t       shcrs;
 928         vuint32_t       cfsr;
 929         vuint32_t       hfsr;
 930
 931         uint32_t        unused_30;
 932         vuint32_t       mmfar;
 933         vuint32_t       bfar;
 934 };
 935
 936 extern struct stm_scb stm_scb;
 937
 938 #define STM_SCB_AIRCR_VECTKEY           16
 939 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
 940 #define STM_SCB_AIRCR_PRIGROUP          8
 941 #define STM_SCB_AIRCR_SYSRESETREQ       2
 942 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
 943 #define STM_SCB_AIRCR_VECTRESET         0
 944
 945 struct stm_mpu {
 946         vuint32_t       typer;
 947         vuint32_t       cr;
 948         vuint32_t       rnr;
 949         vuint32_t       rbar;
 950
 951         vuint32_t       rasr;
 952         vuint32_t       rbar_a1;
 953         vuint32_t       rasr_a1;
 954         vuint32_t       rbar_a2;
 955         vuint32_t       rasr_a2;
 956         vuint32_t       rbar_a3;
 957         vuint32_t       rasr_a3;
 958 };
 959
 960 extern struct stm_mpu stm_mpu;
 961
 962 #define STM_MPU_TYPER_IREGION   16
 963 #define  STM_MPU_TYPER_IREGION_MASK     0xff
 964 #define STM_MPU_TYPER_DREGION   8
 965 #define  STM_MPU_TYPER_DREGION_MASK     0xff
 966 #define STM_MPU_TYPER_SEPARATE  0
 967
 968 #define STM_MPU_CR_PRIVDEFENA   2
 969 #define STM_MPU_CR_HFNMIENA     1
 970 #define STM_MPU_CR_ENABLE       0
 971
 972 #define STM_MPU_RNR_REGION      0
 973 #define STM_MPU_RNR_REGION_MASK         0xff
 974
 975 #define STM_MPU_RBAR_ADDR       5
 976 #define STM_MPU_RBAR_ADDR_MASK          0x7ffffff
 977
 978 #define STM_MPU_RBAR_VALID      4
 979 #define STM_MPU_RBAR_REGION     0
 980 #define STM_MPU_RBAR_REGION_MASK        0xf
 981
 982 #define STM_MPU_RASR_XN         28
 983 #define STM_MPU_RASR_AP         24
 984 #define  STM_MPU_RASR_AP_NONE_NONE      0
 985 #define  STM_MPU_RASR_AP_RW_NONE        1
 986 #define  STM_MPU_RASR_AP_RW_RO          2
 987 #define  STM_MPU_RASR_AP_RW_RW          3
 988 #define  STM_MPU_RASR_AP_RO_NONE        5
 989 #define  STM_MPU_RASR_AP_RO_RO          6
 990 #define  STM_MPU_RASR_AP_MASK           7
 991 #define STM_MPU_RASR_TEX        19
 992 #define  STM_MPU_RASR_TEX_MASK          7
 993 #define STM_MPU_RASR_S          18
 994 #define STM_MPU_RASR_C          17
 995 #define STM_MPU_RASR_B          16
 996 #define STM_MPU_RASR_SRD        8
 997 #define  STM_MPU_RASR_SRD_MASK          0xff
 998 #define STM_MPU_RASR_SIZE       1
 999 #define  STM_MPU_RASR_SIZE_MASK         0x1f
1000 #define STM_MPU_RASR_ENABLE     0
1001
1002 #define isr(name) void stm_ ## name ## _isr(void);
1003
1004 isr(nmi)
1005 isr(hardfault)
1006 isr(memmanage)
1007 isr(busfault)
1008 isr(usagefault)
1009 isr(svc)
1010 isr(debugmon)
1011 isr(pendsv)
1012 isr(systick)
1013 isr(wwdg)
1014 isr(pvd)
1015 isr(tamper_stamp)
1016 isr(rtc_wkup)
1017 isr(flash)
1018 isr(rcc)
1019 isr(exti0)
1020 isr(exti1)
1021 isr(exti2)
1022 isr(exti3)
1023 isr(exti4)
1024 isr(dma1_channel1)
1025 isr(dma1_channel2)
1026 isr(dma1_channel3)
1027 isr(dma1_channel4)
1028 isr(dma1_channel5)
1029 isr(dma1_channel6)
1030 isr(dma1_channel7)
1031 isr(adc1)
1032 isr(usb_hp)
1033 isr(usb_lp)
1034 isr(dac)
1035 isr(comp)
1036 isr(exti9_5)
1037 isr(lcd)
1038 isr(tim9)
1039 isr(tim10)
1040 isr(tim11)
1041 isr(tim2)
1042 isr(tim3)
1043 isr(tim4)
1044 isr(i2c1_ev)
1045 isr(i2c1_er)
1046 isr(i2c2_ev)
1047 isr(i2c2_er)
1048 isr(spi1)
1049 isr(spi2)
1050 isr(usart1)
1051 isr(usart2)
1052 isr(usart3)
1053 isr(exti15_10)
1054 isr(rtc_alarm)
1055 isr(usb_fs_wkup)
1056 isr(tim6)
1057 isr(tim7)
1058
1059 #undef isr
1060
1061 #define STM_ISR_WWDG_POS                0
1062 #define STM_ISR_PVD_POS                 1
1063 #define STM_ISR_TAMPER_STAMP_POS        2
1064 #define STM_ISR_RTC_WKUP_POS            3
1065 #define STM_ISR_FLASH_POS               4
1066 #define STM_ISR_RCC_POS                 5
1067 #define STM_ISR_EXTI0_POS               6
1068 #define STM_ISR_EXTI1_POS               7
1069 #define STM_ISR_EXTI2_POS               8
1070 #define STM_ISR_EXTI3_POS               9
1071 #define STM_ISR_EXTI4_POS               10
1072 #define STM_ISR_DMA1_CHANNEL1_POS       11
1073 #define STM_ISR_DMA2_CHANNEL1_POS       12
1074 #define STM_ISR_DMA3_CHANNEL1_POS       13
1075 #define STM_ISR_DMA4_CHANNEL1_POS       14
1076 #define STM_ISR_DMA5_CHANNEL1_POS       15
1077 #define STM_ISR_DMA6_CHANNEL1_POS       16
1078 #define STM_ISR_DMA7_CHANNEL1_POS       17
1079 #define STM_ISR_ADC1_POS                18
1080 #define STM_ISR_USB_HP_POS              19
1081 #define STM_ISR_USB_LP_POS              20
1082 #define STM_ISR_DAC_POS                 21
1083 #define STM_ISR_COMP_POS                22
1084 #define STM_ISR_EXTI9_5_POS             23
1085 #define STM_ISR_LCD_POS                 24
1086 #define STM_ISR_TIM9_POS                25
1087 #define STM_ISR_TIM10_POS               26
1088 #define STM_ISR_TIM11_POS               27
1089 #define STM_ISR_TIM2_POS                28
1090 #define STM_ISR_TIM3_POS                29
1091 #define STM_ISR_TIM4_POS                30
1092 #define STM_ISR_I2C1_EV_POS             31
1093 #define STM_ISR_I2C1_ER_POS             32
1094 #define STM_ISR_I2C2_EV_POS             33
1095 #define STM_ISR_I2C2_ER_POS             34
1096 #define STM_ISR_SPI1_POS                35
1097 #define STM_ISR_SPI2_POS                36
1098 #define STM_ISR_USART1_POS              37
1099 #define STM_ISR_USART2_POS              38
1100 #define STM_ISR_USART3_POS              39
1101 #define STM_ISR_EXTI15_10_POS           40
1102 #define STM_ISR_RTC_ALARM_POS           41
1103 #define STM_ISR_USB_FS_WKUP_POS         42
1104 #define STM_ISR_TIM6_POS                43
1105 #define STM_ISR_TIM7_POS                44
1106
1107 struct stm_syscfg {
1108         vuint32_t       memrmp;
1109         vuint32_t       pmc;
1110         vuint32_t       exticr[4];
1111 };
1112
1113 extern struct stm_syscfg stm_syscfg;
1114
1115 #define STM_SYSCFG_MEMRMP_MEM_MODE      0
1116 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH          0
1117 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH        1
1118 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SRAM                3
1119 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MASK                3
1120
1121 #define STM_SYSCFG_PMC_USB_PU           0
1122
1123 #define STM_SYSCFG_EXTICR_PA            0
1124 #define STM_SYSCFG_EXTICR_PB            1
1125 #define STM_SYSCFG_EXTICR_PC            2
1126 #define STM_SYSCFG_EXTICR_PD            3
1127 #define STM_SYSCFG_EXTICR_PE            4
1128 #define STM_SYSCFG_EXTICR_PH            5
1129
1130 static inline void
1131 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1132         uint8_t reg = pin >> 2;
1133         uint8_t shift = (pin & 3) << 2;
1134         uint8_t val = 0;
1135
1136         /* Enable SYSCFG */
1137         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
1138
1139         if (gpio == &stm_gpioa)
1140                 val = STM_SYSCFG_EXTICR_PA;
1141         else if (gpio == &stm_gpiob)
1142                 val = STM_SYSCFG_EXTICR_PB;
1143         else if (gpio == &stm_gpioc)
1144                 val = STM_SYSCFG_EXTICR_PC;
1145         else if (gpio == &stm_gpiod)
1146                 val = STM_SYSCFG_EXTICR_PD;
1147         else if (gpio == &stm_gpioe)
1148                 val = STM_SYSCFG_EXTICR_PE;
1149
1150         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
1151 }
1152
1153
1154 struct stm_dma_channel {
1155         vuint32_t       ccr;
1156         vuint32_t       cndtr;
1157         vvoid_t         cpar;
1158         vvoid_t         cmar;
1159         vuint32_t       reserved;
1160 };
1161
1162 #define STM_NUM_DMA     7
1163
1164 struct stm_dma {
1165         vuint32_t               isr;
1166         vuint32_t               ifcr;
1167         struct stm_dma_channel  channel[STM_NUM_DMA];
1168 };
1169
1170 extern struct stm_dma stm_dma;
1171
1172 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
1173  */
1174
1175 #define STM_DMA_INDEX(channel)          ((channel) - 1)
1176
1177 #define STM_DMA_ISR(index)              ((index) << 2)
1178 #define STM_DMA_ISR_MASK                        0xf
1179 #define STM_DMA_ISR_TEIF                        3
1180 #define STM_DMA_ISR_HTIF                        2
1181 #define STM_DMA_ISR_TCIF                        1
1182 #define STM_DMA_ISR_GIF                         0
1183
1184 #define STM_DMA_IFCR(index)             ((index) << 2)
1185 #define STM_DMA_IFCR_MASK                       0xf
1186 #define STM_DMA_IFCR_CTEIF                      3
1187 #define STM_DMA_IFCR_CHTIF                      2
1188 #define STM_DMA_IFCR_CTCIF                      1
1189 #define STM_DMA_IFCR_CGIF                       0
1190
1191 #define STM_DMA_CCR_MEM2MEM             (14)
1192
1193 #define STM_DMA_CCR_PL                  (12)
1194 #define  STM_DMA_CCR_PL_LOW                     (0)
1195 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
1196 #define  STM_DMA_CCR_PL_HIGH                    (2)
1197 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
1198 #define  STM_DMA_CCR_PL_MASK                    (3)
1199
1200 #define STM_DMA_CCR_MSIZE               (10)
1201 #define  STM_DMA_CCR_MSIZE_8                    (0)
1202 #define  STM_DMA_CCR_MSIZE_16                   (1)
1203 #define  STM_DMA_CCR_MSIZE_32                   (2)
1204 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
1205
1206 #define STM_DMA_CCR_PSIZE               (8)
1207 #define  STM_DMA_CCR_PSIZE_8                    (0)
1208 #define  STM_DMA_CCR_PSIZE_16                   (1)
1209 #define  STM_DMA_CCR_PSIZE_32                   (2)
1210 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
1211
1212 #define STM_DMA_CCR_MINC                (7)
1213 #define STM_DMA_CCR_PINC                (6)
1214 #define STM_DMA_CCR_CIRC                (5)
1215 #define STM_DMA_CCR_DIR                 (4)
1216 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
1217 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
1218 #define STM_DMA_CCR_TEIE                (3)
1219 #define STM_DMA_CCR_HTIE                (2)
1220 #define STM_DMA_CCR_TCIE                (1)
1221 #define STM_DMA_CCR_EN                  (0)
1222
1223 #define STM_DMA_CHANNEL_ADC1            1
1224 #define STM_DMA_CHANNEL_SPI1_RX         2
1225 #define STM_DMA_CHANNEL_SPI1_TX         3
1226 #define STM_DMA_CHANNEL_SPI2_RX         4
1227 #define STM_DMA_CHANNEL_SPI2_TX         5
1228 #define STM_DMA_CHANNEL_USART3_TX       2
1229 #define STM_DMA_CHANNEL_USART3_RX       3
1230 #define STM_DMA_CHANNEL_USART1_TX       4
1231 #define STM_DMA_CHANNEL_USART1_RX       5
1232 #define STM_DMA_CHANNEL_USART2_RX       6
1233 #define STM_DMA_CHANNEL_USART2_TX       7
1234 #define STM_DMA_CHANNEL_I2C2_TX         4
1235 #define STM_DMA_CHANNEL_I2C2_RX         5
1236 #define STM_DMA_CHANNEL_I2C1_TX         6
1237 #define STM_DMA_CHANNEL_I2C1_RX         7
1238 #define STM_DMA_CHANNEL_TIM2_CH3        1
1239 #define STM_DMA_CHANNEL_TIM2_UP         2
1240 #define STM_DMA_CHANNEL_TIM2_CH1        5
1241 #define STM_DMA_CHANNEL_TIM2_CH2        7
1242 #define STM_DMA_CHANNEL_TIM2_CH4        7
1243 #define STM_DMA_CHANNEL_TIM3_CH3        2
1244 #define STM_DMA_CHANNEL_TIM3_CH4        3
1245 #define STM_DMA_CHANNEL_TIM3_UP         3
1246 #define STM_DMA_CHANNEL_TIM3_CH1        6
1247 #define STM_DMA_CHANNEL_TIM3_TRIG       6
1248 #define STM_DMA_CHANNEL_TIM4_CH1        1
1249 #define STM_DMA_CHANNEL_TIM4_CH2        4
1250 #define STM_DMA_CHANNEL_TIM4_CH3        5
1251 #define STM_DMA_CHANNEL_TIM4_UP         7
1252 #define STM_DMA_CHANNEL_TIM6_UP_DA      2
1253 #define STM_DMA_CHANNEL_C_CHANNEL1      2
1254 #define STM_DMA_CHANNEL_TIM7_UP_DA      3
1255 #define STM_DMA_CHANNEL_C_CHANNEL2      3
1256
1257 /*
1258  * Only spi channel 1 and 2 can use DMA
1259  */
1260 #define STM_NUM_SPI     2
1261
1262 struct stm_spi {
1263         vuint32_t       cr1;
1264         vuint32_t       cr2;
1265         vuint32_t       sr;
1266         vuint32_t       dr;
1267         vuint32_t       crcpr;
1268         vuint32_t       rxcrcr;
1269         vuint32_t       txcrcr;
1270 };
1271
1272 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1273
1274 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1275  */
1276
1277 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1278
1279 #define STM_SPI_CR1_BIDIMODE            15
1280 #define STM_SPI_CR1_BIDIOE              14
1281 #define STM_SPI_CR1_CRCEN               13
1282 #define STM_SPI_CR1_CRCNEXT             12
1283 #define STM_SPI_CR1_DFF                 11
1284 #define STM_SPI_CR1_RXONLY              10
1285 #define STM_SPI_CR1_SSM                 9
1286 #define STM_SPI_CR1_SSI                 8
1287 #define STM_SPI_CR1_LSBFIRST            7
1288 #define STM_SPI_CR1_SPE                 6
1289 #define STM_SPI_CR1_BR                  3
1290 #define  STM_SPI_CR1_BR_PCLK_2                  0
1291 #define  STM_SPI_CR1_BR_PCLK_4                  1
1292 #define  STM_SPI_CR1_BR_PCLK_8                  2
1293 #define  STM_SPI_CR1_BR_PCLK_16                 3
1294 #define  STM_SPI_CR1_BR_PCLK_32                 4
1295 #define  STM_SPI_CR1_BR_PCLK_64                 5
1296 #define  STM_SPI_CR1_BR_PCLK_128                6
1297 #define  STM_SPI_CR1_BR_PCLK_256                7
1298 #define  STM_SPI_CR1_BR_MASK                    7
1299
1300 #define STM_SPI_CR1_MSTR                2
1301 #define STM_SPI_CR1_CPOL                1
1302 #define STM_SPI_CR1_CPHA                0
1303
1304 #define STM_SPI_CR2_TXEIE       7
1305 #define STM_SPI_CR2_RXNEIE      6
1306 #define STM_SPI_CR2_ERRIE       5
1307 #define STM_SPI_CR2_SSOE        2
1308 #define STM_SPI_CR2_TXDMAEN     1
1309 #define STM_SPI_CR2_RXDMAEN     0
1310
1311 #define STM_SPI_SR_BSY          7
1312 #define STM_SPI_SR_OVR          6
1313 #define STM_SPI_SR_MODF         5
1314 #define STM_SPI_SR_CRCERR       4
1315 #define STM_SPI_SR_TXE          1
1316 #define STM_SPI_SR_RXNE         0
1317
1318 struct stm_adc {
1319         vuint32_t       sr;
1320         vuint32_t       cr1;
1321         vuint32_t       cr2;
1322         vuint32_t       smpr1;
1323         vuint32_t       smpr2;
1324         vuint32_t       smpr3;
1325         vuint32_t       jofr1;
1326         vuint32_t       jofr2;
1327         vuint32_t       jofr3;
1328         vuint32_t       jofr4;
1329         vuint32_t       htr;
1330         vuint32_t       ltr;
1331         vuint32_t       sqr1;
1332         vuint32_t       sqr2;
1333         vuint32_t       sqr3;
1334         vuint32_t       sqr4;
1335         vuint32_t       sqr5;
1336         vuint32_t       jsqr;
1337         vuint32_t       jdr1;
1338         vuint32_t       jdr2;
1339         vuint32_t       jdr3;
1340         vuint32_t       jdr4;
1341         vuint32_t       dr;
1342         uint8_t         reserved[0x300 - 0x5c];
1343         vuint32_t       csr;
1344         vuint32_t       ccr;
1345 };
1346
1347 extern struct stm_adc stm_adc;
1348
1349 #define STM_ADC_SR_JCNR         9
1350 #define STM_ADC_SR_RCNR         8
1351 #define STM_ADC_SR_ADONS        6
1352 #define STM_ADC_SR_OVR          5
1353 #define STM_ADC_SR_STRT         4
1354 #define STM_ADC_SR_JSTRT        3
1355 #define STM_ADC_SR_JEOC         2
1356 #define STM_ADC_SR_EOC          1
1357 #define STM_ADC_SR_AWD          0
1358
1359 #define STM_ADC_CR1_OVRIE       26
1360 #define STM_ADC_CR1_RES         24
1361 #define  STM_ADC_CR1_RES_12             0
1362 #define  STM_ADC_CR1_RES_10             1
1363 #define  STM_ADC_CR1_RES_8              2
1364 #define  STM_ADC_CR1_RES_6              3
1365 #define  STM_ADC_CR1_RES_MASK           3
1366 #define STM_ADC_CR1_AWDEN       23
1367 #define STM_ADC_CR1_JAWDEN      22
1368 #define STM_ADC_CR1_PDI         17
1369 #define STM_ADC_CR1_PDD         16
1370 #define STM_ADC_CR1_DISCNUM     13
1371 #define  STM_ADC_CR1_DISCNUM_1          0
1372 #define  STM_ADC_CR1_DISCNUM_2          1
1373 #define  STM_ADC_CR1_DISCNUM_3          2
1374 #define  STM_ADC_CR1_DISCNUM_4          3
1375 #define  STM_ADC_CR1_DISCNUM_5          4
1376 #define  STM_ADC_CR1_DISCNUM_6          5
1377 #define  STM_ADC_CR1_DISCNUM_7          6
1378 #define  STM_ADC_CR1_DISCNUM_8          7
1379 #define  STM_ADC_CR1_DISCNUM_MASK       7
1380 #define STM_ADC_CR1_JDISCEN     12
1381 #define STM_ADC_CR1_DISCEN      11
1382 #define STM_ADC_CR1_JAUTO       10
1383 #define STM_ADC_CR1_AWDSGL      9
1384 #define STM_ADC_CR1_SCAN        8
1385 #define STM_ADC_CR1_JEOCIE      7
1386 #define STM_ADC_CR1_AWDIE       6
1387 #define STM_ADC_CR1_EOCIE       5
1388 #define STM_ADC_CR1_AWDCH       0
1389 #define  STM_ADC_CR1_AWDCH_MASK         0x1f
1390
1391 #define STM_ADC_CR2_SWSTART     30
1392 #define STM_ADC_CR2_EXTEN       28
1393 #define  STM_ADC_CR2_EXTEN_DISABLE      0
1394 #define  STM_ADC_CR2_EXTEN_RISING       1
1395 #define  STM_ADC_CR2_EXTEN_FALLING      2
1396 #define  STM_ADC_CR2_EXTEN_BOTH         3
1397 #define  STM_ADC_CR2_EXTEN_MASK         3
1398 #define STM_ADC_CR2_EXTSEL      24
1399 #define  STM_ADC_CR2_EXTSEL_TIM9_CC2    0
1400 #define  STM_ADC_CR2_EXTSEL_TIM9_TRGO   1
1401 #define  STM_ADC_CR2_EXTSEL_TIM2_CC3    2
1402 #define  STM_ADC_CR2_EXTSEL_TIM2_CC2    3
1403 #define  STM_ADC_CR2_EXTSEL_TIM3_TRGO   4
1404 #define  STM_ADC_CR2_EXTSEL_TIM4_CC4    5
1405 #define  STM_ADC_CR2_EXTSEL_TIM2_TRGO   6
1406 #define  STM_ADC_CR2_EXTSEL_TIM3_CC1    7
1407 #define  STM_ADC_CR2_EXTSEL_TIM3_CC3    8
1408 #define  STM_ADC_CR2_EXTSEL_TIM4_TRGO   9
1409 #define  STM_ADC_CR2_EXTSEL_TIM6_TRGO   10
1410 #define  STM_ADC_CR2_EXTSEL_EXTI_11     15
1411 #define  STM_ADC_CR2_EXTSEL_MASK        15
1412 #define STM_ADC_CR2_JWSTART     22
1413 #define STM_ADC_CR2_JEXTEN      20
1414 #define  STM_ADC_CR2_JEXTEN_DISABLE     0
1415 #define  STM_ADC_CR2_JEXTEN_RISING      1
1416 #define  STM_ADC_CR2_JEXTEN_FALLING     2
1417 #define  STM_ADC_CR2_JEXTEN_BOTH        3
1418 #define  STM_ADC_CR2_JEXTEN_MASK        3
1419 #define STM_ADC_CR2_JEXTSEL     16
1420 #define  STM_ADC_CR2_JEXTSEL_TIM9_CC1   0
1421 #define  STM_ADC_CR2_JEXTSEL_TIM9_TRGO  1
1422 #define  STM_ADC_CR2_JEXTSEL_TIM2_TRGO  2
1423 #define  STM_ADC_CR2_JEXTSEL_TIM2_CC1   3
1424 #define  STM_ADC_CR2_JEXTSEL_TIM3_CC4   4
1425 #define  STM_ADC_CR2_JEXTSEL_TIM4_TRGO  5
1426 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC1   6
1427 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC2   7
1428 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC3   8
1429 #define  STM_ADC_CR2_JEXTSEL_TIM10_CC1  9
1430 #define  STM_ADC_CR2_JEXTSEL_TIM7_TRGO  10
1431 #define  STM_ADC_CR2_JEXTSEL_EXTI_15    15
1432 #define  STM_ADC_CR2_JEXTSEL_MASK       15
1433 #define STM_ADC_CR2_ALIGN       11
1434 #define STM_ADC_CR2_EOCS        10
1435 #define STM_ADC_CR2_DDS         9
1436 #define STM_ADC_CR2_DMA         8
1437 #define STM_ADC_CR2_DELS        4
1438 #define  STM_ADC_CR2_DELS_NONE          0
1439 #define  STM_ADC_CR2_DELS_UNTIL_READ    1
1440 #define  STM_ADC_CR2_DELS_7             2
1441 #define  STM_ADC_CR2_DELS_15            3
1442 #define  STM_ADC_CR2_DELS_31            4
1443 #define  STM_ADC_CR2_DELS_63            5
1444 #define  STM_ADC_CR2_DELS_127           6
1445 #define  STM_ADC_CR2_DELS_255           7
1446 #define  STM_ADC_CR2_DELS_MASK          7
1447 #define STM_ADC_CR2_CONT        1
1448 #define STM_ADC_CR2_ADON        0
1449
1450 #define STM_ADC_CCR_TSVREFE     23
1451 #define STM_ADC_CCR_ADCPRE      16
1452 #define  STM_ADC_CCR_ADCPRE_HSI_1       0
1453 #define  STM_ADC_CCR_ADCPRE_HSI_2       1
1454 #define  STM_ADC_CCR_ADCPRE_HSI_4       2
1455 #define  STM_ADC_CCR_ADCPRE_MASK        3
1456
1457 struct stm_temp_cal {
1458         uint16_t        vref;
1459         uint16_t        ts_cal_cold;
1460         uint16_t        reserved;
1461         uint16_t        ts_cal_hot;
1462 };
1463
1464 extern struct stm_temp_cal      stm_temp_cal;
1465
1466 #define stm_temp_cal_cold       25
1467 #define stm_temp_cal_hot        110
1468
1469 #define STM_NUM_I2C     2
1470
1471 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1472
1473 struct stm_i2c {
1474         vuint32_t       cr1;
1475         vuint32_t       cr2;
1476         vuint32_t       oar1;
1477         vuint32_t       oar2;
1478         vuint32_t       dr;
1479         vuint32_t       sr1;
1480         vuint32_t       sr2;
1481         vuint32_t       ccr;
1482         vuint32_t       trise;
1483 };
1484
1485 extern struct stm_i2c stm_i2c1, stm_i2c2;
1486
1487 #define STM_I2C_CR1_SWRST       15
1488 #define STM_I2C_CR1_ALERT       13
1489 #define STM_I2C_CR1_PEC         12
1490 #define STM_I2C_CR1_POS         11
1491 #define STM_I2C_CR1_ACK         10
1492 #define STM_I2C_CR1_STOP        9
1493 #define STM_I2C_CR1_START       8
1494 #define STM_I2C_CR1_NOSTRETCH   7
1495 #define STM_I2C_CR1_ENGC        6
1496 #define STM_I2C_CR1_ENPEC       5
1497 #define STM_I2C_CR1_ENARP       4
1498 #define STM_I2C_CR1_SMBTYPE     3
1499 #define STM_I2C_CR1_SMBUS       1
1500 #define STM_I2C_CR1_PE          0
1501
1502 #define STM_I2C_CR2_LAST        12
1503 #define STM_I2C_CR2_DMAEN       11
1504 #define STM_I2C_CR2_ITBUFEN     10
1505 #define STM_I2C_CR2_ITEVTEN     9
1506 #define STM_I2C_CR2_ITERREN     8
1507 #define STM_I2C_CR2_FREQ        0
1508 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1509 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1510 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1511 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1512 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1513 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1514
1515 #define STM_I2C_SR1_SMBALERT    15
1516 #define STM_I2C_SR1_TIMEOUT     14
1517 #define STM_I2C_SR1_PECERR      12
1518 #define STM_I2C_SR1_OVR         11
1519 #define STM_I2C_SR1_AF          10
1520 #define STM_I2C_SR1_ARLO        9
1521 #define STM_I2C_SR1_BERR        8
1522 #define STM_I2C_SR1_TXE         7
1523 #define STM_I2C_SR1_RXNE        6
1524 #define STM_I2C_SR1_STOPF       4
1525 #define STM_I2C_SR1_ADD10       3
1526 #define STM_I2C_SR1_BTF         2
1527 #define STM_I2C_SR1_ADDR        1
1528 #define STM_I2C_SR1_SB          0
1529
1530 #define STM_I2C_SR2_PEC         8
1531 #define  STM_I2C_SR2_PEC_MASK   0xff00
1532 #define STM_I2C_SR2_DUALF       7
1533 #define STM_I2C_SR2_SMBHOST     6
1534 #define STM_I2C_SR2_SMBDEFAULT  5
1535 #define STM_I2C_SR2_GENCALL     4
1536 #define STM_I2C_SR2_TRA         2
1537 #define STM_I2C_SR2_BUSY        1
1538 #define STM_I2C_SR2_MSL         0
1539
1540 #define STM_I2C_CCR_FS          15
1541 #define STM_I2C_CCR_DUTY        14
1542 #define STM_I2C_CCR_CCR         0
1543 #define  STM_I2C_CCR_MASK       0x7ff
1544
1545 struct stm_tim234 {
1546         vuint32_t       cr1;
1547         vuint32_t       cr2;
1548         vuint32_t       smcr;
1549         vuint32_t       dier;
1550
1551         vuint32_t       sr;
1552         vuint32_t       egr;
1553         vuint32_t       ccmr1;
1554         vuint32_t       ccmr2;
1555
1556         vuint32_t       ccer;
1557         vuint32_t       cnt;
1558         vuint32_t       psc;
1559         vuint32_t       arr;
1560
1561         uint32_t        reserved_30;
1562         vuint32_t       ccr1;
1563         vuint32_t       ccr2;
1564         vuint32_t       ccr3;
1565
1566         vuint32_t       ccr4;
1567         uint32_t        reserved_44;
1568         vuint32_t       dcr;
1569         vuint32_t       dmar;
1570
1571         uint32_t        reserved_50;
1572 };
1573
1574 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1575
1576 #define STM_TIM234_CR1_CKD      8
1577 #define  STM_TIM234_CR1_CKD_1           0
1578 #define  STM_TIM234_CR1_CKD_2           1
1579 #define  STM_TIM234_CR1_CKD_4           2
1580 #define  STM_TIM234_CR1_CKD_MASK        3
1581 #define STM_TIM234_CR1_ARPE     7
1582 #define STM_TIM234_CR1_CMS      5
1583 #define  STM_TIM234_CR1_CMS_EDGE        0
1584 #define  STM_TIM234_CR1_CMS_CENTER_1    1
1585 #define  STM_TIM234_CR1_CMS_CENTER_2    2
1586 #define  STM_TIM234_CR1_CMS_CENTER_3    3
1587 #define  STM_TIM234_CR1_CMS_MASK        3
1588 #define STM_TIM234_CR1_DIR      4
1589 #define  STM_TIM234_CR1_DIR_UP          0
1590 #define  STM_TIM234_CR1_DIR_DOWN        1
1591 #define STM_TIM234_CR1_OPM      3
1592 #define STM_TIM234_CR1_URS      2
1593 #define STM_TIM234_CR1_UDIS     1
1594 #define STM_TIM234_CR1_CEN      0
1595
1596 #define STM_TIM234_CR2_TI1S     7
1597 #define STM_TIM234_CR2_MMS      4
1598 #define  STM_TIM234_CR2_MMS_RESET               0
1599 #define  STM_TIM234_CR2_MMS_ENABLE              1
1600 #define  STM_TIM234_CR2_MMS_UPDATE              2
1601 #define  STM_TIM234_CR2_MMS_COMPARE_PULSE       3
1602 #define  STM_TIM234_CR2_MMS_COMPARE_OC1REF      4
1603 #define  STM_TIM234_CR2_MMS_COMPARE_OC2REF      5
1604 #define  STM_TIM234_CR2_MMS_COMPARE_OC3REF      6
1605 #define  STM_TIM234_CR2_MMS_COMPARE_OC4REF      7
1606 #define  STM_TIM234_CR2_MMS_MASK                7
1607 #define STM_TIM234_CR2_CCDS     3
1608
1609 #define STM_TIM234_SMCR_ETP     15
1610 #define STM_TIM234_SMCR_ECE     14
1611 #define STM_TIM234_SMCR_ETPS    12
1612 #define  STM_TIM234_SMCR_ETPS_OFF               0
1613 #define  STM_TIM234_SMCR_ETPS_DIV_2             1
1614 #define  STM_TIM234_SMCR_ETPS_DIV_4             2
1615 #define  STM_TIM234_SMCR_ETPS_DIV_8             3
1616 #define  STM_TIM234_SMCR_ETPS_MASK              3
1617 #define STM_TIM234_SMCR_ETF     8
1618 #define  STM_TIM234_SMCR_ETF_NONE               0
1619 #define  STM_TIM234_SMCR_ETF_INT_N_2            1
1620 #define  STM_TIM234_SMCR_ETF_INT_N_4            2
1621 #define  STM_TIM234_SMCR_ETF_INT_N_8            3
1622 #define  STM_TIM234_SMCR_ETF_DTS_2_N_6          4
1623 #define  STM_TIM234_SMCR_ETF_DTS_2_N_8          5
1624 #define  STM_TIM234_SMCR_ETF_DTS_4_N_6          6
1625 #define  STM_TIM234_SMCR_ETF_DTS_4_N_8          7
1626 #define  STM_TIM234_SMCR_ETF_DTS_8_N_6          8
1627 #define  STM_TIM234_SMCR_ETF_DTS_8_N_8          9
1628 #define  STM_TIM234_SMCR_ETF_DTS_16_N_5         10
1629 #define  STM_TIM234_SMCR_ETF_DTS_16_N_6         11
1630 #define  STM_TIM234_SMCR_ETF_DTS_16_N_8         12
1631 #define  STM_TIM234_SMCR_ETF_DTS_32_N_5         13
1632 #define  STM_TIM234_SMCR_ETF_DTS_32_N_6         14
1633 #define  STM_TIM234_SMCR_ETF_DTS_32_N_8         15
1634 #define  STM_TIM234_SMCR_ETF_MASK               15
1635 #define STM_TIM234_SMCR_MSM     7
1636 #define STM_TIM234_SMCR_TS      4
1637 #define  STM_TIM234_SMCR_TS_ITR0                0
1638 #define  STM_TIM234_SMCR_TS_ITR1                1
1639 #define  STM_TIM234_SMCR_TS_ITR2                2
1640 #define  STM_TIM234_SMCR_TS_ITR3                3
1641 #define  STM_TIM234_SMCR_TS_TI1F_ED             4
1642 #define  STM_TIM234_SMCR_TS_TI1FP1              5
1643 #define  STM_TIM234_SMCR_TS_TI2FP2              6
1644 #define  STM_TIM234_SMCR_TS_ETRF                7
1645 #define  STM_TIM234_SMCR_TS_MASK                7
1646 #define STM_TIM234_SMCR_OCCS    3
1647 #define STM_TIM234_SMCR_SMS     0
1648 #define  STM_TIM234_SMCR_SMS_DISABLE            0
1649 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_1     1
1650 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_2     2
1651 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_3     3
1652 #define  STM_TIM234_SMCR_SMS_RESET_MODE         4
1653 #define  STM_TIM234_SMCR_SMS_GATED_MODE         5
1654 #define  STM_TIM234_SMCR_SMS_TRIGGER_MODE       6
1655 #define  STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK     7
1656 #define  STM_TIM234_SMCR_SMS_MASK               7
1657
1658 #define STM_TIM234_SR_CC4OF     12
1659 #define STM_TIM234_SR_CC3OF     11
1660 #define STM_TIM234_SR_CC2OF     10
1661 #define STM_TIM234_SR_CC1OF     9
1662 #define STM_TIM234_SR_TIF       6
1663 #define STM_TIM234_SR_CC4IF     4
1664 #define STM_TIM234_SR_CC3IF     3
1665 #define STM_TIM234_SR_CC2IF     2
1666 #define STM_TIM234_SR_CC1IF     1
1667 #define STM_TIM234_SR_UIF       0
1668
1669 #define STM_TIM234_EGR_TG       6
1670 #define STM_TIM234_EGR_CC4G     4
1671 #define STM_TIM234_EGR_CC3G     3
1672 #define STM_TIM234_EGR_CC2G     2
1673 #define STM_TIM234_EGR_CC1G     1
1674 #define STM_TIM234_EGR_UG       0
1675
1676 #define STM_TIM234_CCMR1_OC2CE  15
1677 #define STM_TIM234_CCMR1_OC2M   12
1678 #define  STM_TIM234_CCMR1_OC2M_FROZEN                   0
1679 #define  STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH        1
1680 #define  STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH         2
1681 #define  STM_TIM234_CCMR1_OC2M_TOGGLE                   3
1682 #define  STM_TIM234_CCMR1_OC2M_FORCE_LOW                4
1683 #define  STM_TIM234_CCMR1_OC2M_FORCE_HIGH               5
1684 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_1               6
1685 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_2               7
1686 #define  STM_TIM234_CCMR1_OC2M_MASK                     7
1687 #define STM_TIM234_CCMR1_OC2PE  11
1688 #define STM_TIM234_CCMR1_OC2FE  10
1689 #define STM_TIM234_CCMR1_CC2S   8
1690 #define  STM_TIM234_CCMR1_CC2S_OUTPUT                   0
1691 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI2                1
1692 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI1                2
1693 #define  STM_TIM234_CCMR1_CC2S_INPUT_TRC                3
1694 #define  STM_TIM234_CCMR1_CC2S_MASK                     3
1695
1696 #define STM_TIM234_CCMR1_OC1CE  7
1697 #define STM_TIM234_CCMR1_OC1M   4
1698 #define  STM_TIM234_CCMR1_OC1M_FROZEN                   0
1699 #define  STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH        1
1700 #define  STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH         2
1701 #define  STM_TIM234_CCMR1_OC1M_TOGGLE                   3
1702 #define  STM_TIM234_CCMR1_OC1M_FORCE_LOW                4
1703 #define  STM_TIM234_CCMR1_OC1M_FORCE_HIGH               5
1704 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_1               6
1705 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_2               7
1706 #define  STM_TIM234_CCMR1_OC1M_MASK                     7
1707 #define STM_TIM234_CCMR1_OC1PE  11
1708 #define STM_TIM234_CCMR1_OC1FE  2
1709 #define STM_TIM234_CCMR1_CC1S   0
1710 #define  STM_TIM234_CCMR1_CC1S_OUTPUT                   0
1711 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI1                1
1712 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI2                2
1713 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC                3
1714 #define  STM_TIM234_CCMR1_CC1S_MASK                     3
1715
1716 #define STM_TIM234_CCMR2_OC2CE  15
1717 #define STM_TIM234_CCMR2_OC4M   12
1718 #define  STM_TIM234_CCMR2_OC4M_FROZEN                   0
1719 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
1720 #define  STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH         2
1721 #define  STM_TIM234_CCMR2_OC4M_TOGGLE                   3
1722 #define  STM_TIM234_CCMR2_OC4M_FORCE_LOW                4
1723 #define  STM_TIM234_CCMR2_OC4M_FORCE_HIGH               5
1724 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_1               6
1725 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_2               7
1726 #define  STM_TIM234_CCMR2_OC4M_MASK                     7
1727 #define STM_TIM234_CCMR2_OC4PE  11
1728 #define STM_TIM234_CCMR2_OC4FE  10
1729 #define STM_TIM234_CCMR2_CC4S   8
1730 #define  STM_TIM234_CCMR2_CC4S_OUTPUT                   0
1731 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI4                1
1732 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI3                2
1733 #define  STM_TIM234_CCMR2_CC4S_INPUT_TRC                3
1734 #define  STM_TIM234_CCMR2_CC4S_MASK                     3
1735
1736 #define STM_TIM234_CCMR2_OC3CE  7
1737 #define STM_TIM234_CCMR2_OC3M   4
1738 #define  STM_TIM234_CCMR2_OC3M_FROZEN                   0
1739 #define  STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH        1
1740 #define  STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH         2
1741 #define  STM_TIM234_CCMR2_OC3M_TOGGLE                   3
1742 #define  STM_TIM234_CCMR2_OC3M_FORCE_LOW                4
1743 #define  STM_TIM234_CCMR2_OC3M_FORCE_HIGH               5
1744 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_1               6
1745 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_2               7
1746 #define  STM_TIM234_CCMR2_OC3M_MASK                     7
1747 #define STM_TIM234_CCMR2_OC3PE  11
1748 #define STM_TIM234_CCMR2_OC3FE  2
1749 #define STM_TIM234_CCMR2_CC3S   0
1750 #define  STM_TIM234_CCMR2_CC3S_OUTPUT                   0
1751 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI3                1
1752 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI4                2
1753 #define  STM_TIM234_CCMR2_CC3S_INPUT_TRC                3
1754 #define  STM_TIM234_CCMR2_CC3S_MASK                     3
1755
1756 #define STM_TIM234_CCER_CC4NP   15
1757 #define STM_TIM234_CCER_CC4P    13
1758 #define STM_TIM234_CCER_CC4E    12
1759 #define STM_TIM234_CCER_CC3NP   11
1760 #define STM_TIM234_CCER_CC3P    9
1761 #define STM_TIM234_CCER_CC3E    8
1762 #define STM_TIM234_CCER_CC2NP   7
1763 #define STM_TIM234_CCER_CC2P    5
1764 #define STM_TIM234_CCER_CC2E    4
1765 #define STM_TIM234_CCER_CC1NP   3
1766 #define STM_TIM234_CCER_CC1P    1
1767 #define STM_TIM234_CCER_CC1E    0
1768
1769 struct stm_usb {
1770         vuint32_t       epr[8];
1771         uint8_t         reserved_20[0x40 - 0x20];
1772         vuint32_t       cntr;
1773         vuint32_t       istr;
1774         vuint32_t       fnr;
1775         vuint32_t       daddr;
1776         vuint32_t       btable;
1777 };
1778
1779 #define STM_USB_EPR_CTR_RX      15
1780 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1781 #define STM_USB_EPR_DTOG_RX     14
1782 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1783 #define STM_USB_EPR_STAT_RX     12
1784 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1785 #define  STM_USB_EPR_STAT_RX_STALL                      1
1786 #define  STM_USB_EPR_STAT_RX_NAK                        2
1787 #define  STM_USB_EPR_STAT_RX_VALID                      3
1788 #define  STM_USB_EPR_STAT_RX_MASK                       3
1789 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1790 #define STM_USB_EPR_SETUP       11
1791 #define STM_USB_EPR_EP_TYPE     9
1792 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1793 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1794 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1795 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1796 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1797 #define STM_USB_EPR_EP_KIND     8
1798 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1799 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1800 #define STM_USB_EPR_CTR_TX      7
1801 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1802 #define STM_USB_EPR_DTOG_TX     6
1803 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1804 #define STM_USB_EPR_STAT_TX     4
1805 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1806 #define  STM_USB_EPR_STAT_TX_STALL                      1
1807 #define  STM_USB_EPR_STAT_TX_NAK                        2
1808 #define  STM_USB_EPR_STAT_TX_VALID                      3
1809 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1810 #define  STM_USB_EPR_STAT_TX_MASK                       3
1811 #define STM_USB_EPR_EA          0
1812 #define  STM_USB_EPR_EA_MASK                            0xf
1813
1814 #define STM_USB_CNTR_CTRM       15
1815 #define STM_USB_CNTR_PMAOVRM    14
1816 #define STM_USB_CNTR_ERRM       13
1817 #define STM_USB_CNTR_WKUPM      12
1818 #define STM_USB_CNTR_SUSPM      11
1819 #define STM_USB_CNTR_RESETM     10
1820 #define STM_USB_CNTR_SOFM       9
1821 #define STM_USB_CNTR_ESOFM      8
1822 #define STM_USB_CNTR_RESUME     4
1823 #define STM_USB_CNTR_FSUSP      3
1824 #define STM_USB_CNTR_LP_MODE    2
1825 #define STM_USB_CNTR_PDWN       1
1826 #define STM_USB_CNTR_FRES       0
1827
1828 #define STM_USB_ISTR_CTR        15
1829 #define STM_USB_ISTR_PMAOVR     14
1830 #define STM_USB_ISTR_ERR        13
1831 #define STM_USB_ISTR_WKUP       12
1832 #define STM_USB_ISTR_SUSP       11
1833 #define STM_USB_ISTR_RESET      10
1834 #define STM_USB_ISTR_SOF        9
1835 #define STM_USB_ISTR_ESOF       8
1836 #define STM_USB_ISTR_DIR        4
1837 #define STM_USB_ISTR_EP_ID      0
1838 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1839
1840 #define STM_USB_FNR_RXDP        15
1841 #define STM_USB_FNR_RXDM        14
1842 #define STM_USB_FNR_LCK         13
1843 #define STM_USB_FNR_LSOF        11
1844 #define  STM_USB_FNR_LSOF_MASK                  0x3
1845 #define STM_USB_FNR_FN          0
1846 #define  STM_USB_FNR_FN_MASK                    0x7ff
1847
1848 #define STM_USB_DADDR_EF        7
1849 #define STM_USB_DADDR_ADD       0
1850 #define  STM_USB_DADDR_ADD_MASK                 0x7f
1851
1852 extern struct stm_usb stm_usb;
1853
1854 union stm_usb_bdt {
1855         struct {
1856                 vuint32_t       addr_tx;
1857                 vuint32_t       count_tx;
1858                 vuint32_t       addr_rx;
1859                 vuint32_t       count_rx;
1860         } single;
1861         struct {
1862                 vuint32_t       addr;
1863                 vuint32_t       count;
1864         } double_tx[2];
1865         struct {
1866                 vuint32_t       addr;
1867                 vuint32_t       count;
1868         } double_rx[2];
1869 };
1870
1871 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
1872 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
1873 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
1874 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
1875 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
1876
1877 #define STM_USB_BDT_SIZE        8
1878
1879 extern uint8_t stm_usb_sram[];
1880
1881 struct stm_exti {
1882         vuint32_t       imr;
1883         vuint32_t       emr;
1884         vuint32_t       rtsr;
1885         vuint32_t       ftsr;
1886
1887         vuint32_t       swier;
1888         vuint32_t       pr;
1889 };
1890
1891 extern struct stm_exti stm_exti;
1892
1893 #endif /* _STM32L_H_ */