2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 static volatile __data uint16_t ao_tick_count;
22 uint16_t ao_time(void)
31 static __xdata uint8_t ao_forever;
34 ao_delay(uint16_t ticks)
37 ao_sleep(&ao_forever);
40 #define T2_CLOCK_DIVISOR 8 /* 24e6/8 = 3e6 */
41 #define T2_SAMPLE_TIME 30000 /* 3e6/30000 = 100 */
44 volatile __data uint8_t ao_adc_interval = 1;
45 volatile __data uint8_t ao_adc_count;
56 if (++ao_adc_count == ao_adc_interval) {
65 ao_timer_set_adc_interval(uint8_t interval) __critical
67 ao_adc_interval = interval;
82 /* Set flash latency to tolerate 32MHz SYSCLK -> 1 wait state */
83 uint32_t acr = STM_FLASH->acr;
85 /* Enable 64-bit access and prefetch */
86 acr |= (1 << STM_FLASH_ACR_ACC64) | (1 << STM_FLASH_ACR_PRFEN);
89 /* Enable 1 wait state so the CPU can run at 32MHz */
90 acr |= (1 << STM_FLASH_ACR_LATENCY);
93 /* Enable HSI RC clock 16MHz */
94 if (!(STM_RCC->cr & (1 << STM_RCC_CR_HSIRDY))) {
95 STM_RCC->cr |= (1 << STM_RCC_CR_HSION);
96 while (!(STM_RCC->cr & (1 << STM_RCC_CR_HSIRDY)))
100 /* Switch to direct HSI for SYSCLK */
101 if ((STM_RCC->cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
102 (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS)) {
103 cfgr = STM_RCC->cfgr;
104 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
105 cfgr |= (STM_RCC_CFGR_SW_HSI << STM_RCC_CFGR_SW);
106 STM_RCC->cfgr = cfgr;
107 while ((STM_RCC->cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
108 (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS))
112 /* Disable the PLL */
113 STM_RCC->cr &= ~(1 << STM_RCC_CR_PLLON);
114 while (STM_RCC->cr & (1 << STM_RCC_CR_PLLRDY))
117 /* PLLVCO to 96MHz (for USB) -> PLLMUL = 6 */
118 cfgr = STM_RCC->cfgr;
119 cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
120 cfgr |= (STM_RCC_CFGR_PLLMUL_6 << STM_RCC_CFGR_PLLMUL);
122 /* SYSCLK to 32MHz from PLL clock -> PLLDIV = /3 */
123 cfgr &= ~(STM_RCC_CFGR_PLLDIV_MASK << STM_RCC_CFGR_PLLDIV);
124 cfgr |= (STM_RCC_CFGR_PLLDIV_3 << STM_RCC_CFGR_PLLDIV);
126 /* PLL source to HSI */
127 cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
129 STM_RCC->cfgr = cfgr;
131 /* Enable the PLL and wait for it */
132 STM_RCC->cr |= (1 << STM_RCC_CR_PLLON);
133 while (!(STM_RCC->cr & (1 << STM_RCC_CR_PLLRDY)))
136 /* Switch to the PLL for the system clock */
138 cfgr = STM_RCC->cfgr;
139 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
140 cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
141 STM_RCC->cfgr = cfgr;
142 while ((STM_RCC->cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
143 (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS))
146 /* HCLK to 32MHz -> AHB prescaler = /1 */
147 cfgr = STM_RCC->cfgr;
148 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
149 cfgr |= (STM_RCC_CFGR_HPRE_DIV_1 << STM_RCC_CFGR_HPRE);
150 STM_RCC->cfgr = cfgr;
151 while ((STM_RCC->cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
152 (STM_RCC_CFGR_HPRE_DIV_1 << STM_RCC_CFGR_HPRE))
155 /* PCLK1 to 16MHz -> APB1 Prescaler = 2 */
156 cfgr = STM_RCC->cfgr;
157 cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
158 cfgr |= (STM_RCC_CFGR_PPRE1_DIV_2 << STM_RCC_CFGR_PPRE1);
159 STM_RCC->cfgr = cfgr;
161 /* PCLK2 to 16MHz -> APB2 Prescaler = 2 */
162 cfgr = STM_RCC->cfgr;
163 cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
164 cfgr |= (STM_RCC_CFGR_PPRE2_DIV_2 << STM_RCC_CFGR_PPRE2);
165 STM_RCC->cfgr = cfgr;