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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19
  20 struct ao_spi_stm_info {
  21         uint8_t miso_dma_index;
  22         uint8_t mosi_dma_index;
  23         struct stm_spi *stm_spi;
  24 };
  25
  26 uint8_t ao_spi_mutex[STM_NUM_SPI];
  27
  28 static const struct ao_spi_stm_info ao_spi_stm_info[STM_NUM_SPI] = {
  29         {
  30                 .miso_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI1_RX),
  31                 .mosi_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI1_TX),
  32                 &stm_spi1
  33         },
  34         {
  35                 .miso_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI2_RX),
  36                 .mosi_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI2_TX),
  37                 &stm_spi2
  38         }
  39 };
  40
  41 static uint8_t  spi_dev_null;
  42
  43 void
  44 ao_spi_send(void *block, uint16_t len, uint8_t spi_index)
  45 {
  46         struct stm_spi *stm_spi = ao_spi_stm_info[spi_index].stm_spi;
  47         uint8_t mosi_dma_index = ao_spi_stm_info[spi_index].mosi_dma_index;
  48         uint8_t miso_dma_index = ao_spi_stm_info[spi_index].miso_dma_index;
  49
  50         /* Set up the transmit DMA to deliver data */
  51         ao_dma_set_transfer(mosi_dma_index,
  52                             &stm_spi->dr,
  53                             block,
  54                             len,
  55                             (0 << STM_DMA_CCR_MEM2MEM) |
  56                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
  57                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
  58                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
  59                             (1 << STM_DMA_CCR_MINC) |
  60                             (0 << STM_DMA_CCR_PINC) |
  61                             (0 << STM_DMA_CCR_CIRC) |
  62                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
  63
  64         /* Clear RXNE */
  65         (void) stm_spi->dr;
  66
  67         /* Set up the receive DMA -- when this is done, we know the SPI unit
  68          * is idle. Without this, we'd have to poll waiting for the BSY bit to
  69          * be cleared
  70          */
  71         ao_dma_set_transfer(miso_dma_index,
  72                             &stm_spi->dr,
  73                             &spi_dev_null,
  74                             len,
  75                             (0 << STM_DMA_CCR_MEM2MEM) |
  76                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
  77                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
  78                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
  79                             (0 << STM_DMA_CCR_MINC) |
  80                             (0 << STM_DMA_CCR_PINC) |
  81                             (0 << STM_DMA_CCR_CIRC) |
  82                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  83         stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
  84                         (0 << STM_SPI_CR2_RXNEIE) |
  85                         (0 << STM_SPI_CR2_ERRIE) |
  86                         (0 << STM_SPI_CR2_SSOE) |
  87                         (1 << STM_SPI_CR2_TXDMAEN) |
  88                         (1 << STM_SPI_CR2_RXDMAEN));
  89         ao_dma_start(miso_dma_index);
  90         ao_dma_start(mosi_dma_index);
  91         ao_arch_critical(
  92                 while (!ao_dma_done[miso_dma_index])
  93                         ao_sleep(&ao_dma_done[miso_dma_index]);
  94                 );
  95         ao_dma_done_transfer(mosi_dma_index);
  96         ao_dma_done_transfer(miso_dma_index);
  97 }
  98
  99 void
 100 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index)
 101 {
 102         struct stm_spi *stm_spi = ao_spi_stm_info[spi_index].stm_spi;
 103         uint8_t mosi_dma_index = ao_spi_stm_info[spi_index].mosi_dma_index;
 104         uint8_t miso_dma_index = ao_spi_stm_info[spi_index].miso_dma_index;
 105
 106         /* Set up transmit DMA to make the SPI hardware actually run */
 107         ao_dma_set_transfer(mosi_dma_index,
 108                             &stm_spi->dr,
 109                             &spi_dev_null,
 110                             len,
 111                             (0 << STM_DMA_CCR_MEM2MEM) |
 112                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 113                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 114                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 115                             (0 << STM_DMA_CCR_MINC) |
 116                             (0 << STM_DMA_CCR_PINC) |
 117                             (0 << STM_DMA_CCR_CIRC) |
 118                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 119
 120         /* Clear RXNE */
 121         (void) stm_spi->dr;
 122
 123         /* Set up the receive DMA to capture data */
 124         ao_dma_set_transfer(miso_dma_index,
 125                             &stm_spi->dr,
 126                             block,
 127                             len,
 128                             (0 << STM_DMA_CCR_MEM2MEM) |
 129                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 130                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 131                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 132                             (1 << STM_DMA_CCR_MINC) |
 133                             (0 << STM_DMA_CCR_PINC) |
 134                             (0 << STM_DMA_CCR_CIRC) |
 135                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 136
 137         stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
 138                         (0 << STM_SPI_CR2_RXNEIE) |
 139                         (0 << STM_SPI_CR2_ERRIE) |
 140                         (0 << STM_SPI_CR2_SSOE) |
 141                         (1 << STM_SPI_CR2_TXDMAEN) |
 142                         (1 << STM_SPI_CR2_RXDMAEN));
 143         ao_dma_start(miso_dma_index);
 144         ao_dma_start(mosi_dma_index);
 145
 146         /* Wait until the SPI unit is done */
 147         ao_arch_critical(
 148                 while (!ao_dma_done[miso_dma_index])
 149                         ao_sleep(&ao_dma_done[miso_dma_index]);
 150                 );
 151
 152         ao_dma_done_transfer(mosi_dma_index);
 153         ao_dma_done_transfer(miso_dma_index);
 154 }
 155
 156 void
 157 ao_spi_get(uint8_t spi_index)
 158 {
 159         struct stm_spi  *stm_spi = ao_spi_stm_info[spi_index].stm_spi;
 160
 161         ao_mutex_get(&ao_spi_mutex[spi_index]);
 162         stm_spi->cr1 = ((0 << STM_SPI_CR1_BIDIMODE) |                   /* Three wire mode */
 163                         (0 << STM_SPI_CR1_BIDIOE) |
 164                         (0 << STM_SPI_CR1_CRCEN) |                      /* CRC disabled */
 165                         (0 << STM_SPI_CR1_CRCNEXT) |
 166                         (0 << STM_SPI_CR1_DFF) |
 167                         (0 << STM_SPI_CR1_RXONLY) |
 168                         (1 << STM_SPI_CR1_SSM) |                        /* Software SS handling */
 169                         (1 << STM_SPI_CR1_SSI) |                        /*  ... */
 170                         (0 << STM_SPI_CR1_LSBFIRST) |                   /* Little endian */
 171                         (1 << STM_SPI_CR1_SPE) |                        /* Enable SPI unit */
 172                         (STM_SPI_CR1_BR_PCLK_4 << STM_SPI_CR1_BR) |     /* baud rate to pclk/4 */
 173                         (1 << STM_SPI_CR1_MSTR) |
 174                         (0 << STM_SPI_CR1_CPOL) |                       /* Format 0 */
 175                         (0 << STM_SPI_CR1_CPHA));
 176 }
 177
 178 void
 179 ao_spi_put(uint8_t spi_index)
 180 {
 181         struct stm_spi  *stm_spi = ao_spi_stm_info[spi_index].stm_spi;
 182
 183         stm_spi->cr1 = 0;
 184         ao_mutex_put(&ao_spi_mutex[spi_index]);
 185 }
 186
 187 static void
 188 ao_spi_channel_init(uint8_t spi_index)
 189 {
 190         struct stm_spi  *stm_spi = ao_spi_stm_info[spi_index].stm_spi;
 191
 192         stm_spi->cr1 = 0;
 193         (void) stm_spi->sr;
 194         stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
 195                         (0 << STM_SPI_CR2_RXNEIE) |
 196                         (0 << STM_SPI_CR2_ERRIE) |
 197                         (0 << STM_SPI_CR2_SSOE) |
 198                         (0 << STM_SPI_CR2_TXDMAEN) |
 199                         (0 << STM_SPI_CR2_RXDMAEN));
 200 }
 201
 202 void
 203 ao_spi_init(void)
 204 {
 205 #if HAS_SPI_1
 206 # if SPI_1_PA5_PA6_PA7
 207         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
 208         stm_afr_set(&stm_gpioa, 5, STM_AFR_AF5);
 209         stm_afr_set(&stm_gpioa, 6, STM_AFR_AF5);
 210         stm_afr_set(&stm_gpioa, 7, STM_AFR_AF5);
 211 # else
 212 #  if SPI_1_PB3_PB4_PB5
 213         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
 214         stm_afr_set(&stm_gpiob, 3, STM_AFR_AF5);
 215         stm_afr_set(&stm_gpiob, 4, STM_AFR_AF5);
 216         stm_afr_set(&stm_gpiob, 5, STM_AFR_AF5);
 217 #  else
 218 #   if SPI_1_PE13_PE14_PE15
 219         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN);
 220         stm_afr_set(&stm_gpioe, 13, STM_AFR_AF5);
 221         stm_afr_set(&stm_gpioe, 14, STM_AFR_AF5);
 222         stm_afr_set(&stm_gpioe, 15, STM_AFR_AF5);
 223 #   else
 224 #    error "No SPI_1 port configuration specified"
 225 #   endif
 226 #  endif
 227 # endif
 228
 229         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SPI1EN);
 230
 231         ao_spi_channel_init(0);
 232
 233         stm_nvic_set_enable(STM_ISR_SPI1_POS);
 234         stm_nvic_set_priority(STM_ISR_SPI1_POS, 3);
 235 #endif
 236
 237 #if HAS_SPI_2
 238 # if SPI_2_PB13_PB14_PB15
 239         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
 240         stm_afr_set(&stm_gpiob, 13, STM_AFR_AF5);
 241         stm_afr_set(&stm_gpiob, 14, STM_AFR_AF5);
 242         stm_afr_set(&stm_gpiob, 15, STM_AFR_AF5);
 243 # else
 244 #  if SPI_2_PPD1_PD3_PD4
 245         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN);
 246         stm_afr_set(&stm_gpiod, 1, STM_AFR_AF5);
 247         stm_afr_set(&stm_gpiod, 3, STM_AFR_AF5);
 248         stm_afr_set(&stm_gpiod, 4, STM_AFR_AF5);
 249 #  else
 250 #   error "No SPI_2 port configuration specified"
 251 #  endif
 252 # endif
 253
 254         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_SPI2EN);
 255
 256         ao_spi_channel_init(1);
 257
 258         stm_nvic_set_enable(STM_ISR_SPI2_POS);
 259         stm_nvic_set_priority(STM_ISR_SPI2_POS, 3);
 260 #endif
 261 }