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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19
  20 struct ao_spi_stm_info {
  21         uint8_t miso_dma_index;
  22         uint8_t mosi_dma_index;
  23         struct stm_spi *stm_spi;
  24 };
  25
  26 static uint8_t          ao_spi_mutex[STM_NUM_SPI];
  27 static uint8_t          ao_spi_index[STM_NUM_SPI];
  28
  29 static const struct ao_spi_stm_info ao_spi_stm_info[STM_NUM_SPI] = {
  30         {
  31                 .miso_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI1_RX),
  32                 .mosi_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI1_TX),
  33                 &stm_spi1
  34         },
  35         {
  36                 .miso_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI2_RX),
  37                 .mosi_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI2_TX),
  38                 &stm_spi2
  39         }
  40 };
  41
  42 static uint8_t  spi_dev_null;
  43
  44 void
  45 ao_spi_send(void *block, uint16_t len, uint8_t spi_index)
  46 {
  47         struct stm_spi *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
  48         uint8_t mosi_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].mosi_dma_index;
  49         uint8_t miso_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].miso_dma_index;
  50
  51         /* Set up the transmit DMA to deliver data */
  52         ao_dma_set_transfer(mosi_dma_index,
  53                             &stm_spi->dr,
  54                             block,
  55                             len,
  56                             (0 << STM_DMA_CCR_MEM2MEM) |
  57                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
  58                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
  59                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
  60                             (1 << STM_DMA_CCR_MINC) |
  61                             (0 << STM_DMA_CCR_PINC) |
  62                             (0 << STM_DMA_CCR_CIRC) |
  63                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
  64
  65         /* Clear RXNE */
  66         (void) stm_spi->dr;
  67
  68         /* Set up the receive DMA -- when this is done, we know the SPI unit
  69          * is idle. Without this, we'd have to poll waiting for the BSY bit to
  70          * be cleared
  71          */
  72         ao_dma_set_transfer(miso_dma_index,
  73                             &stm_spi->dr,
  74                             &spi_dev_null,
  75                             len,
  76                             (0 << STM_DMA_CCR_MEM2MEM) |
  77                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
  78                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
  79                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
  80                             (0 << STM_DMA_CCR_MINC) |
  81                             (0 << STM_DMA_CCR_PINC) |
  82                             (0 << STM_DMA_CCR_CIRC) |
  83                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  84         stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
  85                         (0 << STM_SPI_CR2_RXNEIE) |
  86                         (0 << STM_SPI_CR2_ERRIE) |
  87                         (0 << STM_SPI_CR2_SSOE) |
  88                         (1 << STM_SPI_CR2_TXDMAEN) |
  89                         (1 << STM_SPI_CR2_RXDMAEN));
  90         ao_dma_start(miso_dma_index);
  91         ao_dma_start(mosi_dma_index);
  92         ao_arch_critical(
  93                 while (!ao_dma_done[miso_dma_index])
  94                         ao_sleep(&ao_dma_done[miso_dma_index]);
  95                 );
  96         ao_dma_done_transfer(mosi_dma_index);
  97         ao_dma_done_transfer(miso_dma_index);
  98 }
  99
 100 void
 101 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index)
 102 {
 103         struct stm_spi *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
 104         uint8_t mosi_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].mosi_dma_index;
 105         uint8_t miso_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].miso_dma_index;
 106
 107         /* Set up the transmit DMA to deliver data */
 108         ao_dma_set_transfer(mosi_dma_index,
 109                             &stm_spi->dr,
 110                             &value,
 111                             len,
 112                             (0 << STM_DMA_CCR_MEM2MEM) |
 113                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 114                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 115                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 116                             (0 << STM_DMA_CCR_MINC) |
 117                             (0 << STM_DMA_CCR_PINC) |
 118                             (0 << STM_DMA_CCR_CIRC) |
 119                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 120
 121         /* Clear RXNE */
 122         (void) stm_spi->dr;
 123
 124         /* Set up the receive DMA -- when this is done, we know the SPI unit
 125          * is idle. Without this, we'd have to poll waiting for the BSY bit to
 126          * be cleared
 127          */
 128         ao_dma_set_transfer(miso_dma_index,
 129                             &stm_spi->dr,
 130                             &spi_dev_null,
 131                             len,
 132                             (0 << STM_DMA_CCR_MEM2MEM) |
 133                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 134                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 135                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 136                             (0 << STM_DMA_CCR_MINC) |
 137                             (0 << STM_DMA_CCR_PINC) |
 138                             (0 << STM_DMA_CCR_CIRC) |
 139                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 140         stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
 141                         (0 << STM_SPI_CR2_RXNEIE) |
 142                         (0 << STM_SPI_CR2_ERRIE) |
 143                         (0 << STM_SPI_CR2_SSOE) |
 144                         (1 << STM_SPI_CR2_TXDMAEN) |
 145                         (1 << STM_SPI_CR2_RXDMAEN));
 146         ao_dma_start(miso_dma_index);
 147         ao_dma_start(mosi_dma_index);
 148         ao_arch_critical(
 149                 while (!ao_dma_done[miso_dma_index])
 150                         ao_sleep(&ao_dma_done[miso_dma_index]);
 151                 );
 152         ao_dma_done_transfer(mosi_dma_index);
 153         ao_dma_done_transfer(miso_dma_index);
 154 }
 155
 156 void
 157 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index)
 158 {
 159         struct stm_spi *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
 160         uint8_t mosi_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].mosi_dma_index;
 161         uint8_t miso_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].miso_dma_index;
 162
 163         spi_dev_null = 0xff;
 164
 165         /* Set up transmit DMA to make the SPI hardware actually run */
 166         ao_dma_set_transfer(mosi_dma_index,
 167                             &stm_spi->dr,
 168                             &spi_dev_null,
 169                             len,
 170                             (0 << STM_DMA_CCR_MEM2MEM) |
 171                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 172                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 173                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 174                             (0 << STM_DMA_CCR_MINC) |
 175                             (0 << STM_DMA_CCR_PINC) |
 176                             (0 << STM_DMA_CCR_CIRC) |
 177                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 178
 179         /* Clear RXNE */
 180         (void) stm_spi->dr;
 181
 182         /* Set up the receive DMA to capture data */
 183         ao_dma_set_transfer(miso_dma_index,
 184                             &stm_spi->dr,
 185                             block,
 186                             len,
 187                             (0 << STM_DMA_CCR_MEM2MEM) |
 188                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 189                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 190                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 191                             (1 << STM_DMA_CCR_MINC) |
 192                             (0 << STM_DMA_CCR_PINC) |
 193                             (0 << STM_DMA_CCR_CIRC) |
 194                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 195
 196         stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
 197                         (0 << STM_SPI_CR2_RXNEIE) |
 198                         (0 << STM_SPI_CR2_ERRIE) |
 199                         (0 << STM_SPI_CR2_SSOE) |
 200                         (1 << STM_SPI_CR2_TXDMAEN) |
 201                         (1 << STM_SPI_CR2_RXDMAEN));
 202         ao_dma_start(miso_dma_index);
 203         ao_dma_start(mosi_dma_index);
 204
 205         /* Wait until the SPI unit is done */
 206         ao_arch_critical(
 207                 while (!ao_dma_done[miso_dma_index])
 208                         ao_sleep(&ao_dma_done[miso_dma_index]);
 209                 );
 210
 211         ao_dma_done_transfer(mosi_dma_index);
 212         ao_dma_done_transfer(miso_dma_index);
 213 }
 214
 215 void
 216 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index)
 217 {
 218         struct stm_spi *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
 219         uint8_t mosi_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].mosi_dma_index;
 220         uint8_t miso_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].miso_dma_index;
 221
 222         /* Set up transmit DMA to send data */
 223         ao_dma_set_transfer(mosi_dma_index,
 224                             &stm_spi->dr,
 225                             out,
 226                             len,
 227                             (0 << STM_DMA_CCR_MEM2MEM) |
 228                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 229                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 230                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 231                             (1 << STM_DMA_CCR_MINC) |
 232                             (0 << STM_DMA_CCR_PINC) |
 233                             (0 << STM_DMA_CCR_CIRC) |
 234                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 235
 236         /* Clear RXNE */
 237         (void) stm_spi->dr;
 238
 239         /* Set up the receive DMA to capture data */
 240         ao_dma_set_transfer(miso_dma_index,
 241                             &stm_spi->dr,
 242                             in,
 243                             len,
 244                             (0 << STM_DMA_CCR_MEM2MEM) |
 245                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 246                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 247                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 248                             (1 << STM_DMA_CCR_MINC) |
 249                             (0 << STM_DMA_CCR_PINC) |
 250                             (0 << STM_DMA_CCR_CIRC) |
 251                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 252
 253         stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
 254                         (0 << STM_SPI_CR2_RXNEIE) |
 255                         (0 << STM_SPI_CR2_ERRIE) |
 256                         (0 << STM_SPI_CR2_SSOE) |
 257                         (1 << STM_SPI_CR2_TXDMAEN) |
 258                         (1 << STM_SPI_CR2_RXDMAEN));
 259         ao_dma_start(miso_dma_index);
 260         ao_dma_start(mosi_dma_index);
 261
 262         /* Wait until the SPI unit is done */
 263         ao_arch_critical(
 264                 while (!ao_dma_done[miso_dma_index])
 265                         ao_sleep(&ao_dma_done[miso_dma_index]);
 266                 );
 267
 268         ao_dma_done_transfer(mosi_dma_index);
 269         ao_dma_done_transfer(miso_dma_index);
 270 }
 271
 272 static void
 273 ao_spi_disable_index(uint8_t spi_index)
 274 {
 275         /* Disable current config
 276          */
 277         switch (AO_SPI_INDEX(spi_index)) {
 278         case STM_SPI_INDEX(1):
 279                 switch (spi_index) {
 280                 case AO_SPI_1_PA5_PA6_PA7:
 281                         stm_gpio_set(&stm_gpioa, 5, 1);
 282                         stm_moder_set(&stm_gpioa, 5, STM_MODER_OUTPUT);
 283                         stm_moder_set(&stm_gpioa, 6, STM_MODER_INPUT);
 284                         stm_moder_set(&stm_gpioa, 7, STM_MODER_OUTPUT);
 285                         break;
 286                 case AO_SPI_1_PB3_PB4_PB5:
 287                         stm_gpio_set(&stm_gpiob, 3, 1);
 288                         stm_moder_set(&stm_gpiob, 3, STM_MODER_OUTPUT);
 289                         stm_moder_set(&stm_gpiob, 4, STM_MODER_INPUT);
 290                         stm_moder_set(&stm_gpiob, 5, STM_MODER_OUTPUT);
 291                         break;
 292                 case AO_SPI_1_PE13_PE14_PE15:
 293                         stm_gpio_set(&stm_gpioe, 13, 1);
 294                         stm_moder_set(&stm_gpioe, 13, STM_MODER_OUTPUT);
 295                         stm_moder_set(&stm_gpioe, 14, STM_MODER_INPUT);
 296                         stm_moder_set(&stm_gpioe, 15, STM_MODER_OUTPUT);
 297                         break;
 298                 }
 299                 break;
 300         case STM_SPI_INDEX(2):
 301                 switch (spi_index) {
 302                 case AO_SPI_2_PB13_PB14_PB15:
 303                         stm_gpio_set(&stm_gpiob, 13, 1);
 304                         stm_moder_set(&stm_gpiob, 13, STM_MODER_OUTPUT);
 305                         stm_moder_set(&stm_gpiob, 14, STM_MODER_INPUT);
 306                         stm_moder_set(&stm_gpiob, 15, STM_MODER_OUTPUT);
 307                         break;
 308                 case AO_SPI_2_PD1_PD3_PD4:
 309                         stm_gpio_set(&stm_gpiod, 1, 1);
 310                         stm_moder_set(&stm_gpiod, 1, STM_MODER_OUTPUT);
 311                         stm_moder_set(&stm_gpiod, 3, STM_MODER_INPUT);
 312                         stm_moder_set(&stm_gpiod, 4, STM_MODER_OUTPUT);
 313                         break;
 314                 }
 315                 break;
 316         }
 317 }
 318
 319 static void
 320 ao_spi_enable_index(uint8_t spi_index)
 321 {
 322         switch (AO_SPI_INDEX(spi_index)) {
 323         case STM_SPI_INDEX(1):
 324                 switch (spi_index) {
 325                 case AO_SPI_1_PA5_PA6_PA7:
 326                         stm_afr_set(&stm_gpioa, 5, STM_AFR_AF5);
 327                         stm_afr_set(&stm_gpioa, 6, STM_AFR_AF5);
 328                         stm_afr_set(&stm_gpioa, 7, STM_AFR_AF5);
 329                         break;
 330                 case AO_SPI_1_PB3_PB4_PB5:
 331                         stm_afr_set(&stm_gpiob, 3, STM_AFR_AF5);
 332                         stm_afr_set(&stm_gpiob, 4, STM_AFR_AF5);
 333                         stm_afr_set(&stm_gpiob, 5, STM_AFR_AF5);
 334                         break;
 335                 case AO_SPI_1_PE13_PE14_PE15:
 336                         stm_afr_set(&stm_gpioe, 13, STM_AFR_AF5);
 337                         stm_afr_set(&stm_gpioe, 14, STM_AFR_AF5);
 338                         stm_afr_set(&stm_gpioe, 15, STM_AFR_AF5);
 339                         break;
 340                 }
 341                 break;
 342         case STM_SPI_INDEX(2):
 343                 switch (spi_index) {
 344                 case AO_SPI_2_PB13_PB14_PB15:
 345                         stm_afr_set(&stm_gpiob, 13, STM_AFR_AF5);
 346                         stm_afr_set(&stm_gpiob, 14, STM_AFR_AF5);
 347                         stm_afr_set(&stm_gpiob, 15, STM_AFR_AF5);
 348                         break;
 349                 case AO_SPI_2_PD1_PD3_PD4:
 350                         stm_afr_set(&stm_gpiod, 1, STM_AFR_AF5);
 351                         stm_afr_set(&stm_gpiod, 3, STM_AFR_AF5);
 352                         stm_afr_set(&stm_gpiod, 4, STM_AFR_AF5);
 353                         break;
 354                 }
 355                 break;
 356         }
 357 }
 358
 359 void
 360 ao_spi_get(uint8_t spi_index, uint32_t speed)
 361 {
 362         uint8_t         id = AO_SPI_INDEX(spi_index);
 363         struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
 364
 365         ao_mutex_get(&ao_spi_mutex[id]);
 366         stm_spi->cr1 = ((0 << STM_SPI_CR1_BIDIMODE) |                   /* Three wire mode */
 367                         (0 << STM_SPI_CR1_BIDIOE) |
 368                         (0 << STM_SPI_CR1_CRCEN) |                      /* CRC disabled */
 369                         (0 << STM_SPI_CR1_CRCNEXT) |
 370                         (0 << STM_SPI_CR1_DFF) |
 371                         (0 << STM_SPI_CR1_RXONLY) |
 372                         (1 << STM_SPI_CR1_SSM) |                        /* Software SS handling */
 373                         (1 << STM_SPI_CR1_SSI) |                        /*  ... */
 374                         (0 << STM_SPI_CR1_LSBFIRST) |                   /* Big endian */
 375                         (1 << STM_SPI_CR1_SPE) |                        /* Enable SPI unit */
 376                         (speed << STM_SPI_CR1_BR) |     /* baud rate to pclk/4 */
 377                         (1 << STM_SPI_CR1_MSTR) |
 378                         (0 << STM_SPI_CR1_CPOL) |                       /* Format 0 */
 379                         (0 << STM_SPI_CR1_CPHA));
 380         if (spi_index != ao_spi_index[id]) {
 381
 382                 /* Disable old config
 383                  */
 384                 ao_spi_disable_index(ao_spi_index[id]);
 385
 386                 /* Enable new config
 387                  */
 388                 ao_spi_enable_index(spi_index);
 389
 390                 /* Remember current config
 391                  */
 392                 ao_spi_index[id] = spi_index;
 393         }
 394 }
 395
 396 void
 397 ao_spi_put(uint8_t spi_index)
 398 {
 399         uint8_t         id = AO_SPI_INDEX(spi_index);
 400         struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
 401
 402         stm_spi->cr1 = 0;
 403         ao_mutex_put(&ao_spi_mutex[id]);
 404 }
 405
 406 static void
 407 ao_spi_channel_init(uint8_t spi_index)
 408 {
 409         uint8_t         id = AO_SPI_INDEX(spi_index);
 410         struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
 411
 412         ao_spi_disable_index(spi_index);
 413
 414         stm_spi->cr1 = 0;
 415         (void) stm_spi->sr;
 416         stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
 417                         (0 << STM_SPI_CR2_RXNEIE) |
 418                         (0 << STM_SPI_CR2_ERRIE) |
 419                         (0 << STM_SPI_CR2_SSOE) |
 420                         (0 << STM_SPI_CR2_TXDMAEN) |
 421                         (0 << STM_SPI_CR2_RXDMAEN));
 422 }
 423
 424 void
 425 ao_spi_init(void)
 426 {
 427 #if HAS_SPI_1
 428 # if SPI_1_PA5_PA6_PA7
 429         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
 430         stm_ospeedr_set(&stm_gpioa, 5, SPI_1_OSPEEDR);
 431         stm_ospeedr_set(&stm_gpioa, 6, SPI_1_OSPEEDR);
 432         stm_ospeedr_set(&stm_gpioa, 7, SPI_1_OSPEEDR);
 433 # endif
 434 # if SPI_1_PB3_PB4_PB5
 435         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
 436         stm_ospeedr_set(&stm_gpiob, 3, SPI_1_OSPEEDR);
 437         stm_ospeedr_set(&stm_gpiob, 4, SPI_1_OSPEEDR);
 438         stm_ospeedr_set(&stm_gpiob, 5, SPI_1_OSPEEDR);
 439 # endif
 440 # if SPI_1_PE13_PE14_PE15
 441         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN);
 442         stm_ospeedr_set(&stm_gpioe, 13, SPI_1_OSPEEDR);
 443         stm_ospeedr_set(&stm_gpioe, 14, SPI_1_OSPEEDR);
 444         stm_ospeedr_set(&stm_gpioe, 15, SPI_1_OSPEEDR);
 445 # endif
 446         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SPI1EN);
 447         ao_spi_index[0] = AO_SPI_CONFIG_NONE;
 448         ao_spi_channel_init(0);
 449 #endif
 450
 451 #if HAS_SPI_2
 452 # if SPI_2_PB13_PB14_PB15
 453         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
 454         stm_ospeedr_set(&stm_gpiob, 13, SPI_2_OSPEEDR);
 455         stm_ospeedr_set(&stm_gpiob, 14, SPI_2_OSPEEDR);
 456         stm_ospeedr_set(&stm_gpiob, 15, SPI_2_OSPEEDR);
 457 # endif
 458 # if SPI_2_PD1_PD3_PD4
 459         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN);
 460         stm_ospeedr_set(&stm_gpiod, 1, SPI_2_OSPEEDR);
 461         stm_ospeedr_set(&stm_gpiod, 3, SPI_2_OSPEEDR);
 462         stm_ospeedr_set(&stm_gpiod, 4, SPI_2_OSPEEDR);
 463 # endif
 464         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_SPI2EN);
 465         ao_spi_index[1] = AO_SPI_CONFIG_NONE;
 466         ao_spi_channel_init(1);
 467 #endif
 468 }