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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include <ao.h>
  20 #include <ao_profile.h>
  21
  22 static void ao_profile_test(void)
  23 {
  24         uint8_t i;
  25         uint32_t        ticks[20];
  26
  27         for (i = 0; i < 20; i++) {
  28                 ticks[i] = ao_profile_tick();
  29                 ao_delay(0);
  30         }
  31         for (i = 0; i < 19; i++)
  32                 printf ("%d\n", ticks[i+1] - ticks[i]);
  33 }
  34
  35 static const struct ao_cmds ao_profile_cmds[] = {
  36         { ao_profile_test,      "P\0Test profile counter" },
  37         { 0, NULL }
  38 };
  39
  40 void ao_profile_init(void)
  41 {
  42         /* Turn on timer 2 and 4 */
  43         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM2EN) |
  44                 (1 << STM_RCC_APB1ENR_TIM4EN);
  45
  46         /* disable timers */
  47         stm_tim4.cr1 = 0;
  48         stm_tim2.cr1 = 0;
  49
  50         /* tim4 is master */
  51
  52
  53         stm_tim4.cr2 = ((0 << STM_TIM234_CR2_TI1S) |
  54                         (STM_TIM234_CR2_MMS_UPDATE << STM_TIM234_CR2_MMS) |
  55                         (0 << STM_TIM234_CR2_CCDS));
  56
  57         stm_tim4.smcr = ((0 << STM_TIM234_SMCR_ETP) |
  58                          (0 << STM_TIM234_SMCR_ECE) |
  59                          (STM_TIM234_SMCR_ETPS_OFF << STM_TIM234_SMCR_ETPS) |
  60                          (STM_TIM234_SMCR_ETF_NONE << STM_TIM234_SMCR_ETF) |
  61                          (0 << STM_TIM234_SMCR_MSM) |
  62                          (STM_TIM234_SMCR_TS_ITR3 << STM_TIM234_SMCR_TS) |
  63                          (0 << STM_TIM234_SMCR_OCCS) |
  64                          (STM_TIM234_SMCR_SMS_DISABLE << STM_TIM234_SMCR_SMS));
  65
  66         stm_tim4.dier = 0;
  67         stm_tim4.sr = 0;
  68
  69         stm_tim4.psc = 31;
  70         stm_tim4.cnt = 0;
  71         stm_tim4.arr = 0xffff;
  72
  73         /* tim2 is slaved to tim4 */
  74
  75         stm_tim2.cr2 = ((0 << STM_TIM234_CR2_TI1S) |
  76                         (STM_TIM234_CR2_MMS_ENABLE << STM_TIM234_CR2_MMS) |
  77                         (0 << STM_TIM234_CR2_CCDS));
  78         stm_tim2.smcr = ((0 << STM_TIM234_SMCR_ETP) |
  79                          (0 << STM_TIM234_SMCR_ECE) |
  80                          (STM_TIM234_SMCR_ETPS_OFF << STM_TIM234_SMCR_ETPS) |
  81                          (STM_TIM234_SMCR_ETF_NONE << STM_TIM234_SMCR_ETF) |
  82                          (0 << STM_TIM234_SMCR_MSM) |
  83                          (STM_TIM234_SMCR_TS_ITR3 << STM_TIM234_SMCR_TS) |
  84                          (0 << STM_TIM234_SMCR_OCCS) |
  85                          (STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK << STM_TIM234_SMCR_SMS));
  86         stm_tim2.dier = 0;
  87         stm_tim2.sr = 0;
  88         stm_tim2.psc = 0;
  89         stm_tim2.cnt = 0;
  90         stm_tim2.arr = 0xffff;
  91
  92         /* Start your timers */
  93
  94         stm_tim2.cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
  95                         (0 << STM_TIM234_CR1_ARPE) |
  96                         (STM_TIM234_CR1_CMS_EDGE | STM_TIM234_CR1_CMS) |
  97                         (STM_TIM234_CR1_DIR_UP << STM_TIM234_CR1_DIR) |
  98                         (0 << STM_TIM234_CR1_OPM) |
  99                         (0 << STM_TIM234_CR1_URS) |
 100                         (0 << STM_TIM234_CR1_UDIS) |
 101                         (1 << STM_TIM234_CR1_CEN));
 102
 103         stm_tim4.cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
 104                         (0 << STM_TIM234_CR1_ARPE) |
 105                         (STM_TIM234_CR1_CMS_EDGE | STM_TIM234_CR1_CMS) |
 106                         (STM_TIM234_CR1_DIR_UP << STM_TIM234_CR1_DIR) |
 107                         (0 << STM_TIM234_CR1_OPM) |
 108                         (1 << STM_TIM234_CR1_URS) |
 109                         (0 << STM_TIM234_CR1_UDIS) |
 110                         (1 << STM_TIM234_CR1_CEN));
 111
 112         ao_cmd_register(&ao_profile_cmds[0]);
 113 }