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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19
  20 struct ao_i2c_stm_info {
  21         uint8_t tx_dma_index;
  22         uint8_t rx_dma_index;
  23         struct stm_i2c  *stm_i2c;
  24 };
  25
  26 #define I2C_FAST        1
  27
  28 #define I2C_TIMEOUT     100
  29
  30 #define I2C_IDLE        0
  31 #define I2C_RUNNING     1
  32 #define I2C_ERROR       2
  33
  34 static uint8_t  ao_i2c_state[STM_NUM_I2C];
  35 static uint16_t ao_i2c_addr[STM_NUM_I2C];
  36 uint8_t         ao_i2c_mutex[STM_NUM_I2C];
  37
  38 # define I2C_HIGH_SLOW  5000    /* ns, 100kHz clock */
  39 #ifdef TELEMEGA
  40 # define I2C_HIGH_FAST  2000    /* ns, 167kHz clock */
  41 #else
  42 # define I2C_HIGH_FAST  1000    /* ns, 333kHz clock */
  43 #endif
  44
  45 # define I2C_RISE_SLOW  500     /* ns */
  46 # define I2C_RISE_FAST  100     /* ns */
  47
  48 /* Clock period in ns */
  49 #define CYCLES(period)  (((period) * (AO_PCLK1 / 1000)) / 1000000)
  50
  51 #define max(a,b)        ((a) > (b) ? (a) : (b))
  52 #define I2C_CCR_HIGH_SLOW       max(4,CYCLES(I2C_HIGH_SLOW))
  53 #define I2C_CCR_HIGH_FAST       max(4,CYCLES(I2C_HIGH_FAST))
  54 #define I2C_TRISE_SLOW          (CYCLES(I2C_RISE_SLOW) + 1)
  55 #define I2C_TRISE_FAST          (CYCLES(I2C_RISE_FAST) + 1)
  56
  57 #if I2C_FAST
  58 #define I2C_TRISE       I2C_TRISE_FAST
  59 #define I2C_CCR_HIGH    I2C_CCR_HIGH_FAST
  60 #else
  61 #define I2C_TRISE       I2C_TRISE_SLOW
  62 #define I2C_CCR_HIGH    I2C_CCR_HIGH_SLOW
  63 #endif
  64
  65 #if AO_PCLK1 == 2000000
  66 # define AO_STM_I2C_CR2_FREQ    STM_I2C_CR2_FREQ_2_MHZ
  67 #endif
  68 #if AO_PCLK1 == 4000000
  69 #  define AO_STM_I2C_CR2_FREQ   STM_I2C_CR2_FREQ_4_MHZ
  70 #endif
  71 #if AO_PCLK1 == 8000000
  72 # define AO_STM_I2C_CR2_FREQ    STM_I2C_CR2_FREQ_8_MHZ
  73 #endif
  74 #if AO_PCLK1 == 16000000
  75 # define AO_STM_I2C_CR2_FREQ    STM_I2C_CR2_FREQ_16_MHZ
  76 #endif
  77 #if AO_PCLK1 == 32000000
  78 # define AO_STM_I2C_CR2_FREQ    STM_I2C_CR2_FREQ_32_MHZ
  79 #endif
  80
  81 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) |      \
  82                         (0 << STM_I2C_CR1_ALERT) |      \
  83                         (0 << STM_I2C_CR1_PEC) |        \
  84                         (0 << STM_I2C_CR1_POS) |        \
  85                         (0 << STM_I2C_CR1_ACK) |        \
  86                         (0 << STM_I2C_CR1_STOP) |       \
  87                         (0 << STM_I2C_CR1_START) |      \
  88                         (0 << STM_I2C_CR1_NOSTRETCH) |  \
  89                         (0 << STM_I2C_CR1_ENGC) |       \
  90                         (0 << STM_I2C_CR1_ENPEC) |      \
  91                         (0 << STM_I2C_CR1_ENARP) |      \
  92                         (0 << STM_I2C_CR1_SMBTYPE) |    \
  93                         (0 << STM_I2C_CR1_SMBUS) |      \
  94                         (1 << STM_I2C_CR1_PE))
  95
  96 #define AO_STM_I2C_CR2  ((0 << STM_I2C_CR2_LAST) |                      \
  97                          (0 << STM_I2C_CR2_DMAEN) |                     \
  98                          (0 << STM_I2C_CR2_ITBUFEN) |                   \
  99                          (0 << STM_I2C_CR2_ITEVTEN) |                   \
 100                          (0 << STM_I2C_CR2_ITERREN) |                   \
 101                          (AO_STM_I2C_CR2_FREQ << STM_I2C_CR2_FREQ))
 102
 103 static const struct ao_i2c_stm_info     ao_i2c_stm_info[STM_NUM_I2C] = {
 104         {
 105                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
 106                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
 107                 .stm_i2c = &stm_i2c1
 108         },
 109         {
 110                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
 111                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
 112                 .stm_i2c = &stm_i2c2
 113         },
 114 };
 115
 116 static uint8_t  *ao_i2c_recv_data[STM_NUM_I2C];
 117 static uint16_t ao_i2c_recv_len[STM_NUM_I2C];
 118 static uint16_t ev_count;
 119
 120 static void
 121 ao_i2c_ev_isr(uint8_t index)
 122 {
 123         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 124         uint32_t        sr1;
 125
 126         ++ev_count;
 127         sr1 = stm_i2c->sr1;
 128         if (sr1 & (1 << STM_I2C_SR1_SB))
 129                 stm_i2c->dr = ao_i2c_addr[index];
 130         if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
 131                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
 132                 ao_i2c_state[index] = I2C_RUNNING;
 133                 ao_wakeup(&ao_i2c_state[index]);
 134         }
 135         if (sr1 & (1 << STM_I2C_SR1_BTF)) {
 136                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
 137                 ao_wakeup(&ao_i2c_state[index]);
 138         }
 139         if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
 140                 if (ao_i2c_recv_len[index]) {
 141                         *(ao_i2c_recv_data[index]++) = stm_i2c->dr;
 142                         if (!--ao_i2c_recv_len[index])
 143                                 ao_wakeup(&ao_i2c_recv_len[index]);
 144                 }
 145         }
 146 }
 147
 148 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
 149 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
 150
 151 static void
 152 ao_i2c_er_isr(uint8_t index)
 153 {
 154         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 155         uint32_t        sr1;
 156
 157         sr1 = stm_i2c->sr1;
 158         if (sr1 & (1 << STM_I2C_SR1_AF)) {
 159                 ao_i2c_state[index] = I2C_ERROR;
 160                 stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF);
 161                 ao_wakeup(&ao_i2c_state[index]);
 162         }
 163 }
 164
 165 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
 166 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
 167
 168 void
 169 ao_i2c_get(uint8_t index)
 170 {
 171         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 172         ao_mutex_get(&ao_i2c_mutex[index]);
 173
 174         stm_i2c->sr1 = 0;
 175         stm_i2c->sr2 = 0;
 176 }
 177
 178 void
 179 ao_i2c_put(uint8_t index)
 180 {
 181         ao_mutex_put(&ao_i2c_mutex[index]);
 182 }
 183
 184 uint8_t
 185 ao_i2c_start(uint8_t index, uint16_t addr)
 186 {
 187         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 188         uint32_t        sr1, sr2;
 189         int             t;
 190
 191         ao_i2c_state[index] = I2C_IDLE;
 192         ao_i2c_addr[index] = addr;
 193         stm_i2c->cr2 = AO_STM_I2C_CR2;
 194         stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START);
 195         for (t = 0; t < I2C_TIMEOUT; t++) {
 196                 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_START)))
 197                         break;
 198         }
 199         ao_alarm(AO_MS_TO_TICKS(250));
 200         ao_arch_block_interrupts();
 201         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
 202         ao_i2c_ev_isr(index);
 203         while (ao_i2c_state[index] == I2C_IDLE)
 204                 if (ao_sleep(&ao_i2c_state[index]))
 205                         break;
 206         ao_arch_release_interrupts();
 207         ao_clear_alarm();
 208         return ao_i2c_state[index] == I2C_RUNNING;
 209 }
 210
 211 static void
 212 ao_i2c_wait_stop(uint8_t index)
 213 {
 214         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 215         int     t;
 216
 217         for (t = 0; t < I2C_TIMEOUT; t++) {
 218                 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_STOP)))
 219                         break;
 220                 ao_yield();
 221         }
 222         ao_i2c_state[index] = I2C_IDLE;
 223 }
 224
 225 static void
 226 ao_i2c_wait_addr(uint8_t index)
 227 {
 228         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 229         int     t;
 230
 231         for (t = 0; t < I2C_TIMEOUT; t++)
 232                 if (!(stm_i2c->sr1 & (1 << STM_I2C_SR1_ADDR)))
 233                         break;
 234         if (t)
 235                 printf ("wait_addr %d\n", t);
 236 }
 237
 238 uint8_t
 239 ao_i2c_send(void *block, uint16_t len, uint8_t index, uint8_t stop)
 240 {
 241         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 242         uint8_t         *b = block;
 243         uint32_t        sr1;
 244         uint8_t         tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
 245         int             t;
 246
 247         /* Clear any pending ADDR bit */
 248         (void) stm_i2c->sr2;
 249         ao_i2c_wait_addr(index);
 250         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_DMAEN);
 251         ao_dma_set_transfer(tx_dma_index,
 252                             &stm_i2c->dr,
 253                             block,
 254                             len,
 255                             (0 << STM_DMA_CCR_MEM2MEM) |
 256                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 257                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 258                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 259                             (1 << STM_DMA_CCR_MINC) |
 260                             (0 << STM_DMA_CCR_PINC) |
 261                             (0 << STM_DMA_CCR_CIRC) |
 262                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 263
 264         ao_dma_start(tx_dma_index);
 265         ao_alarm(1 + len);
 266         ao_arch_block_interrupts();
 267         while (!ao_dma_done[tx_dma_index])
 268                 if (ao_sleep(&ao_dma_done[tx_dma_index]))
 269                         break;
 270         ao_clear_alarm();
 271         ao_dma_done_transfer(tx_dma_index);
 272         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
 273         while ((stm_i2c->sr1 & (1 << STM_I2C_SR1_BTF)) == 0)
 274                 if (ao_sleep(&ao_i2c_state[index]))
 275                         break;
 276         stm_i2c->cr2 = AO_STM_I2C_CR2;
 277         ao_arch_release_interrupts();
 278         if (stop) {
 279                 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
 280                 ao_i2c_wait_stop(index);
 281         }
 282         return TRUE;
 283 }
 284
 285 void
 286 ao_i2c_recv_dma_isr(int index)
 287 {
 288         int             i;
 289         struct stm_i2c  *stm_i2c = NULL;
 290
 291         for (i = 0; i < STM_NUM_I2C; i++)
 292                 if (index == ao_i2c_stm_info[i].rx_dma_index) {
 293                         stm_i2c = ao_i2c_stm_info[i].stm_i2c;
 294                         break;
 295                 }
 296         if (!stm_i2c)
 297                 return;
 298         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
 299         ao_dma_done[index] = 1;
 300         ao_wakeup(&ao_dma_done[index]);
 301 }
 302
 303 uint8_t
 304 ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
 305 {
 306         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 307         uint8_t         *b = block;
 308         int             t;
 309         uint8_t         ret = TRUE;
 310
 311         if (len == 0)
 312                 return TRUE;
 313         if (len == 1) {
 314                 ao_i2c_recv_data[index] = block;
 315                 ao_i2c_recv_len[index] = 1;
 316                 stm_i2c->cr1 = AO_STM_I2C_CR1;
 317
 318                 /* Clear any pending ADDR bit */
 319                 stm_i2c->sr2;
 320                 ao_i2c_wait_addr(index);
 321
 322                 /* Enable interrupts to transfer the byte */
 323                 stm_i2c->cr2 = (AO_STM_I2C_CR2 |
 324                                 (1 << STM_I2C_CR2_ITEVTEN) |
 325                                 (1 << STM_I2C_CR2_ITERREN) |
 326                                 (1 << STM_I2C_CR2_ITBUFEN));
 327                 if (stop)
 328                         stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
 329
 330                 ao_alarm(1);
 331                 ao_arch_block_interrupts();
 332                 while (ao_i2c_recv_len[index])
 333                         if (ao_sleep(&ao_i2c_recv_len[index]))
 334                                 break;
 335                 ao_arch_release_interrupts();
 336                 ret = ao_i2c_recv_len[index] == 0;
 337                 ao_clear_alarm();
 338         } else {
 339                 uint8_t         rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
 340                 ao_dma_set_transfer(rx_dma_index,
 341                                     &stm_i2c->dr,
 342                                     block,
 343                                     len,
 344                                     (0 << STM_DMA_CCR_MEM2MEM) |
 345                                     (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 346                                     (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 347                                     (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 348                                     (1 << STM_DMA_CCR_MINC) |
 349                                     (0 << STM_DMA_CCR_PINC) |
 350                                     (0 << STM_DMA_CCR_CIRC) |
 351                                     (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 352                 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK);
 353                 stm_i2c->cr2 = AO_STM_I2C_CR2 |
 354                         (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST);
 355                 /* Clear any pending ADDR bit */
 356                 (void) stm_i2c->sr2;
 357                 ao_i2c_wait_addr(index);
 358
 359                 ao_dma_start(rx_dma_index);
 360                 ao_alarm(len);
 361                 ao_arch_block_interrupts();
 362                 while (!ao_dma_done[rx_dma_index])
 363                         if (ao_sleep(&ao_dma_done[rx_dma_index]))
 364                                 break;
 365                 ao_arch_release_interrupts();
 366                 ao_clear_alarm();
 367                 ret = ao_dma_done[rx_dma_index];
 368                 ao_dma_done_transfer(rx_dma_index);
 369                 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
 370         }
 371         if (stop)
 372                 ao_i2c_wait_stop(index);
 373         return ret;
 374 }
 375
 376 void
 377 ao_i2c_channel_init(uint8_t index)
 378 {
 379         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 380         int i;
 381
 382         /* Turn I2C off while configuring */
 383         stm_i2c->cr1 = (1 << STM_I2C_CR1_SWRST);
 384         for (i = 0; i < 100; i++)
 385                 asm("nop");
 386         stm_i2c->cr1 = 0;
 387         stm_i2c->cr2 = AO_STM_I2C_CR2;
 388
 389         (void) stm_i2c->sr1;
 390         (void) stm_i2c->sr2;
 391         (void) stm_i2c->dr;
 392
 393         stm_i2c->sr1 = 0;
 394         stm_i2c->sr2 = 0;
 395
 396         stm_i2c->ccr = ((I2C_FAST << STM_I2C_CCR_FS) |
 397                         (0 << STM_I2C_CCR_DUTY) |
 398                         (I2C_CCR_HIGH << STM_I2C_CCR_CCR));
 399
 400         stm_i2c->trise = I2C_TRISE;
 401
 402         stm_i2c->cr1 = AO_STM_I2C_CR1;
 403 }
 404
 405 static inline void
 406 i2c_pin_set(struct stm_gpio *gpio, int pin)
 407 {
 408         stm_afr_set(gpio, pin, STM_AFR_AF4);
 409         stm_ospeedr_set(gpio, pin, STM_OSPEEDR_400kHz);
 410         stm_pupdr_set(gpio, pin, STM_PUPDR_PULL_UP);
 411 }
 412
 413 void
 414 ao_i2c_init(void)
 415 {
 416         /* All of the I2C configurations are on port B */
 417         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
 418 #if HAS_I2C_1
 419 # if I2C_1_PB6_PB7
 420         i2c_pin_set(&stm_gpiob, 6);
 421         i2c_pin_set(&stm_gpiob, 7);
 422 # else
 423 #  if I2C_1_PB8_PB9
 424         i2c_pin_set(&stm_gpiob, 8);
 425         i2c_pin_set(&stm_gpiob, 9);
 426 #  else
 427 #   error "No I2C_1 port configuration specified"
 428 #  endif
 429 # endif
 430
 431         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
 432         ao_i2c_channel_init(0);
 433
 434         stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
 435         stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, AO_STM_NVIC_MED_PRIORITY);
 436         stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
 437         stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, AO_STM_NVIC_MED_PRIORITY);
 438 #endif
 439
 440 #if HAS_I2C_2
 441 # if I2C_2_PB10_PB11
 442         i2c_pin_set(&stm_gpiob, 10);
 443         i2c_pin_set(&stm_gpiob, 11);
 444 # else
 445 #  error "No I2C_2 port configuration specified"
 446 # endif
 447         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
 448         ao_i2c_channel_init(1);
 449
 450         stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
 451         stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, AO_STM_NVIC_MED_PRIORITY);
 452         stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
 453         stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, AO_STM_NVIC_MED_PRIORITY);
 454 #endif
 455 }